JPH0855102A - Input state detecting circuit - Google Patents

Abstract

PURPOSE:To provide an input state detecting circuit capable of automatically setting up an external I/O terminal as an input terminal or an output terminal. CONSTITUTION:The input state detecting circuit for detecting the I/O state of an external I/O terminal 1 included in a semiconductor circuit and setting up the terminal 1 as an input terminal or an output terminal is provided with a pair of mutually different conductive transistors(TRs) 2, 3 serially connected between terminals to which different fixed potential Vcc, Vss to be impressed and connecting their node to the terminal 1, an external terminal 4 to which a prescribed signal for simultaneously turning on/off the TRs 2, 3 is to be applied, a judging circuit 9a for judging the potential of the terminal 1 and outputting its judged result, and a setting circuit 10a for receiving the judged result from the circuit 9a and setting up the terminal 1 as an input terminal or an output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor circuit,
The input state detection circuit that detects the data input state of the external input / output terminal and sets the external input / output terminal to the input terminal or the output terminal according to the detection result, and prevents the external input dedicated terminal from opening the input And an input state detection circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, external input / output terminals capable of inputting / outputting data are
Although it is necessary to set the input terminal or the output terminal for each terminal in advance, it is not possible to automatically set the input terminal or the output terminal for each terminal depending on the circuit configuration. Also, in the external input dedicated terminal, when the input is open, the voltage level of the input wiring from this terminal becomes a high impedance state, and if the semiconductor integrated circuit is operated with the input open, the noise entering from this terminal As a result, the input level changes inadvertently and easily between the H level and the L level, and the internal circuit may malfunction. However, conventionally, there was no mechanism for detecting the input state of the external input dedicated terminal by the internal circuit, so even if the semiconductor integrated circuit malfunctions due to the open state of the external input dedicated terminal, the cause is easily I could not identify.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in the first invention, a series transistor pair of different conductivity type in which external input / output terminals are connected to a connection point, An external terminal for simultaneously turning on / off this transistor pair, a determination circuit for determining the potential of the external input / output terminal, and a setting circuit for setting the external input / output terminal as an input terminal or an output terminal based on the determination result. An object of the present invention is to provide an input state detection circuit which can automatically set an external input / output terminal to an input terminal or an output terminal by providing the input / output terminal.

According to the second aspect of the invention, there is provided a first inverter which has a predetermined threshold value for output inversion and receives the potential of the external input / output terminal, and a second inverter which receives the first inverter. A discriminating circuit having a predetermined threshold value for inverting the output and including a third inverter that receives the potential of the external input / output terminal as an input, and a matching circuit that is input from the second inverter and the third inverter is provided. Accordingly, it is an object of the present invention to provide an input state detection circuit that can automatically set an external input / output terminal to an input terminal or an output terminal.

In the third invention, the setting circuit stores and holds the output value of the discrimination circuit when the external terminal is given a predetermined signal, and is provided in the semiconductor circuit when the signal is not given. A register that can be rewritten to a value from a data line, and an output buffer that performs operation switching control according to the value stored in the register and outputs data from the data line to the external input / output terminal when operating. By providing an input buffer that takes in the data from the external input / output terminal to the data line at the time of operation, an input state in which the setting to the external input / output terminal or the output terminal can be performed automatically or with a minimum program command An object is to provide a detection circuit. According to a fourth aspect of the present invention, by providing a resistor pair instead of a transistor pair, it is possible to provide an input state detection circuit that can set an external input / output terminal or an output terminal automatically or with a minimum program command. To aim.

According to the fifth aspect of the present invention, a series transistor pair of different conductivity types in which a terminal for exclusive use of external input is connected to a connection point, an external terminal for simultaneously turning on / off this transistor pair, and a potential of the terminal for exclusive use of external input are set. By providing a discriminating circuit for discriminating and a latch circuit for latching and outputting the output of the discriminating circuit according to a signal for turning on / off the transistor pair given to the external terminal, An object of the present invention is to provide an input state detection circuit capable of preventing a malfunction of a semiconductor circuit due to an input open state.

According to the sixth aspect of the invention, there is provided a first inverter having a predetermined threshold value for inverting the output, to which the potential of the external input dedicated terminal is inputted, and a second inverter inputted from the first inverter, A discriminating circuit including a third inverter having a predetermined threshold value for inverting the output and having the potential of the external input dedicated terminal as an input, and a matching circuit input from the second inverter and the third inverter is provided. Accordingly, it is an object of the present invention to provide an input state detection circuit capable of preventing a malfunction of a semiconductor circuit due to an input open state of an external input dedicated terminal. In the seventh invention, when the latch circuit outputs a signal indicating that the external input dedicated terminal is in the input open state, by providing a grounding means for grounding the external input dedicated terminal, the external input dedicated terminal is opened. It is an object of the present invention to provide an input state detection circuit capable of preventing a malfunction of a semiconductor circuit due to a state.

[0008]

In the input state detection circuit according to the first aspect of the present invention, a series transistor pair of different conductivity type in which an external input / output terminal is connected to a connection point and the transistor pair are turned on / off at the same time. And a discrimination circuit for discriminating the potential of the external input / output terminal and outputting the discrimination result, and setting the external input / output terminal as an input terminal or an output terminal in response to the discrimination result. And a setting circuit for setting.

In the input state detecting circuit according to the second aspect of the present invention, the discriminating circuit inverts the output higher than the first potential at the connection point of the transistor pair when the transistor pair is conductive and the external input / output terminals are open. A first inverter which has a threshold value of, and which receives the potential of the external input / output terminal as an input, a second inverter which is input from the first inverter, and a threshold value for output inversion lower than the first potential. And a third inverter which receives the potential of the external input / output terminal as an input, and a matching circuit which is input from the second inverter and the third inverter.

In the input state detection circuit according to the third aspect of the invention, the setting circuit stores and holds the output value of the discrimination circuit when a predetermined signal is given to the external terminal, and when the signal is not given, The semiconductor circuit is provided with a register that can be rewritten to a value from a data line, and an output buffer and an input buffer whose operation switching control is performed according to the value stored in the register. Output the data from the line to the external input / output terminal,
When the input buffer is operating, the data from the external input / output terminal is taken into the data line.

An input state detection circuit according to a fourth aspect of the invention is characterized in that the transistor pairs of different conductivity types are replaced with a pair of resistors.

The input state detection circuit according to the fifth aspect of the invention should be provided with a series transistor pair of different conductivity types in which a terminal dedicated to external input is connected to a connection point, and a signal for simultaneously turning on / off the transistor pair. It is characterized by comprising an external terminal, a discrimination circuit for discriminating the potential of the external input dedicated terminal and outputting the discrimination result, and a latch circuit for latching the output of the discrimination circuit with the signal and outputting it.

In the input state detection circuit according to the sixth aspect of the invention, the discriminating circuit performs the output inversion higher than the first potential at the connection point of the transistor pair when the transistor pair is conductive and the external input dedicated terminal is in the open state. A first inverter which has a threshold value of 1 and which receives the potential of the external input dedicated terminal as an input, a second inverter which is input from the first inverter, and a threshold value for output inversion lower than the first potential. A third inverter that has the potential of the external input dedicated terminal as an input;
And the matching circuit input from the third inverter.

The input state detection circuit according to the seventh aspect of the present invention comprises grounding means for grounding the external input dedicated terminal when the latch circuit outputs a signal indicating that the external input dedicated terminal is in an open state. Is characterized by.

[0015]

In the input state detection circuit according to the first aspect of the invention, when the transistor pair is turned on by the signal applied to the external terminal, the transistor pair is connected when the potential of the external input / output terminal is the first fixed potential. The potential at the point becomes the first fixed potential. When the potential of the external input / output terminal is the second fixed potential, the potential of the connection point of the transistor pair becomes the second fixed potential. When the external input / output terminal is open, the potential at the connection point of the transistor pair becomes an intermediate potential between the first fixed potential and the second fixed potential. The discrimination circuit discriminates from these potentials whether a fixed potential is applied to the external input / output terminal or is in an open state.When the discrimination result is a fixed potential, the setting circuit sets the external input / output terminal to the input terminal. , In the open state, set the external I / O pin as the output pin.

In the input state detection circuit according to the second invention, when the potential of the external input / output terminal is the first fixed potential, the first inverter is the second fixed potential, the second inverter is the first fixed potential, and the third fixed potential is the third fixed potential. Since the inverters output the second fixed potentials, the matching circuit outputs the second fixed potential. When the potential of the external input / output terminal is the second fixed potential, the first inverter outputs the first fixed potential, the second inverter outputs the second fixed potential, and the third inverter outputs the first fixed potential. The circuit also outputs the second fixed potential at this time. The determination circuit thereby determines that the fixed potential is applied to the external input / output terminal. When the external input / output terminal is open, the potential at the connection point of the transistor pair becomes an intermediate potential between the first fixed potential and the second fixed potential. As a result, the first inverter of the discrimination circuit outputs the first fixed potential, the second inverter outputs the second fixed potential, and the third inverter outputs the second fixed potential, so that the matching circuit outputs the first fixed potential. .
The determination circuit thereby determines that the external input / output terminal is in the open state.

In the input state detection circuit according to the third aspect of the invention, the register stores and holds the output value of the determination circuit when the external terminal is given a predetermined signal, and when the predetermined signal is not given, The value from the data line provided in the semiconductor circuit can be stored and held again. When the value stored in the register is the first fixed potential, the setting circuit operates the output buffer to set the external input / output terminal as the output terminal. When the value stored in the register is the second fixed potential, the setting circuit operates the input buffer to set the external input / output terminal as the input terminal.

In the input state detection circuit according to the fourth aspect of the present invention, when the potential of the external input / output terminal is the first fixed potential, the potential of the connection point of the resistor pair becomes the first fixed potential. When the potential of the external input / output terminal is the second fixed potential, the potential of the connection point of the resistor pair is the second fixed potential.
It becomes a fixed potential. When the external input / output terminal is open, the potential at the connection point of the resistor pair becomes an intermediate potential between the first fixed potential and the second fixed potential. The determination circuit determines from these potentials whether the fixed potential is applied to the external input / output terminal or the open state. The setting circuit accepts this discrimination result by a predetermined signal given to the external terminal, and when the discrimination result is a fixed potential, the external input / output terminal is the input terminal, and when it is open, the external input / output terminal is Set the terminal as an output terminal.

In the input state detection circuit according to the fifth aspect of the present invention, when the transistor pair is turned on by the signal applied to the external terminal, the transistor pair is connected when the potential of the external input dedicated terminal is the first fixed potential. The potential at the point becomes the first fixed potential. When the potential of the external input dedicated terminal is the second fixed potential, the potential of the connection point of the transistor pair becomes the second fixed potential. When the external input dedicated terminal is open, the potential at the connection point of the transistor pair becomes an intermediate potential between the first fixed potential and the second fixed potential. The discrimination circuit discriminates from these potentials whether the fixed potential is applied to the external input dedicated terminal or the open state, and outputs. The latch circuit latches the output of the determination circuit with a signal that turns on the transistor pair applied to the external terminal, and outputs the output with a signal that turns off the transistor pair applied to the external terminal.

In the input state detection circuit according to the sixth aspect of the invention, when the potential of the external input dedicated terminal is the first fixed potential, the first inverter is the second fixed potential, the second inverter is the first fixed potential, and the third fixed potential is the third fixed potential. Since the inverters output the second fixed potentials, the matching circuit outputs the second fixed potential. When the potential of the external input dedicated terminal is the second fixed potential, the first inverter outputs the first fixed potential, the second inverter outputs the second fixed potential, and the third inverter outputs the first fixed potential. The circuit also outputs the second fixed potential at this time. The determination circuit thereby determines that the fixed potential is applied to the external input dedicated terminal. When the external input dedicated terminal is open, the potential at the connection point of the transistor pair becomes an intermediate potential between the first fixed potential and the second fixed potential. As a result, the first inverter of the discrimination circuit outputs the first fixed potential, the second inverter outputs the second fixed potential, and the third inverter outputs the second fixed potential, so that the matching circuit outputs the first fixed potential. . The latch circuit latches the output of the determination circuit with a signal that turns on the transistor pair applied to the external terminal, and outputs the output with a signal that turns off the transistor pair applied to the external terminal.

In the input state detection circuit according to the seventh aspect of the present invention, when the latch circuit outputs a signal indicating that the external input dedicated terminal is in the input open state, the grounding means grounds the external input dedicated terminal.

[0022]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Example 1. FIG. 1 is a circuit diagram showing the configuration of one embodiment of an input state detection circuit according to the first to third inventions. In this input state detection circuit, the source is connected to the power supply potential Vcc, the drain is connected to the external input / output terminal 1, the P channel type FET 2 having a large ON resistance, the P channel type FET 2 has the same ON resistance, and the source is the ground potential Vss. And an N-channel FET 3 whose drain is connected to the external input / output terminal 1,
ON / OFF of channel type FET2 and N channel type FET3
The external terminal 4 to which a predetermined signal for turning off is given is N
It is connected to the gate of the channel-type FET 3 and also connected to the gate of the P-channel-type FET 2 via the inverter 5.

Further, an inverter 6 having a threshold value for output inversion higher than 1/2 of the power supply potential Vcc and having the potential of the external input / output terminal 1 as an input, and an inverter 7 having the output of the inverter 6 as an input. , An inverter 8 having a threshold value for output inversion lower than 1/2 of the power supply potential Vcc and having the potential of the external input / output terminal 1 as an input;
Ex. With each output of NOR circuit 9 (match circuit)
And a discrimination circuit 9a for discriminating the input / output state of the external input / output terminal 1.

In addition, Ex. The register 10 for storing the output value of the NOR circuit 9 or the value from the data line 12 and the switching control of the operation are performed by the value stored in the register 10, and during the operation (the input buffer 11a is cut off). An output buffer 11 that outputs the data from the data line 12 to the external input / output terminal 1, and an input buffer 11a that takes the data from the external input / output terminal 1 into the data line 12 during operation (the output buffer 11 is shut off). And Ex.
A setting circuit 10a for receiving the output from the NOR circuit 9 and setting the external input / output terminal 1 as an input terminal or an output terminal is provided. When a predetermined signal is input to the external terminal 4, the register 10 receives the Ex. The output value of the NOR circuit 9 is stored and held. When a predetermined signal is not input, the value output from the data line 12 is stored and held again when the program rewrite request signal WR is given.

The operation of the input state detection circuit having such a configuration will be described below. In a semiconductor integrated circuit, when a terminal is used as an input terminal, an H-level or L-level potential is externally applied to the terminal in advance, while when it is used as an output terminal, it is in a floating state (open state) in advance. I have to.

When operating the semiconductor integrated circuit, the external terminal 4 is used to set the terminal as an input terminal or an output terminal.
Then, for example, a reset signal (a signal for setting the semiconductor integrated circuit to the initial state) which is a pulse signal is given. This reset signal turns on the P-channel FET 2 and the N-channel FET 3. In this state, when the H-level potential (power supply potential Vcc) is applied to the external input / output terminal 1, no current flows in the P-channel FET 2,
Due to the on-resistance of the N-channel FET3, both FET2,
The potential at the common connection point of the drains of 3 becomes H level. When the potential at the common connection point of the drains of both FETs 2 and 3 is H level, the inverter 6 outputs L level (ground potential Vss), the inverter 7 outputs H level, and the inverter 8 outputs L level. The NOR circuit 9 outputs L level.
The register 10 receives the reset signal from the Ex. The L level output of the NOR circuit 9 is stored and held, the input buffer 11a is operated (the output buffer 11 is cut off), and the external input / output terminal 1 is set as an input terminal.

When an L-level potential is applied to the external input / output terminal 1, no current flows in the N-channel type FET 3 and both FETs are turned on by the ON resistance of the P-channel type FET 2.
The potential at the common connection point of the drains 2 and 3 becomes L level. The potential at the common connection point of the drains of both FETs 2 and 3 is L
At the time of level, the inverter 6 is at H level and the inverter 7
Output L level and the inverter 8 outputs H level,
Ex. The NOR circuit 9 outputs L level. Register 1
0 is set to E by the reset signal given to the external terminal 4.
x. The L level output of the NOR circuit 9 is stored and held, the input buffer 11a is operated (the output buffer 11 is shut off), and the external input / output terminal 1 is set as the input terminal.

When the potential of the external input / output terminal 1 is in a floating state, the P-channel type FET 2 and the N-channel type F
A current flows in ET3, and the potential at the common connection point of the drains of both FETs 2 and 3 becomes an intermediate potential between the H level and the L level due to the distributed voltage of the ON resistance of both FETs 2 and 3. Both F
When the potential at the common connection point of the drains of ET2 and 3 is an intermediate potential between the H level and the L level, depending on the respective threshold values,
Since the inverter 6 outputs H level, the inverter 7 outputs L level, and the inverter 8 outputs L level, Ex. The NOR circuit 9 outputs H level. The register 10 receives the reset signal from the Ex. The H level output of the NOR circuit 9 is stored and held, and the output buffer 11
Is activated (the input buffer 11a is cut off), and the external input / output terminal 1 is set as an output terminal.

No reset signal is given to the external terminal 4,
When the P-channel type FET 2 and the N-channel type FET 3 are turned off, the penetrating current of the P-channel type FET 2 and the N-channel type FET 3 does not flow. Also, the register 10 holds the value at the time of inputting the reset signal, and the Ex. N
The output of the OR circuit 9 is not accepted, but when the rewrite request signal WR is given from the program, the data line 12
The value from is stored and retained again.

FIG. 2 is a circuit diagram showing a configuration example of the register 10. This register 10 has Ex. NOR circuit 9
Output line and data line 12 are connected to the D terminal via the buffers 35 and 36, respectively, and the external terminal 4 and the program signal line (WR) are connected to the clock terminal CK via the OR circuit 37. 38
It is composed of The Q terminal output of the D-type flip-flop 38 is supplied to the output buffer 11, and the inverted output of the Q terminal is supplied to the input buffer 11a, and the operation of the output buffer 11 and the input buffer 11a is switched and controlled. Further, the external terminal 4 and the program signal line (WR) are also connected to the buffer 35 and the buffer 36, respectively, and control the operation of the buffer 35 and the buffer 36 to open or to open the input / output terminals.

The operation of the register 10 will be described with reference to the time chart of the signal waveforms of the respective parts shown in FIG.
This will be described below. When the reset signal is input to the external terminal 4 (FIG. 3 (a)), the buffer 35 is activated and the output signal of the determination circuit (the output signal of the Ex.NOR circuit 9) (FIG. 3 (b)) is output. Input to D terminal and OR
An H level signal is input to the clock terminal CK through the circuit 37, and the D-type flip-flop 38 stores and holds the output signal (FIG. 3B) of the determination circuit (FIG. 3C). The stored value is output from the Q terminal and output buffer 1
1 and the operation of the input buffer 11a are switched and controlled.

When the reset signal is not input to the external terminal 4 (FIG. 3 (a)), the input / output terminals of the buffer 35 are open, and the output signal of the discrimination circuit is not input to the D terminal. In this state, when the program rewrite request signal WR is given (FIG. 3D), the buffer 3
6 is activated and the value from the data line 12 (see FIG.
(E)) is input to the D terminal, and an H level signal is input to the clock terminal CK through the OR circuit 37.
The type flip-flop 38 receives the value from the data line 12 (see FIG.
(E)) is stored and held (FIG. 3 (c)). This stored and held value is output from the Q terminal, and the operation of the output buffer 11 and the input buffer 11a is switched and controlled.

Example 2. FIG. 4 is a circuit diagram showing the configuration of an embodiment of the input state detection circuit according to the fourth invention. In this input state detection circuit, in the configuration of the input state detection circuit according to the first to fourth aspects of the invention, the P-channel FET 2 and the inverter 5 are connected at one end to the power supply potential Vcc and at the other end to the external input / output terminal 1. The resistance Rd is replaced with a resistance Rd (Ru = R) whose one end is connected to the ground potential Vss and the other end is connected to the external input / output terminal 1.
The configuration is replaced with d). Other configurations are
Since the configuration is the same as that of the input state detection circuit according to the first to fourth inventions shown in FIG. 1, the description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. In a semiconductor integrated circuit, when a terminal is used as an input terminal, an H-level or L-level potential is externally applied to the terminal in advance, while when it is used as an output terminal, it is set in a floating state in advance.

When operating the semiconductor integrated circuit, the external terminal 4 is used to set the terminal as an input terminal or an output terminal.
To the reset signal, which is a pulse signal, for example.
In this state, when an H-level potential (power supply potential Vcc) is applied to the external input / output terminal 1, no current flows through the resistor Ru, and the potential at the common connection point of the resistors Ru and Rd is changed by the resistor Rd. It becomes H level. When the potential at the common connection point between the resistors Ru and Rd is at the H level, the inverter 6 outputs the L level (ground potential Vss), the inverter 7 outputs the H level, and the inverter 8 outputs the L level. The NOR circuit 9 outputs L level. The register 10 receives the reset signal from the Ex. L of NOR circuit 9
The level output is stored and held, the input buffer 11a is operated (the output buffer 11 is cut off), and the external input / output terminal 1 is set as the input terminal.

When an L level potential is applied to the external input / output terminal 1, no current flows through the resistor Rd and the resistor Ru
As a result, the potential at the common connection point of the resistors Ru and Rd becomes L level. When the potential at the common connection point of both resistors Ru and Rd is at L level, the inverter 6 is at H level and the inverter 7 is at L level.
Level, the inverter 8 outputs H level, so E
x. The NOR circuit 9 outputs L level. Register 10
Is reset by the reset signal given to the external terminal 4.
x. The L level output of the NOR circuit 9 is stored and held, the input buffer 11a is operated (the output buffer 11 is shut off), and the external input / output terminal 1 is set as the input terminal.

When the potential of the external input / output terminal 1 is in a floating state, a current flows through the resistors Ru and Rd, and the common connection point of the resistors Ru and Rd is generated by the distribution voltage of the resistors Ru and Rd (Ru = Rd). Potential becomes an intermediate potential between H level and L level. When the potential at the common connection point of the resistors Ru and Rd is an intermediate potential between the H level and the L level, the inverter 6 outputs the H level, the inverter 7 outputs the L level, and the inverter 8 outputs the L level according to the respective threshold values. Ex. The NOR circuit 9 outputs H level. The register 10 receives the reset signal from the Ex. The H level output of the NOR circuit 9 is stored and held, and the output buffer 11 is operated (input buffer 11a
Is cut off), and the external input / output terminal 1 is set as an output terminal.

When the reset signal is not input to the external terminal 4, the register 10 holds the value at the time of the most recent reset signal input, and the Ex. The output of the NOR circuit 9 is not accepted, but when the rewrite request signal WR is given from the program, it is stored and held again in the value from the data line 12.

Example 3. FIG. 5 is a circuit diagram showing the configuration of the first embodiment of the input state detection circuit according to the fifth and sixth inventions. In this input state detection circuit, the source is the power supply potential Vcc.
In addition, the P-channel FET2 having a drain connected to the external input-only terminal 13 has the same on-resistance as the P-channel FET2, the source connected to the ground potential Vss, and the drain connected to the external-input dedicated terminal 13 A FET 3 and a P-channel FET 2 and an N-channel FET
An external terminal 4 to which a reset signal for turning on / off 3 (a signal for setting the semiconductor integrated circuit to an initial state) is given is connected to the gate of the N-channel FET 3 and a P-channel via an inverter 5. Connected to the gate of the FET2.

Further, an inverter 6 having a threshold value for output inversion higher than 1/2 of the power supply potential Vcc and having the potential of the external input dedicated terminal 13 as an input, and an inverter 7 having the output of the inverter 6 as an input. , An inverter 8 having a threshold value for output inversion lower than 1/2 of the power supply potential Vcc and having the potential of the external input dedicated terminal 13 as an input, and an inverter 8 having inputs of the outputs of the inverter 7 and the inverter 8. A NOR circuit 9 (coincidence circuit) is provided and a discrimination circuit 9a for discriminating the input state of the external input dedicated terminal 13 is provided.

Ex. The output node of the NOR circuit 9 is connected to the drain, the gate is connected to the N-channel FET 15 to which the reset signal line from the external terminal 4 is connected, and the gate is connected to the bar reset signal line from the external terminal 4 to P.
A transmission gate in which a channel type FET 16 is connected in parallel, a P channel type FET 19 in which a gate is connected to a reset signal line from the external terminal 4, and an N channel type FET 20 in which a gate is connected to a bar reset signal line from an external terminal 4 Are connected in parallel, two inverters 17 and 18 connected in opposite directions between the two transmission gates, and an inverter 21 in which an input node is connected to the drain of a P-channel type FET 19. The latch circuit 14 is provided which latches the output of the circuit 9a with a reset signal applied to the external terminal 4 and outputs the latched signal after turning off the reset signal.

The operation of the input state detection circuit having such a configuration will be described below. In the semiconductor integrated circuit, the H-level or L-level potential must be externally applied to the external input-only terminal in advance. When operating the semiconductor integrated circuit, a reset signal which is, for example, a pulse signal is applied to the external terminal 4 in order to check whether an H level or L level potential is applied to the external input dedicated terminal. This reset signal turns on the P-channel FET 2 and the N-channel FET 3. In this state, when an H-level potential is applied to the external input-only terminal 13, no current flows in the P-channel FET 2 and the drains of both FETs 2 and 3 are commonly connected by the ON resistance of the N-channel FET 3. The potential at the point becomes H level.

When the potential at the common connection point of the drains of both FETs 2 and 3 is at the H level, the inverter 6 outputs the L level, the inverter 7 outputs the H level, and the inverter 8 outputs the L level. The NOR circuit 9 outputs L level. At this time, due to the reset signal, the transmission gate including the FETs 15 and 16 is open, the L level is input to the inverter 18, and the inverter 18 outputs the H level. In this state, when the reset signal of the external terminal 4 is turned off, the transmission gate formed of the FETs 15 and 16 is closed, the transmission gate formed of the FETs 19 and 20 is opened, and the H level is output from the inverter 18. Since 17 is connected, this H level output is held. Therefore,
The inverter 21 keeps receiving the H level and continues to output the L level. Therefore, the latch circuit 14 outputs the Ex. N
The L level output of the OR circuit 9 is latched.

When an L-level potential is applied to the external input-only terminal 13, no current flows through the N-channel type FET 3 and the on-resistance of the P-channel type FET 2 causes both F
The potential at the common connection point of the drains of ET2 and ET3 becomes L level. When the potential at the common connection point of the drains of both FETs 2 and 3 is L level, the inverter 6 outputs H level, the inverter 7 outputs L level, and the inverter 8 outputs H level. The NOR circuit 9 outputs L level. This is the same as when the H-level potential is applied to the external input dedicated terminal 13 described above, and at this time also, the latch circuit 14 operates the Ex. The L level output of the NOR circuit 9 is latched. Therefore, when the H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 14 outputs the L level.

When the potential of the external input-only terminal 13 is in a floating state, a current flows through the P-channel FET 2 and the N-channel FET 3, and the drain voltage of both FETs 2 and 3 is shared by the distribution voltage of the ON resistance of both FETs 2 and 3. The potential at the connection point becomes an intermediate potential between H level and L level.
When the potential at the common connection point of the drains of both FETs 2 and 3 is an intermediate potential between the H level and the L level, the inverter 6 outputs the H level, the inverter 7 outputs the L level, and the inverter 8 outputs the L level according to the respective threshold values. , Ex. N
The OR circuit 9 outputs H level. At this time, the transmission signal formed by the FETs 15 and 16 is opened by the reset signal, the H level is input to the inverter 18, and the inverter 18 outputs the L level.

In this state, when the reset signal of the external terminal 4 is turned off, the transmission gate formed of the FETs 15 and 16 is closed, the transmission gate formed of the FETs 19 and 20 is opened, and the L level is output from the inverter 18. However, since the inverter 17 is connected, this L level output is held. Therefore,
The inverter 21 continues to receive the L level and continues to output the H level.
The H level output of the NOR circuit 9 is latched. Therefore,
When the potential of the external input dedicated terminal 13 is in a floating state, the latch circuit 14 outputs H level. Thus, by checking the output level of the latch circuit 14, the input open state of the external input dedicated terminal 13 can be found quickly.

Example 4. FIG. 6 is a circuit diagram showing the configuration of the second embodiment of the input state detection circuit according to the fifth and sixth inventions. The input state detection circuit inputs the output signal of the inverter 21 of the latch circuit 14 to the interrupt terminal of the CPU 23. Other configurations are the same as the configurations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. When an H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 1
4 outputs an L level. At this time, the CPU 23 is not interrupted. When the potential of the external input dedicated terminal 13 is in a floating state, the latch circuit 14 outputs H level. At this time, the CPU 23 is interrupted, and the CPU 23 executes necessary processing such as fail safe by the interrupt. The other operations are the same as the operations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore the description thereof will be omitted. According to this embodiment, the CPU 23
Can automatically check the input state of the external input dedicated terminal 13 when the semiconductor integrated circuit rises from the reset state.

Example 5. FIG. 7 is a circuit diagram showing the configuration of the third embodiment of the input state detection circuit according to the fifth and sixth inventions. This input state detection circuit inputs the output signal of the inverter 21 of the latch circuit 14 to the status register 24. Other configurations are the same as the above-mentioned fifth and fifth.
Since the configuration is the same as that of the first embodiment of the input state detection circuit according to the sixth invention, the description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. When an H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 1
4 outputs an L level. The L level is input to the status register 24. At this time, the status register 24 does not set the status flag and the status flag is at the L level. When the potential of the external input dedicated terminal 13 is in a floating state, the latch circuit 14 outputs H level. At this time, the status register 24 is
The H level is input, and the status register 24 sets the status flag to the H level. Other operations are
Since the operation is the same as that of the first embodiment of the input state detecting circuit according to the fifth and sixth inventions, the description thereof will be omitted. In this embodiment, the input state of the external input dedicated terminal 13 can be checked by reading the value of the status flag.

Example 6. FIG. 8 is a circuit diagram showing the configuration of the fourth embodiment of the input state detection circuit according to the fifth and sixth inventions. This input state detection circuit inputs the output signal of the inverter 21 of the latch circuit 14 to one input terminal of the NOR circuit 26, and the output of the NOR circuit 26 is input to the oscillation circuit 27 of the internal clock of the semiconductor integrated circuit. Oscillation circuit 27
It is designed to start / stop. To the other input terminal of the NOR circuit 26, the input terminal 25 for the stop command signal of the oscillation circuit 27 is connected. Other configurations are the same as the configurations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. When an H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 1
4 outputs an L level, and the L level is input to one input terminal of the NOR circuit 26. Since the stop command signal of the oscillator circuit 27 is normally at L level, the NOR circuit 26 outputs H level. At this time, the oscillation circuit 27 oscillates. When the potential of the external input-only terminal 13 is in a floating state, the latch circuit 14 outputs H level and N
The H level is input to one input terminal of the OR circuit 26. Since the stop command signal of the oscillation circuit 27 is normally at L level, the NOR circuit 26 outputs L level. At this time, the oscillation circuit 27 stops the oscillation.

When the stop command of the oscillation circuit 27 is executed, the stop command signal becomes H level. At this time,
Since the H level or L level potential is applied to the external input dedicated terminal 13 and the latch circuit 14 outputs the L level, the NOR circuit 26 outputs the L level. At this time, the oscillation circuit 27 stops the oscillation. Other operations are
Since the operation is the same as that of the first embodiment of the input state detecting circuit according to the fifth and sixth inventions, the description thereof will be omitted. In this embodiment, the internal clock oscillation circuit 27 of the semiconductor integrated circuit is not oscillated and the semiconductor integrated circuit is not operated unless the floating state of the potential of the external input dedicated terminal 13 is eliminated. Therefore, it is possible to prevent the semiconductor integrated circuit from operating in the presence of the external input-only terminal 13 whose potential is in a floating state.

Example 7. FIG. 9 is a circuit diagram showing the configuration of the fifth embodiment of the input state detection circuit according to the fifth and sixth inventions. The input state detection circuit inputs the output signal of the inverter 21 of the latch circuit 14 to the program counter 28 of the computer to control the program execution of the computer. Other configurations are the same as the configurations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. When an H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 1
4 outputs the L level, and the L level is input to the program counter 28. At this time, the program counter 28
Does not stop and the program continues to run. When the potential of the external input dedicated terminal 13 is in a floating state, the latch circuit 14 outputs H level, and the program counter 2
The H level is input to 8. At this time, the program counter 28 is stopped and the execution of the program is interrupted. In this state, when the floating state of the potential of the external input dedicated terminal 13 is released, the latch circuit 14 outputs the L level, the L level is input to the program counter 28, the program counter 28 is activated, and the program is executed. It is executed from where it was interrupted. The other operations are the same as the operations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore the description thereof will be omitted. In this embodiment, it is possible to prevent the semiconductor integrated circuit (of the computer) from operating in the presence of the external input-only terminal 13 whose potential is floating.

Example 8. FIG. 10 is a circuit diagram showing the configuration of the sixth embodiment of the input state detection circuit according to the fifth and sixth inventions. In this input state detection circuit, the wiring of the power supply Vcc is separated from the wiring of the power supply Vcc of the internal circuit 30 other than the input state detection circuit, and the output of the inverter 21 of the latch circuit 14 is supplied to the internal circuit 30 and the power supply Vcc. The drain and source are connected to the gate of a P-channel FET 29 to which the drain and source are connected, and the output of the latch circuit 14 controls the power supply to the internal circuit 30. Other configurations are
Since the configuration is the same as that of the first embodiment of the input state detection circuit according to the fifth and sixth inventions, the description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. When an H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 1
4 outputs an L level, the P-channel FET 29 is turned on, and power is supplied from the power supply Vcc to the internal circuit 30.
When the potential of the external input dedicated terminal 13 is in a floating state, the latch circuit 14 outputs an H level, the P-channel FET 29 is turned off, and the power supply from the power supply Vcc to the internal circuit 30 is cut off. The other operations are the same as the operations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore the description thereof will be omitted. In the present embodiment, it is possible to prevent the semiconductor integrated circuit from operating in the presence of the external input-only terminal 13 whose potential is floating.

Example 9. FIG. 11 is a circuit diagram showing the configuration of a seventh embodiment of the input state detection circuit according to the fifth and sixth inventions. In this input state detection circuit, the reset signal input to the external terminal 4a is given only from the outside, and the output of the inverter 21 of the latch circuit 14 is O.
It is input to one input terminal of the R circuit 31, and the OR circuit 31
Is output to the internal circuit 30 as an internal reset signal. A conventional internal reset signal of the internal circuit 30 is input to the other input terminal 32 of the OR circuit 31. Other configurations are the same as the configurations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. When an H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 1
4 outputs an L level. Since the conventional internal reset signal is normally at L level, the output of the OR circuit 31 (internal reset signal) becomes L level, and the internal circuit 30 is not reset. When the potential of the external input-only terminal 13 is in the floating state, the latch circuit 14 outputs H level, so the output of the OR circuit 31 (internal reset signal) becomes H level and the internal circuit 30 is reset. When the conventional internal reset signal of H level is input to the other input terminal 32 of the OR circuit 31, the output of the OR circuit 31 (internal reset signal) becomes H level, and the internal circuit 30 is reset. The other operations are the same as the operations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore the description thereof will be omitted. In the present embodiment, it is possible to prevent the semiconductor integrated circuit from operating in the presence of the external input-only terminal 13 whose potential is floating.

Example 10. FIG. 12 is a circuit diagram showing the configuration of an embodiment of the input state detection circuit according to the seventh invention.
In this input state detection circuit, the output of the inverter 21 of the latch circuit 14 is connected to the external input dedicated terminal 13 and the gate of the N-channel FET 22 whose source is connected to the ground potential Vss. Other configurations are the same as the configurations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore description thereof will be omitted.

The operation of the input state detection circuit having such a configuration will be described below. In the semiconductor integrated circuit, the H-level or L-level potential must be externally applied to the external input-only terminal in advance. When operating the semiconductor integrated circuit, the external terminal 4 is used to check whether an H level or L level potential is applied to the external input dedicated terminal.
To the reset signal, which is a pulse signal, for example.
This reset signal causes the P-channel FET 2 and N
The channel FET 3 is turned on.

When an H level or L level potential is applied to the external input dedicated terminal 13, the latch circuit 14 is set to L level.
Output level. At this time, the N-channel FET 22
An L level potential is applied to the gate of the N channel type FET 22 and the N channel type FET 22 is not turned on. Therefore, the external input dedicated terminal 1
3 is maintained at the already applied H level or L level potential. When the potential of the external input dedicated terminal 13 is in a floating state, the latch circuit 14 outputs H level. At this time, H is applied to the gate of the N-channel FET 22.
A level potential is applied, and the N-channel FET 22 turns on. Therefore, the external input dedicated terminal 13 is grounded and the floating state is eliminated. The other operations are the same as the operations of the first embodiment of the input state detection circuit according to the fifth and sixth inventions described above, and therefore the description thereof will be omitted.

[0063]

According to the input state detection circuit of the first aspect of the present invention, it is possible to realize an input state detection circuit which can automatically set an external input / output terminal to an input terminal or an output terminal.

According to the input state detection circuit of the second aspect of the present invention, it is possible to realize an input state detection circuit which can automatically set an external input / output terminal to an input terminal or an output terminal.

According to the input state detection circuit of the third aspect of the present invention, it is possible to realize an input state detection circuit which can set an external input / output terminal to an input terminal or an output terminal automatically or with a minimum program command. You can

According to the input state detection circuit of the fourth aspect of the present invention, the input state detection circuit which can set the external input / output terminal to the input terminal or the output terminal automatically or with a minimum program command is realized at low cost. can do.

According to the input state detection circuit of the fifth aspect of the present invention, it is possible to realize the input state detection circuit capable of preventing the malfunction of the semiconductor circuit due to the input open state of the external input dedicated terminal.

According to the input state detection circuit of the sixth aspect of the present invention, it is possible to realize the input state detection circuit capable of preventing the malfunction of the semiconductor circuit caused by the input open state of the external input dedicated terminal.

According to the input state detecting circuit of the seventh invention, when the latch circuit outputs a signal indicating that the external input dedicated terminal is in the input open state, the external input dedicated terminal is grounded. It is possible to prevent the malfunction of the semiconductor circuit due to the input open state of the dedicated terminal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of an input state detection circuit according to the first to third inventions.

FIG. 2 is a circuit diagram showing a configuration example of a register.

FIG. 3 is a time chart for explaining the operation of the register.

FIG. 4 is a circuit diagram showing a configuration of an embodiment of an input state detection circuit according to a fourth invention.

FIG. 5 shows a first input state detection circuit according to fifth and sixth inventions.
3 is a circuit diagram showing the configuration of the embodiment of FIG.

FIG. 6 is a second input state detection circuit according to the fifth and sixth inventions.
3 is a circuit diagram showing the configuration of the embodiment of FIG.

FIG. 7 is a third input state detection circuit according to the fifth and sixth inventions.
3 is a circuit diagram showing the configuration of the embodiment of FIG.

FIG. 8 is a fourth diagram of the input state detection circuit according to the fifth and sixth inventions.
3 is a circuit diagram showing the configuration of the embodiment of FIG.

FIG. 9 is a fifth example of the input state detection circuit according to the fifth and sixth inventions.
3 is a circuit diagram showing the configuration of the embodiment of FIG.

FIG. 10 is a circuit diagram showing a configuration of a sixth embodiment of an input state detection circuit according to the fifth and sixth inventions.

FIG. 11 is a circuit diagram showing a configuration of a seventh embodiment of an input state detection circuit according to the fifth and sixth inventions.

FIG. 12 is a circuit diagram showing a configuration of one embodiment of an input state detection circuit according to the seventh invention.

[Explanation of symbols]

1 external input / output terminal, 2 P-channel FET, 3 N
Channel type FET, 4, 4a external terminal, 5-8 inverter, 9 Ex. NOR circuit (matching circuit), 9a discrimination circuit, 10 register, 10a setting circuit, 11 output buffer, 11a input buffer, 12 data line,
13 external input dedicated terminal, 14 latch circuit, 22 N
Channel type FET (grounding means), Rd, Rd resistance, V
cc Power supply potential, Vss ground potential.

Claims (7)

[Claims] 1. An input state detection circuit for detecting an input / output state of an external input / output terminal of a semiconductor circuit and setting the external input / output terminal as an input terminal or an output terminal, wherein terminals to which different fixed potentials should be applied A transistor pair of different conductivity type connected in series between the external input / output terminals and an external terminal to which a signal for simultaneously turning on / off the transistor pair should be given; A determination circuit that determines the potential of the output terminal and outputs the determination result; and a setting circuit that receives the determination result of the determination circuit and sets the external input / output terminal as an input terminal or an output terminal. Input state detection circuit. 2. The discrimination circuit has a threshold value for output reversal higher than a first potential at a connection point of the transistor pair when the transistor pair is on and the external input / output terminal is open, A first inverter that receives the potential of the input / output terminal and a second inverter that receives the output of the first inverter
Third inverter having a threshold value for output inversion lower than the first potential and receiving the potential of the external input / output terminal as an input.
2. The input state detection circuit according to claim 1, further comprising: an inverter and a matching circuit that receives the outputs of the second inverter and the third inverter as inputs. 3. The setting circuit stores and holds the output value of the discrimination circuit when the external terminal is given a signal for simultaneously turning on / off the transistor pair, and when the signal is not given, The semiconductor circuit is provided with a register that can be rewritten to a value from a data line, and an output buffer and an input buffer whose operation switching control is performed according to the value stored in the register. 3. The input state according to claim 1, wherein the data from the line is output to the external input / output terminal, and the data from the external input / output terminal is taken into the data line when the input buffer operates. Detection circuit. 4. The input state detection circuit according to claim 1, wherein the transistor pairs of different conductivity types are replaced with a pair of resistors. 5. An input state detection circuit for detecting an input state of an external input dedicated terminal included in a semiconductor circuit, wherein the input state dedicated detection circuit is connected in series between terminals to which different fixed potentials should be applied, and the external input dedicated terminal is provided at the connection point. A pair of connected transistors of different conductivity types, an external terminal to which a signal for turning on / off the pair of transistors at the same time should be given, and a judgment circuit for judging the potential of the external input dedicated terminal and outputting the judgment result. A latch circuit for latching an output of the discrimination circuit by a signal for turning on the transistor pair given to the external terminal and outputting the signal by a signal for turning off the transistor pair. State detection circuit. 6. The discriminating circuit has a threshold value for output inversion higher than a first potential at a connection point of the transistor pair when the transistor pair is turned on and the external input-only terminal is opened, 1st with the potential of the input-only terminal as the input
A second inverter that receives the output of the first inverter and a third inverter that has a threshold value for output inversion lower than the first potential and that receives the potential of the external input dedicated terminal as an input. The input state detection circuit according to claim 5, further comprising: an inverter; and a matching circuit that receives the outputs of the second inverter and the third inverter as inputs. 7. The latch circuit comprises grounding means for grounding the external input dedicated terminal when a signal indicating that the external input dedicated terminal is in an input open state is output. 6. The input state detection circuit according to item 6.