JPH0855068A - Communication terminal equipment - Google Patents

Abstract

PURPOSE:To provide a communication terminal with which a program can be speedily updated at low cost. CONSTITUTION:This equipment is provided for a system equipped with a down line load function to perform required processing by executing a main program(MPRG) with a CPU, to enable the exchange of data(DT) by providing a communicating means 5 for exchanging the data with a communication line and to update the MPRG by fetching the MPRG to be updated transmitted from the host side through the communication line through the communicating means and storing it in a main memory in the case of updating the MPRG. Therefore, this equipment is provided with a flash memory(FLM) 2 and a RAM 3 consisting of the main memory of a CPU 1, the FLM is divided into an area for main program and an area for backup(BA) for the unit of a memory area so as to enable batch erasure, and the CPU is provided with a processing function for fetching the received DT into the RAM of the main memory when performing down line load from the communication line, function for writing the received DT on the RAM into the BA of the FLM and function for writing the received DT in this BA into the area for main program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication terminal device using a CPU, and more particularly to a communication terminal device of a system in which a main program for controlling the device is downloaded from a host side and updated.

[0002]

2. Description of the Related Art In recent communication terminals, CP is at the center of control.
A U (microprocessor) is used, and it is possible to realize complicated and highly intelligent functions by software control by executing a program by the CPU.

The main program for controlling the communication terminal device is becoming more and more complicated due to the further multifunctionalization of the device and the diversification of network services. Along with this, addition of functions to the operating communication terminal and The main program is often updated due to a program mistake (hereinafter referred to as a program bug).

As a method of updating the program, a read-only memory (hereinafter referred to as a ROM) in which a new program has been written is conventionally used as an old ROM in a communication terminal device.
Change by exchanging with (for the method of using ROM), or use a rewritable memory or disk device, etc., and transfer the main program to the RAM in the communication terminal device through the communication line (hereinafter, this There is a method of rewriting and updating the main program on the RAM (in the case of the download method to the main memory).

To explain the latter specific method, the communication terminal device has a rewritable random access memory (hereinafter referred to as RAM) as a main memory and an execution program for booting (hereinafter referred to as boot ROM). Since a hard disk is connected as an external storage device, the startup is performed by loading the main program stored in this hard disk by executing the boot ROM and then executing the main program. In this case, the downline loading is performed, and the communication terminal device updates the main program by rewriting the main program of the hard disk to the downline loaded one.

[0006]

As described above, in the communication terminal device which performs the control operation by the main program, when the main program needs to be changed, the main program is converted into the ROM in the conventional technique. In the communication terminal device in which the main program is read from the hard disk and placed in the RAM by replacing the ROM in which the new main program is written, the communication is performed from the host side via the communication line. Downline loading is performed on the terminal device, the downline loaded main program is saved from the communication terminal device to the hard disk, and the main program is loaded from the hard disk to the RAM by the boot ROM program at the time of starting the device, and the main program is stored on the RAM. It is common to adopt the method of executing a program There was.

[0007] However, the former method requires on-site replacement work for the operating communication terminal, resulting in high work cost and inconvenient quick response, and the latter method is mainly used. Although there is an advantage that the program can be changed without going to the site, there is a problem that the device cost becomes high because it is necessary to have a main program holding device such as a hard disk.

Therefore, the object of the present invention is to make it possible to quickly change the main program, and
It is to provide a communication terminal device that can be realized at low cost.

[0009]

In order to achieve the above object, the present invention is configured as follows. That is, the main program is executed by the CPU to perform the required processing, and a communication means for exchanging data with the communication line is provided to enable the exchange of data, and at the time of updating the main program, A communication terminal device having a downline load function, wherein a main program to be updated transmitted from a host side via a communication line can be obtained and updated by a downline load function fetched via the communication means. Includes a flash memory and a random access memory that constitute the main memory of the CPU, and the flash memory is divided into a main program area and a backup area in batch erasable memory area units. When downline loading from the communication line, the received data is stored in the main memory The processing function to load the random access memory into the random access memory, the function to write the received data in the random access memory to the backup area of the flash memory, and the received data in the backup area of this flash memory as the main program area of this flash memory. And the function of writing to.

Secondly, a flash memory and a random access memory which constitute the main memory of the CPU are provided, and the flash memory has a main program area, a backup area, a flag in batch erasable memory area units. In addition to dividing into areas, the CPU has
When downline loading from the communication line, a function to process the received data in the random access memory in the main memory, a function to write the received data in the random access memory to the backup area of the flash memory, and a backup of this flash memory A function to write the received data of the area to the main program area of this flash memory, and the information indicating that the processing has been performed when these processings proceed, is written to the flag area of the flash memory as history status information. It was configured with the function to save in.

[0011]

In the first configuration, when downline loading is performed from the communication line, the CPU fetches the received data in the random access memory in the main memory. Then, the CPU writes the received data on the random access memory to the backup area of the flash memory to back it up, and then writes the received data on the backup area of the flash memory to the main program area of this flash memory.

In the present invention, the main memory of the CPU is composed of a flash memory and a random access memory, and the flash memory is divided into a main program area and a backup area in units of memory areas that can be collectively erased. When downline loading is performed from the communication line, the received data is loaded into the random access memory in the main memory, this received data is written to the backup area of the flash memory, and then the received data on this backup area is written. , The main program area of this flash memory is written and the update is completed. By writing the received data in the backup area of the flash memory in this way, even if a power failure occurs during the program update, the updated data will not be lost, and the retransmission of the updated data from the host side will be minimized. Will be able to.

Further, since the flash memory is used as the main memory and the main program is held in the flash memory, an external storage device or the like is not required and the system cost can be reduced.

Further, in the second configuration, when downline loading is performed from the communication line, the received data is
The CPU loads the random access memory in the main memory. Then, the CPU writes the received data on the random access memory to the backup area of the flash memory to back it up, and then writes the received data on the backup area of the flash memory to the main program area of this flash memory.
Further, the CPU writes process history information in the flag area of the flash memory at each stage of the process at this time.

In the present invention, the main memory of the CPU is composed of a flash memory and a random access memory, and the flash memory is divided into a main program area and a backup area in units of memory areas that can be collectively erased. When downline loading is performed from the communication line, the received data is loaded into the random access memory in the main memory, this received data is written to the backup area of the flash memory, and then the received data on this backup area is written. , The main program area of this flash memory is written and the update is completed.

When these processes are carried out, the information indicating that the processes have been carried out is written and saved in the flag area of the flash memory as history status information. Therefore, when the system is started up, the history in the flag area is saved. Check the status information, check which stage of processing is completed, and execute the main program according to that stage.
Transferring the received data in the backup area to the main program area and re-execution of downline load will cause a runaway due to insufficient update processing when updating the main program. In addition to avoiding the risk of causing such problems, writing the received data to the backup area of the flash memory makes it possible to avoid losing the updated data even if a power failure occurs during the program update. It will be possible to minimize the retransmission of update data from.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. To explain the features of the present invention,
In the present invention, when updating the main program,
In order to hold the main program received from the host side via the communication line, a flash memory and a random access memory (RA) are used as the main memory of the CPU without using a large capacity external storage device such as a hard disk device.
M) and the received data are fetched into the RAM and further fetched into the flash memory, so that the main program can be updated even without a large capacity external storage device.

The program for transferring the updated data at the time of downline loading to the main memory is a read-only memory (R
OM), and by causing the CPU to execute this, it becomes possible to execute the process of transferring the update data to the main memory, and the flash memory is a main program area in batch erasable memory area units. , The backup area, the flag area, and when downline loading from the communication line, the received data is loaded into the RAM in the main memory, and then the transfer program on the ROM is used to transfer the data to the CPU on the random access memory. The received data of the above is written in the backup area of the flash memory, and then the received data in this backup area is controlled to be written in the area for the main program, and the processing was performed when these processings proceeded. Is used as the history status information and the flag area of the flash memory is The process of storing written into and to be performed.

Then, when the system is started up, the history status information in the flag area is checked to see at which stage the processing is completed, and depending on the stage, the main program is executed and the received data in the backup area is received. Perform either the transfer to the main program area or the re-execution of downline load to avoid the risk of a runaway due to insufficient update processing when updating the main program. I made it possible.

Further, in the present invention, the main program is stored in a flash memory (a large-capacity semiconductor memory element capable of electrically erasing and writing electrically), and the flash memory is used in a predetermined storage area unit. Since it is possible to electrically erase the stored data collectively (hereinafter referred to as a block), when updating the main program as well, update in units of the above blocks, and do not update the blocks that have not been changed. Only a certain block is downline loaded.

As a result, the update can be performed within the minimum necessary range, and the efficient update processing can be performed. The transfer program of the ROM first transfers the block-unit received data (data to be updated sent from the host side) in the RAM to the backup area which is an empty area of the flash memory, and then the same data block. It is a program that controls to transfer to the corresponding block of the main program that actually needs to be changed.

In this system, the update data is received from the host side by downline loading and is updated and stored in the flash memory that constitutes the main memory. However, during a series of operations until the update is stored, the system is terminated abnormally due to a power failure or the like. In order to prevent the data from being destroyed, write various history in the operation process as flags in the flag area provided on the flash memory for each operation step, and check which flag is set When an abnormal end occurs during updating of update data, this flag and the update data left in the backup area of the flash memory are used so that it is possible to know in what state the interruption has occurred Even in the case of restoration, the update data is restored and the update data is properly replaced. As it is Rukoto, it is doing to protect the system.

Therefore, according to the present invention, by the main program in the flash memory for the main memory, the update data of the main program received in block units via the communication line is once transferred to the RAM, and then on the ROM. Is executed to transfer the data block in RAM to the backup area of the flash memory for the main memory and then to the block that needs to be changed in the actual main program. The downline loading of the main program can be performed each time.

The present invention will be specifically described. FIG. 1 is a block diagram showing a system configuration example of a communication terminal device of the present invention. This figure shows a configuration example of a system in which a CPU is used as a control center, and shows main components. In FIG. 1, reference numeral 1 is a CPU (microprocessor), 2 is a flash memory that can be electrically erased and written electrically, and occupies a part of the main memory (main memory) of the present CPU system.
It is prepared to store the main program etc. to be executed by 1. The flash memory 2 has a relatively large capacity and
Since the reading speed is high, the conventional ROM is used as the main memory.
Ideal for replacing from.

Reference numeral 3 is a working area and a memory used for temporarily holding data when the program is executed.
It is composed of a RAM (Random Access Memory) and temporarily stores a part (data block) of the received program at the time of downline loading.
The RAM 3 is an essential memory for constructing a system of a communication terminal device having a CPU as a center, and is not dedicated to downline loading but is positioned as a part of main memory. Since it is a general-purpose memory that is diverted, the cost of the system does not increase, and efficient use of memory resources can be achieved.

Reference numeral 4 denotes a ROM, which is a read-only memory in which a program for transferring the data block to the flash memory 2 at the time of downline loading is stored. The ROM 4 is a ROM dedicated to the downline load program, but since the function of the program is dedicated to data transfer in the CPU system, it may be a small capacity memory.

Reference numeral 5 denotes a line control circuit, which serves as an interface with a communication line and a modem, and can exchange data and commands with the host side system and other communication terminals via the communication line. .

Reference numeral 6 denotes an operation unit, which is provided with keys such as command keys and data keys for input operation. Then, by inputting a key of the operation unit 6, C
A command or the like can be given to PU1.

Reference numeral 7 denotes a display unit for performing necessary display under the control of the CPU 1. FIG. 2 is an example showing a memory area division structure of the flash memory 2. The use of the flash memory 2 is determined as follows in units of batch erasable of the flash memory. That is, as shown in FIG. 2, the batch erasable units of the flash memory are A1, A2, ... An, ...
Assuming An + 1 and An + 2, n blocks from A1 to An are used as data blocks for storing the main program, and An + 1 is a backup area used to temporarily hold update data when downline loading, and An + 2 is The configuration is used as a flag area for keeping the history of downline load as history.

The main program is divided into n pieces, and each of the divided main programs is sequentially stored in n data blocks 1 to n from A1 to An. Since the main program usually consists of a set of software divided into a plurality of tasks, if a program modification etc. occurs, only a part of the software set (program module) needs to be modified. However, in most cases, the program is updated only by modifying one block.

That is, since the main program is usually divided into a plurality of tasks and handled as software modules, if a program modification occurs, the module that needs to be reworked among the software modules is modified. In addition, it can be replaced with that module.

In the case of the flash memory 2, the memory area is divided into areas of a predetermined memory size, and the storage data can be collectively erased in the area-divided units. Since the data can be written in order, if the main program is divided into modules according to the block structure as shown in FIG. You can complete the update by erasing the contents in 2 batch erasing unit and replacing it with a new module, you do not need to update the whole, just replace part of it, so it is convenient for downline loading is there. Further, this is also efficient in using the memory structure and the communication line.

In this system, the update data is received from the host side by the downline load and is updated and stored in the flash memory 2 which constitutes the main memory. However, due to an abnormal termination due to a power failure or the like during a series of operations until the update is stored. In order to prevent the system from being destroyed, various history in the operation process is written as a flag in the flag area provided in the memory area of the flash memory 2 for each operation step, and which flag is set, By making it possible to know in what state the interruption occurred in the case of abnormal termination during operation, and by using this flag and the update data left in the backup area of the flash memory 2, an abnormality during update of the update data can be obtained. Even when the end occurs, the update data is restored and placed correctly in the update data. As can changing is performed to protect the system.

Here, the operation of the downline load is shown in FIG.
And it demonstrates in detail with reference to the flowchart of FIG. First, when the update data of the main program is received (downline loaded) through the communication line, the CPU 1 once writes the received main program in the RAM 3 (step 102). If the reception is abnormal, the CPU 1 terminates abnormally, and the CPU 1 restarts the downline loading from the beginning (step 103).

When the reception is normally completed, the CPU 1
Sets a backup start flag in the flag area in the flash memory 2 (step 104). Since the flash memory 2 cannot read the internal data in the data erase / write state, this setting is CP
The transfer program is stored in advance in the ROM 4 of the U system, and the transfer program of the ROM 4 is stored in the CP.
This is done by causing U 1 to execute. Also, RO
In addition to the transfer program, M4 may include a startup program before execution of the updated main program.

When the downline load is executed, the CP
U 1 executes the transfer program and transfers the update data of the main program stored in RAM 3 to the backup area of flash memory 2 (step 10).
5). Since the update data can be transferred to the backup area in units of data blocks of the flash memory 2, it is only necessary to transfer the modified data blocks. With this, for the backup area of the flash memory 2,
Finish storing the update data. This is a safety measure to prevent loss of updated data due to power failure or malfunction.

After the transfer is normally completed, the CPU 1 sets a transfer flag in the flag area (step 106). Next, the CPU 1 writes the update data to the data block in the flash memory 2. This corresponds to the official data update processing stage for the data block in the flash memory 2. That is, CPU 1 is RA
The update data held in M 3 is read, and the read update data is transferred to the data block to be actually updated in the flash memory 2 (step 10).
7). As a result, the update data in the RAM 3 can be transferred to the actually updated data block in the flash memory 2 while the update data in the RAM 3 is secured in the backup area of the flash memory 2 for backup.

When the transfer ends normally, the CPU
1 sets an end flag in the flag area in the flash memory 2 to complete the downline loading (step 108).

After the completion of the downline loading, the system is switched to the main memory and restarted, and the updating of the main program is completed. As described above, in the present system, the update data is received from the host side by the downline load and is updated and stored in the flash memory 2 that constitutes the main memory, but abnormal termination due to a power failure or the like occurs during a series of operations until the update is stored. In order to prevent the system from being damaged by the above, various history in the operation process is written as a flag in the flag area provided in the memory area of the flash memory 2 for each operation step, and which flag is set By making it possible to know in what state the interruption occurred in the case of abnormal termination during operation, and by using this flag and the update data left in the backup area of the flash memory 2, an abnormality during update of the update data can be obtained. Even when the end occurs, restore the updated data and place it correctly in the updated data. As can be obtained, it is carried out to protect the system.

By performing the following operation from the state of this flag when the power is turned on, it is possible to prevent the system from running out of control when the main program is not successfully updated, and to start it after the correct update. Is possible.

The operation will be described below. First, when the power is turned on, the CPU 1 executes the system diagnostic routine of the main program, checks the flag area in the flash memory 2, and checks whether the end flag is ON. As a result of checking the end flag, the CPU 1 determines that the previous downline load is normally completed when the end flag is ON, and normally executes the main program in the data block in the flash memory 2. Program operation of
Step 202).

If the end flag is not turned on here,
The CPU 1 determines that the process is interrupted during the downline load, and proceeds to step 203. Then, in the process of step 203, the CPU 1 confirms the transfer flag of the flag area in the flash memory 2, and if the transfer flag is ON, determines that the update process is interrupted during the update of the data block, and the flash memory Update data in the backup area in 2 is temporarily stored in RAM
3 (step 206). When the transfer is completed, the CPU 1 then repeats the processing from step 107 again.

In the processing in step 203, the CPU
In No. 1, if the transfer flag of the flag area in the flash memory 2 is OFF, the process proceeds to step 204, and the backup flag of the flag area in the flash memory 2 is confirmed.

As a result, when the backup flag is ON, it is determined that the backup is interrupted. That is, it is determined that the processing is interrupted while the update data is being transferred from the RAM 3 days to the backup area in the flash memory 2. Then, the CPU 1 ends abnormally. In this case, it is necessary to restart the downline loading of update data from the beginning.

When redoing the downline load from the beginning, the host side is requested to retransmit the update data. This request is automatically sent to the CPU 1 when the startup fails.
Or manually by operating the communication terminal device.

On the other hand, when the backup flag is OFF in the processing of step 204, the CPU
1 judges that downline loading has not been implemented,
The normal program is executed (that is, the main program in the data block in the flash memory 2 is executed).

By this start-up operation, when a downline load is carried out, even if an abnormal termination occurs due to a power failure or the like, runaway can be prevented and the system can be surely protected. Become.

As described above, in this embodiment, the flash memory and the RAM are used as the main memory, the program for transferring the update data at the time of downline loading to the main memory is stored in the ROM, and the flash memory is It is divided into a main program area, a backup area, and a flag area in batch erasable memory area units, and when downline loading is performed from the communication line, the received data is loaded into the RAM in the main memory and then on the ROM. The transfer program is used to write the received data on the RAM to the backup area of the flash memory, and then the program on the ROM is used to write the received data in the backup area of the flash memory to the main program area. When proceeding with the processing of Information indicating that the process was carried out as history status information, and so as to write and save the flash memory flag area. Then, when the system is started up, the history status information in the flag area is checked to see which stage of processing has been completed, and depending on that stage, the main program is executed and the backup area receive data for the main program is used. Either transfer to the area or execute re-execution of downline load so that the risk of runaway etc. can be avoided when updating the main program due to insufficient update processing. did.

Further, since the data to be updated is stored in the backup area, if there is no abnormality in the processing up to this storage, the host system updates the main program without down-loading the updated data. I was able to do it. In addition, the update data is updated in units of memory areas of the flash memory that can be erased collectively. Therefore, when updating the main program, the amount of data to be updated can be minimized, efficient data transfer can be performed, and update data is performed in batch erasable memory area units of the flash memory. Therefore, the processing at the time of updating can be efficiently performed. Further, since the RAM area of the main memory is used to receive the update data, there is no need for an external storage device or the like, and there is an advantage that the system cost can be kept low.

Therefore, according to the present apparatus, the system can be constructed at a low cost, and by saving the backup and each operating state, it is possible to check the system destruction due to the power failure during the system updating, and the reliability is improved. In addition to the improvement of the communication efficiency, it is possible to significantly improve the maintainability of the communication terminal device. It should be noted that the present invention is not limited to the above-described embodiments, and can be carried out by being modified appropriately within the scope of the invention.

[0051]

As described above, according to the present invention, it is possible to inexpensively construct a system for a communication terminal device that updates a main program or the like by downline loading, and to use backup and By saving the operating state, it is possible to check the system damage due to a power failure during the system update, which improves the reliability and also has the advantage that the maintainability of the communication terminal device can be greatly improved.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention,
It is an example which shows a part of CPU system of the communication terminal device of this invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention,
The figure which shows the example of a division structure of the flash memory applied to this invention.

FIG. 3 is a diagram for explaining an embodiment of the present invention,
The flowchart for demonstrating the downline load of this invention.

FIG. 4 is a diagram for explaining an embodiment of the present invention,
The flowchart for demonstrating the system protection operation | movement of this invention.

[Explanation of symbols]

 1 ... CPU 2 ... Flash memory 3 ... RAM 4 ... ROM 5 ... Line control circuit

Claims (6)

[Claims] 1. A main program is executed by a CPU to perform required processing, and a communication means for exchanging data with a communication line is provided to enable data exchange.
Further, when updating the main program, the main program to be updated, which is transmitted from the host side via the communication line, can be obtained and updated by the downline load function that takes in through the communication means. In a communication terminal device having a function, the main memory of the CPU is capable of electrically erasing stored information in batches in units of predetermined storage areas, and is capable of random access and a first memory capable of writing and reading information. A second memory, and the first memory is a main program area in units of memory areas that can be collectively erased;
In addition to dividing the backup area, the CPU has a processing function of loading the received data into the random access memory in the main memory when performing the downline load from the communication line, and the received data on the random access memory. A communication terminal device characterized by being provided with a function of writing to a backup area of the memory and a function of writing the reception data of the backup area of the first memory to a main program area of the first memory. . 2. A main program is executed by a CPU to perform required processing, and a communication means for exchanging data with a communication line is provided to enable data exchange.
Further, when updating the main program, the main program to be updated, which is transmitted from the host side via the communication line, can be obtained and updated by the downline load function that takes in through the communication means. In a communication terminal device having a function, a flash memory and a random access memory forming a main memory of the CPU are provided, and the flash memory is divided into a main program area and a backup area in batch erasable memory area units, The CPU has a processing function of loading received data into a random access memory in a main memory when performing downline loading from a communication line, and a function of writing the received data on the random access memory into a backup area of a flash memory. This hula Receiving data of the backup area Shumemori - a data communication terminal apparatus, characterized in that which is configured by providing a function of writing in the main program area of the flash memory. 3. A CPU executes a main program to perform a required process, and a communication means for transferring data to and from a communication line is provided to enable data transfer.
Further, when updating the main program, the main program to be updated, which is transmitted from the host side via the communication line, can be obtained and updated by the downline load function that takes in through the communication means. In a communication terminal device having a function, a flash memory and a random access memory that constitute the main memory of the CPU are provided, and the flash memory is divided into a main program area, a backup area, and a flag area in batch erasable memory area units. At the same time, the CPU has a processing function of loading the received data into the random access memory in the main memory when performing downline loading from the communication line, and writing the received data in the random access memory to the backup area of the flash memory. function , A function for writing the reception data of the backup area of this flash memory to the main program area of this flash memory, and the information indicating that the processing has been carried out when these processings proceed, A communication terminal device, comprising: a function of writing and storing in a flag area of a memory. 4. The CPU has a function of referring to history status information in a flag area of the flash memory to determine whether or not the main program update process is interrupted before executing the main program. 4. A function for restarting downline loading is provided.
The communication terminal device described. 5. The CPU has a function of determining whether or not the main program update process is interrupted by referring to history status information in a flag area of the flash memory before executing the main program. A function to write the received data to the main program area of the flash memory when the received data is in the backup area of the flash memory, and downline load when there is no received data in the backup area when the interruption occurs 4. The communication terminal device according to claim 3, further comprising a function of restarting the communication terminal. 6. The main program is configured as a block corresponding to the electrically batch erasable memory area unit of a flash memory, and when the CPU is downline loaded, the main program is 4. The communication terminal device according to claim 2, further comprising a function of controlling to update in block units.