JPH0855015A - Arithmetic unit for floating point number - Google Patents

Abstract

PURPOSE:To reduce the hardware amount of an arithmetic unit for executing the addition, subtraction, multiplication and division of floating point numbers. CONSTITUTION:In the case of floating point addition and subtraction, two mantissas for which digits are matched by a swapper 15 and a right shifter 16 are supplied through first and second mantissa selectors 17 and 18 and two pieces of one-bit right shifters 19 and 20 to an adder-subtractor 21 and added and subtracted in the adder-subtractor 21 and the result is rounded. In the case of floating point multiplication and divison, an intermediate sum S and a carry C outputted from a multiplier 24 are supplied through the first and second mantissa selectors 17 and 18 and two pieces of the one-bit right shifters 19 and 20 to the adder-subtractor 21 and added in the adder-subtractor 21 and the result is rounded. The rounded result of the adder-subtractor 21 is passed through a priority encoder 22 and a left shifter 23 and outputted as the normalized mantissa. Exponents are processed by exponent computing units 11, 13 and 14 and an exponent selector 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for performing addition, subtraction, multiplication and division of floating point numbers.

[0002]

2. Description of the Related Art In recent years, a floating point arithmetic operation unit, which has been required to have high speed in accordance with scientific and technical calculations and complicated graphic processing, responds to this request by operating a plurality of arithmetic units in parallel. It was On the other hand, in microcontrollers used for embedded applications and the like, the demand for high-speed arithmetic is increasing, but in order to reduce costs, it is not possible to use arithmetic arithmetic units having a plurality of arithmetic units. Therefore, there is a need for a floating-point arithmetic operation device that realizes a plurality of types of arithmetic operations with a small amount of hardware.

US Pat. No. 4,866,652 describes
An arithmetic unit for floating point arithmetic of the form (A × B) + C is disclosed. In this device, the two multiplexers and the right shifter that constitute the mantissa digit matching means for addition and subtraction are arranged in the subsequent stage of the multiplier. On the other hand, it is obtained by multiplying the n-bit mantissa by the m-bit mantissa (n
Rounding the product of + m) bits to n bits yields the n-bit product mantissa. Previously, US Pat. No. 4,866,65
Rounding was done inside the mantissa multiplier, as shown in the prior art in No. 2. A configuration is also possible in which a rounding bit generator is provided inside the mantissa multiplier and the higher n bits of the product of (n + m) bits and the generated rounding bit are output from the mantissa multiplier. Are known.

By the way, IEEE (the Institute of E
The Electrical and Electronics Engineers) 754 standard defines an expression format of a 32-bit single precision floating point number consisting of a 1-bit code S, an 8-bit exponent E, and a 23-bit fractional part F. Usually, a floating-point number that has been normalized so that the virtual non-zero value bit and the decimal point are positioned higher than the most significant bit (MSB) of the decimal part F is used. However, the bias B is given to the actual index so that the index E is a positive number. In the case of single precision, 2 ⁷ −1 is set as the bias B for the actual index.
= 127 is set as an index E. That is, the real number R expressed as a single-precision normalized number (normalized number) is R = (− 1) ^S 2 ^E-127 (1.F) (1). However, in the formula (1), 1. F is called the mantissa M.

The exponent of the multiplicand operand or the exponent of the dividend operand is an n-bit first exponent X, and the exponent of the multiplier operand or the divisor operand is an n-bit second exponent.
, And the bias of the index is B = 2 ^(n-1) -1
And The actual calculation of the exponent at the time of multiplication is (X−B) + (Y−B) = (X + Y−B) −B (2). That is, the exponent with bias to be obtained in the case of multiplication is X + Y-B. The actual calculation of the exponent at the time of division is (X−B) − (Y−B) = (X−Y + B) −B (3). That is, the exponent with bias to be obtained in the case of division is XY + B.

Japanese Unexamined Patent Publication (Kokai) No. 4-328630 discloses a structure of an exponent arithmetic unit for obtaining the product exponent X + Y-B and the quotient exponent X-Y + B by one adder.

[0007]

The above-mentioned US Pat. No. 4,8
The arithmetic unit for floating-point arithmetic in the form of (A × B) + C disclosed in Japanese Patent No. 66,652 has a single addition A since the means for aligning the mantissa is arranged after the multiplier.
It was not suitable for + B or single subtraction AB. Further, in the configuration in which the rounding is performed inside the multiplier or the rounding bit generating device is provided inside the multiplier, there is a problem that the hardware amount of the multiplier increases as a result.

Further, the exponential arithmetic unit disclosed in the above-mentioned Japanese Patent Laid-Open No. 4-328630 has a problem that the exponential processing in the case of addition and subtraction cannot be executed.

It is an object of the present invention to provide an arithmetic operation unit with a small amount of hardware suitable for executing single addition, single subtraction, single multiplication and single division of floating point numbers.

Another object of the present invention is to provide an exponential arithmetic unit which can be used for addition, subtraction, multiplication and division.

[0011]

In the first and second arithmetic operation units according to the present invention, the exponent and the mantissa of the augend operand or the exponent and the mantissa of the minuend operand are used as the exponent and the mantissa of the first operand, respectively. The exponent and mantissa of the add operand as the exponent and mantissa of the second operand, and the exponent and mantissa of the multiplicand operand as the exponent and mantissa of the third operand, respectively. 4 is assumed to be an arithmetic operation unit for a floating point number to which the exponent and the mantissa of the multiplier operand and the exponent and the mantissa of the divisor operand are given as the exponent and the mantissa, respectively.

A first arithmetic operation device according to the present invention employs a configuration in which mantissa digit aligning means and mantissa multiplication / division means are arranged in parallel. Specifically, a digit alignment means for performing digit alignment between the mantissa of the first operand and the mantissa of the second operand, and two intermediate values from the mantissa of the third operand and the mantissa of the fourth operand. Form multiplying and dividing means for calculating an intermediate product or an intermediate quotient, one of the two mantissas aligned in the case of addition and subtraction, and one of the two intermediate values in the case of multiplication and division. First selecting means for selecting one as the first data, the other of the two mantissas aligned in the case of addition and subtraction, and the other of the two intermediate values in the case of multiplication and division. The second selection means for selecting the other of them as the second data, and the addition / subtraction means for performing the addition / subtraction of the first and second data are adopted.

A second arithmetic operation unit according to the present invention is (n
Paying attention to the fact that the processing for obtaining a result rounded to n bits from the product or quotient of + m) bits can be realized by the hardware used for addition and subtraction, as a configuration for dividing and inputting the product of (n + m) bits to the addition and subtraction means. It was obtained. Specifically, the multiplication / division means for calculating the product or quotient of (n + m) bits from the mantissa of the third operand and the mantissa of the fourth operand, and the mantissa of the first operand in the case of addition / subtraction, In the case of multiplication / division, first selection means for selecting the upper n bits of the product or quotient of the (n + m) bits as the first data, and in the case of addition / subtraction, the mantissa of the second operand. In the case of multiplication and division, (n +
m) the lower m bits of the product or quotient of
In the case of multiplication and division, the second selection means for selecting the first rounding bit and the second data in the case of addition and subtraction are aligned with each other. To the digitizing means for outputting the first data and generating the second rounding bit from the second data, and in the case of addition and subtraction, the digitized first digit.
And addition / subtraction of second data, rounding using the first rounding bit, and in the case of multiplication / division, addition / subtraction means for rounding the first data using the second rounding bit It adopts a configuration with and.

The exponential arithmetic unit according to the present invention is obtained by adding some circuits to the subtractor, paying attention to the fact that exponential arithmetic in addition and subtraction and multiplication and division can be realized by subtraction. Specifically, the exponent of the augend operand or the exponent of the augend operand is used as the exponent of the first operand, the exponent of the addend operand or the exponent of the subtractive operand is used as the exponent of the second operand, and the exponent of the third operand. Is an exponent arithmetic unit for a floating-point number in which the exponent of the multiplicand operand or the exponent of the dividend operand is the exponent of the multiplier operand or the exponent of the divisor operand, respectively, as the exponent of the fourth operand. The exponent or the exponent of the third operand is the n-bit first exponent X, the exponent of the second operand or the fourth operand is the n-bit second exponent Y, and the exponent bias is B = 2 ^(n-1) -1, n 1-bit inverters each having the following functions, a logic gate, a subtractor, and (n + 1) ) A configuration including a bit inverter and an output selector is adopted.

That is, the n 1-bit inverters use n bits of intermediate data composed of the second exponent Y itself in the case of addition and subtraction and the most significant bit of the second exponent Y in the case of multiplication. And the inversion of each of the lower (n-1) bits of the second exponent Y, in the case of division, the inversion of the most significant bit of the second exponent Y It obtains n-bit intermediate data composed of the lower (n-1) bits of the exponent Y, respectively. The logic gate is
In order to obtain the (n + 1) -bit subtraction data IB, 0 is added and subtracted, and in the case of multiplication and division, the value of the most significant bit of the n-bit intermediate data obtained by the n 1-bit inverters. Are added to the upper digits of the n-bit intermediate data. The subtractor calculates the first subtraction result P = IA-IB and the second subtraction result Q = IA- (IB + 1) using the first exponent X as the minuend data IA. The (n + 1) -bit inverter obtains the inversion of each of the (n + 1) -bits forming the second subtraction result Q. The output selector outputs a signal indicating that the exponent of the first operand is not smaller than the exponent of the second operand when X ≧ Y and addition / subtraction, and the exponent of the first operand and the exponent of the second operand. The first subtraction result P is selected so as to output the absolute value X−Y of the difference, and X <
In the case of Y and addition / subtraction, the exponent of the first operand is the second
A signal that is less than the exponent of the operand of
The result of the (n + 1) bit inverter is selected to output the absolute value Y−X of the difference between the exponent of the operand and the exponent of the second operand, and in the case of multiplication, the product exponent X + Y−
The first subtraction result P is selected so as to output B, and the second subtraction result Q is selected so as to output the quotient index XY + B in the case of division.

[0016]

According to the first arithmetic operation unit of the present invention, in the case of single addition and single subtraction, the digit aligning means, the first
In the case of the single multiplication and the single division, the multiplication and division means, the first and second selection means, and the addition and subtraction means are used for mantissa processing, respectively.
In other words, the processing of the two mantissas aligned in the case of addition and subtraction and the processing of the intermediate product or the intermediate quotient in the case of multiplication and division are performed by the same addition and subtraction means.

According to the second arithmetic operation device of the present invention, in the case of single addition and single subtraction, the first and second selecting means, the digit aligning means, and the adding / subtracting means perform the single multiplication and In the case of single division, the multiplication / division means, the first and second selection means, the digit alignment means, and the addition / subtraction means are used for mantissa processing, respectively. In other words, the digit alignment addition / subtraction processing involving rounding of two mantissas in the case of addition / subtraction and the rounding addition processing to the required number of bits of the product or quotient in the case of multiplication / division are performed by the same digit alignment means and addition / subtraction means. Be seen.

According to the exponential calculation device of the present invention,
In the case of addition and subtraction, the absolute value of the exponent difference is calculated, and in the case of multiplication, I
A product index conforming to the IEEE754 standard and a quotient exponent conforming to the IEEE754 standard are obtained in the case of division, respectively.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a floating point arithmetic operation unit according to a first embodiment of the present invention. FIG.
In FIG. 11, 11 is a first exponential arithmetic unit, which is a swap that determines the absolute value of the exponential difference between two exponent inputs Ex and Ey in addition and subtraction, and determines whether to replace the mantissa from the arithmetic result. The signal SW is generated, the absolute value of the exponential difference is output as the right shift amount RSA, and Ex and Ey are used for multiplication.
And the quotient index Ez of Ex and Ey are obtained by division. 12 is the first exponential arithmetic unit 1
It is an exponent selector that selects one of the three operation results Ez and the exponent inputs Ex and Ey in 1. Reference numeral 13 is a second exponent arithmetic unit for adding and subtracting the output of the exponent selector 12 and a constant.

Reference numeral 15 denotes two inputs of X and Y in accordance with the swap signal SW generated by the first exponential arithmetic unit 11, where A =
A swapper that outputs as X, B = Y or A = Y, B = X. Reference numeral 16 is a right shifter that shifts the output on the B side of the swapper 15 to the right based on the right shift amount RSA output from the first exponent arithmetic unit 11 and generates a rounding bit. Reference numeral 24 is a multiplier that performs multiplication on two mantissa inputs Mx and My and outputs an intermediate sum S and a carry C. 17 is an output on the A side of the swapper 15 and a multiplier 24
It is a first mantissa selector which selects one of the output S and the output S. A second mantissa selector 18 selects either the output of the right shifter 16 or the output C of the multiplier 24. Reference numeral 19 is a 1-bit right shifter that outputs the result of right-shifting the output of the first mantissa selector 17 or outputs the output of the first mantissa selector 17 as it is according to the type of operation. Similarly, 20 is a 1-bit right shifter that outputs the result of right shifting the output of the second mantissa selector 18 or outputs the output of the second mantissa selector 18 as it is. 21 is a 1-bit right shifter 19, 20
Is an adder / subtractor that performs addition / subtraction and rounding on the output of.
Reference numeral 22 is a priority encoder that detects the number of leading "0" s by detecting the position of the first "1" in the output of the adder / subtractor 21 and outputs this as the left shift amount LSA. Reference numeral 23 is a left shifter that shifts the output of the adder / subtractor 21 to the left based on the left shift amount LSA. 14 is the second
It is a third exponential arithmetic unit for subtracting the left shift amount LSA obtained by the priority encoder 22 from the output of the exponential arithmetic unit 13.

The operation of the floating point arithmetic unit having the above structure will be described. When performing floating-point addition / subtraction, it is necessary to first find the exponent difference and right-shift the mantissa having the smaller exponent by this exponent difference to perform digit alignment.

For this purpose, the first exponent arithmetic unit 11 calculates the exponent difference (Ex-Ey), and the absolute value thereof is obtained as the right shift amount RSA. On the other hand, the two indices Ex,
The magnitude of Ey can be determined by whether or not there is a borrow generated from the most significant bit in the operation of Ex-Ey. If there is a borrow, Ex-Ey <0, that is, Ex <Ey, so this borrow is output as a swap signal SW. To do. Further, the exponent selector 12 outputs the larger one of the indices of Ex and Ey to the second exponent arithmetic unit 13 according to the borrow value.

Further, the two mantissas Mx and My are the swapper 1
5, the swap signal SW is SW = 1, that is, E
If x <Ey, A = My and B = Mx, and if the swap signal SW is SW = 0, that is, Ex ≧ Ey, A = My.
Output as Mx and B = My respectively. As a result, the mantissa of the operand having the smaller exponent is always input to the right shifter 16. In the right shifter 16, the swapper 1
The output on the B side of 5 is right-shifted according to the right-shift amount RSA and is output to the second mantissa selector 18. This operation completes the digit alignment of the mantissa. In order to calculate the digit-matched mantissa as described above, the first mantissa selector 17 selects the output on the A side of the swapper 15 to select the 1-bit right shifter 1
Then, the second mantissa selector 18 selects the output of the right shifter 16 and outputs it to the 1-bit right shifter 20.

Next, addition and subtraction and rounding are performed on the mantissa obtained by aligning the digits. To realize rounding defined by the IEEE754 standard, at least two rounding bits are required.
Bit needed. Of these, the lower 1 bit is called the sticky bit, and all digits below this digit are 0.
Or not.

By the way, assuming that the two bits for rounding are r and s from the upper side, there are the following three calculation results before rounding. Here, “*” indicates “1” or “0”.

(A) 1 *. *** ... * rs (b) 1. *** ... ** rs (c) 0. *** ... *** rs

Since the carry by rounding occurs from the position of r to the higher order side, it is necessary to prepare three carry positions as it is. However, in addition and subtraction, if addition is performed for floating-point numbers with the same sign or subtraction is performed for floating-point numbers with different signs (hereinafter, for the sake of simplicity, it is called the case where a mantissa is carried),
The result is only one of (a) and (b), and in the other cases, only one of (b) and (c). In this embodiment, when a carry is generated in the mantissa, the 1-bit right shifters 19 and 20 shift the input to the right by 1 bit,
Output to the adder / subtractor 21. If no carry is generated in the mantissa, the 1-bit right shifters 19 and 20 do not shift and the input is output as it is to the adder / subtractor 21. Thus, even if the mantissa has a carry by the 1-bit right shifters 19 and 20, it can be treated as (b) and (c), and the rounding carry position can be reduced in two ways. 1
When shifting is performed by the bit right shifters 19 and 20,
Since it is necessary to correct the exponent, the second exponent arithmetic unit 1
In 3, the result of adding 1 to the input is the result of the third exponentiation unit 1
4 is output. In other cases, there is no need to correct the exponent, so the second exponent arithmetic unit 13 outputs the input to the third exponent arithmetic unit 14 as it is.

The 1-bit right shifter 19 thus obtained,
The output of 20 is input to the adder / subtractor 21, which performs addition / subtraction and rounding, and outputs the addition / subtraction result to the priority encoder 22 and the left shifter 23.

In this embodiment, the sticky bit s for rounding is generated when the right shifter 16 shifts. At this time, the position of s in (b) is shifted to the lower one bit, The position of s is the same as that of (c), and the right shifter 1
We are reducing the amount of hardware in 6. If the rounding bit that increases by shifting the position of s is g, the combinations of mantissas when the operation results before rounding are (b) and (c) are as shown in FIGS. 2 (a) and 2 (b), respectively. It is as follows. Here, x and y indicate "1" or "0".

In the adder / subtractor 21, addition and subtraction and rounding are realized as follows. Figure 2 for two inputs
Addition / subtraction is performed for digits higher than g in (a), and both the operation result Z1 when there is a carry from the lowest digit and the operation result Z0 when there is no carry are prepared. On the other hand, for digits less than or equal to g, carry Cgb, Cgc from the digit of g in each case of FIGS. 2A and 2B is calculated. In the case of FIG. 2A, the rounding carry by grs is Cgb, but in the case of FIG. 2B, Cgc is determined by the rounding carry by rs and the value of g.
The output of the adder / subtractor 21 is for digits higher than g depending on the value of the most significant digit of the operation results Z1, Z0, carry Cgb, Cgc, and whether addition or subtraction is performed on the mantissa. Is either Z1 or Z0, and the digit of g is either the operation result or 0. As described above, addition and subtraction and rounding are realized by one adder / subtractor 21.

The priority encoder 22 detects the position of the first "1" in the input, that is, to find the number of leading "0" s, and thereby the addition / subtraction result of the adder / subtractor 21 is normalized. To obtain the left shift amount LSA. The left shifter 23 shifts the output of the adder / subtractor 21 to the left according to the left shift amount LSA output from the priority encoder 22, and outputs a normalized mantissa. The third exponent arithmetic unit 14 corrects the exponent by subtracting the left shift amount LSA, which is the output of the priority encoder 22, from the output of the second exponent arithmetic unit 13, and outputs the corrected exponent. Floating point addition / subtraction can be executed by the above operation.

Next, the operation when performing floating point multiplication will be described. When performing floating-point multiplication, first, the first exponent arithmetic unit 11 obtains the product exponent Ez of Ex and Ey. The product index Ez thus obtained is selected by the index selector 12 and input to the second index calculator 13. Mantissa M
x and My are multiplied by the multiplier 24, and the multiplication result is the intermediate sum S.
And carry C are output. First mantissa selector 17
Selects the intermediate sum S and outputs it to the 1-bit right shifter 19,
The second mantissa selector 18 selects the carry C and outputs it to the 1-bit right shifter 20.

In the floating-point multiplication, the addition result before rounding is always either (a) or (b), so the 1-bit right shifters 19 and 20 shift the input to the right by 1 bit. The outputs of the 1-bit right shifters 19 and 20 are adder / subtractor 21.
Are added and rounded to obtain the mantissa multiplication result. After that, the operations of the priority encoder 22, the left shifter 23, and the third exponent arithmetic unit 14 are the same as the above-mentioned floating point addition / subtraction.

On the other hand, the first exponent arithmetic unit 11 obtains the product exponent Ez = Ex + Ey-B with the exponent bias being B, and outputs it to the exponent selector 12. The exponent selector 12 selects the output of the first exponent arithmetic unit 11 and inputs it to the second exponent arithmetic unit 13. Since the shift has been performed in the 1-bit right shifters 19 and 20, the second exponent arithmetic unit 13
Then, the result obtained by adding 1 to the input is the third exponential arithmetic unit 14
Output to. The operation of the third exponent arithmetic unit 14 is the same as the above-mentioned floating point addition / subtraction. Floating point multiplication can be executed as described above.

Next, the operation when performing floating point division will be described. ROM (Read Onl) that stores the reciprocal of the mantissa of Y
y Memory) is used to perform X / Y division. Now, let the exponent and mantissa of X be Xe and Xf, and the exponent and mantissa of Y be Ye and Yf, respectively. First, the reciprocal of the mantissa Yf is read from the ROM (not shown) and input to the multiplier 24 as My in FIG. On the other hand, the mantissa Xf is input to the multiplier 24 as Mx in FIG. 1, and the multiplication result Mx · My = Xf / Yf is obtained as the intermediate sum S and the carry C. The first mantissa selector 17 selects the intermediate sum S and outputs it to the 1-bit right shifter 19, and the second mantissa selector 18 selects the carry C and outputs it to the 1-bit right shifter 20.

In floating-point division, the addition result before rounding is always either (b) or (c), so the 1-bit right shifters 19 and 20 output their inputs to the adder / subtractor 21 as they are. The outputs of the 1-bit right shifters 19 and 20 are added by an adder / subtractor 21 and rounded to obtain a mantissa division result. After that, the operations of the priority encoder 22 and the left shifter 23 are the same as those in the case of performing the floating point addition / subtraction described above.

On the other hand, the indices Xe and Ye are respectively represented by E in FIG.
It is input to the first exponent arithmetic unit 11 as x and Ey. In the first exponent arithmetic unit 11, the exponent bias is set to B, the quotient exponent Ez = Ex−Ey + B is obtained, and the exponent selector 12
Output to. The exponent selector 12 is the first exponent arithmetic unit 1
The output of 1 is selected and input to the second exponent arithmetic unit 13. Since no shift is performed in the 1-bit right shifters 19 and 20, the second exponent arithmetic unit 13 outputs the input to the third exponent arithmetic unit 14 as it is. The operation of the third exponent arithmetic unit 14 is the same as the above-mentioned floating point addition / subtraction. As described above, the floating point division can be executed.

As described above, according to the present embodiment, the output of the digit matching means constituted by the swapper 15 and the right shifter 16 and the output of the multiplier 24 are set to the first and second mantissa selectors 1.
It is possible to share the adder / subtractor 21 for addition / subtraction and multiplication / division by selecting 7 or 18 according to the type of operation. Further, by providing the 1-bit right shifters 19 and 20, the exponent correction for the carry of the mantissa can be performed in parallel with the addition and subtraction of the mantissa, and the processing can be performed at high speed.

In this embodiment, the output of the multiplier 24 is used as an intermediate value in the form of the intermediate sum S and the carry C, and the adder / subtractor 21
However, the multiplication result may be an intermediate value between the positive number and the negative number so that the multiplier using the redundant binary number outputs, and the adder / subtractor 21 may perform the operation of subtracting the negative number from the positive number.

An exponent register is inserted between the exponent selector 12 and the second exponent arithmetic unit 13, and between the second exponent arithmetic unit 13 and the third exponent arithmetic unit 14, respectively. Mantissa selector 17 and 1-bit right shifter 1
9 and between the second mantissa selector 18 and the 1-bit right shifter 20, and between the adder / subtractor 21 and the priority encoder 22, respectively, pipeline floating-point arithmetic An arithmetic unit can be realized. According to this, since the circuit block assigned to each pipeline stage is used only once during the execution of one arithmetic instruction, it is possible to perform high-speed processing that brings out the full advantage of the pipeline control method.

(Embodiment 2) FIG. 3 is a block diagram of a floating point arithmetic operation unit according to a second embodiment of the present invention. FIG.
1 having the same functions as those in FIG. 1 are denoted by the same reference numerals and detailed description thereof will be omitted, and only those having functions different from those in FIG. 1 will be described.

Reference numeral 25 is a multiplier for multiplying the mantissas Mx and My and outputting the result in (n + m) bits. Reference numeral 26 is a first mantissa selector that selects either the mantissa Mx or the upper n bits of the output of the multiplier 25. 27
Is a second mantissa selector that selects either the mantissa My or the lower m bits of the output of the multiplier 25.
Reference numeral 28 denotes a logic gate, which sets the swap signal SW output from the first exponent arithmetic unit 11 to 0 according to the control signal SWE.
And the swap signal SW is output as it is. Reference numeral 29 is a shift amount selector that selects either the right shift amount ERSA output from the first exponential arithmetic unit 11 or the right shift amount CRSA determined by a control unit (not shown) as the right shift amount RSA. Is.

The operation of the floating-point arithmetic operation unit having the above-mentioned configuration will be described. Since the basic operation is almost the same as that of the first embodiment, the operation is different from that of the first embodiment. Will be described.

When performing floating point addition / subtraction, the mantissa Mx is selected by the first mantissa selector 26 and X of the swapper 15 is selected.
The second mantissa selector 27 outputs the mantissa My.
Is output to the input on the Y side of the swapper 15. The swap signal SW output from the first exponential arithmetic unit 11 is output to the logic gate 28 as it is. Swapper 15
Uses the output of the logic gate 28 as a new swap signal to perform the operation described in the first embodiment. Shift amount selector 2
Reference numeral 9 designates the right shift amount ERSA output from the first exponent arithmetic unit 11 to be the right shift amount RSA, and the right shifter 1
6 is output. The right shifter 16 performs the operation described in the first embodiment. The output on the A side of the swapper 15 is input to the 1-bit right shifter 19, and the output of the right shifter 16 is input to the 1-bit right shifter 20. The components other than those described above perform the operations described in the first embodiment and execute floating point addition / subtraction.

On the other hand, when performing floating point multiplication, the multiplier 25 multiplies the mantissas Mx and My and outputs the result in (n + m) bits. In the floating-point multiplication in this case, only the upper n bits of the operation result of the multiplier 25 are valid numbers, and the lower m bits are used to generate the rounding bit. Therefore, the first mantissa selector In 26, the upper n bits of the multiplication result of the multiplier 25 are selected and output to the X side of the swapper 15, and in the second mantissa selector 27, the lower m bits of the multiplication result of the multiplier 25 are selected and Y of the swapper 15 is selected. Output to the side. The logic gate 28 outputs the swap signal SW as 0. The swapper 15 newly uses the output of the logic gate 28 as a swap signal,
The operation described in the embodiment is performed. Shift amount selector 29
Selects a right shift amount CRSA determined by a control unit (not shown) as a right shift amount RSA and outputs the right shift amount RSA to the right shifter 16.
The right shifter 16 moves the swapper 15 according to the right shift amount RSA.
The output on the B side of is right-shifted. At this time, the right shift amount C
RSA is m, and the lower m bits of the multiplication result are right-shifted by m bits to generate a rounding bit.
The adder / subtractor 21 adds the outputs of the 1-bit right shifters 19 and 20 to add the rounding bits generated by the right shifter 16 to the upper n bits of the output of the multiplier 25, and rounds the n-bit rounded bits. Get the multiplication result. The components other than those described above perform the operation described in the first embodiment and execute the floating point multiplication. The description of the operation during floating point division is omitted.

FIG. 4 shows the internal structure of the first exponent arithmetic unit 11 in FIGS. 1 and 3. In FIG. 4, 53 is 2
It is a (n + 1) -bit subtracter that subtracts two inputs IA and IB, and subtraction results P = IA-IB and Q = IA- (I
B + 1) is output. 51.1 is a 1-bit inverter for inverting the input according to the control signal CS1, 52 is the control signal CS
It is a logic gate that outputs 0 by 3 or outputs the output of the 1-bit inverter 51.1 as it is. The output of the logic gate 52 becomes the most significant bit of the subtraction side IB of the subtractor 53, and the output of the 1-bit inverter 51.1 is the subtractor 5
It is the second bit from the most significant bit of the IB of 3 on the reduction side. 5
1.2-51. Each n is a (n-1) 1-bit inverter whose input is inverted according to the control signal CS2, and the lower (n-1) bit of the subtraction side IB of the subtractor 53 has 1
Bit inverters 51.2 to 51. The n outputs are connected together. Reference numeral 54 is an (n + 1) -bit inverter that inverts and outputs the Q output of the subtractor 53. 55 is a subtractor 5
1 out of 3 Q output, P output and inverter 54 output
It is an output selector that selects one.

The exponential arithmetic unit configured as described above is
The following operations are performed to calculate exponents during addition, subtraction, multiplication and division. The minuend IA of the subtractor 53 is the first exponential input X (Ex), and the n 1-bit inverters 51.
1-51. The input of n is the second exponential input Y (Ey).

First, the product index X + Y-B is the second index Y.
Using the bit inversion data y of the above, it can be expressed as X + Y−B = X− (B−Y) = X− (B + y + 1) (4), and Y = Y _n−1 2 ⁽ⁿ⁻¹⁾ + Y _n−2 2 ^(n-2) + ... + Y ₁ 2 ¹ + Y ₀ 2 ⁰ ... (5), y = y _n-1 2 ^(n-1) + y _n-2 2 ^(n-2) + ... + y ₁ 2 ¹ It can be expressed as + y ₀ 2 ⁰ (6). Therefore, from the formula (6) and B = 2 ^(n-1) -1, from B + y + 1 = 2 ^(n-1) -1 + y + 1 = 2 ^(n-1) + y = 2 ⁿ + (y _n-1 +1) 2 It can be expressed as ^(n-1) + y _n-2 2 ^(n-2) + ... + y ₀ 2 ⁰ (7).

Here, _assuming that y _n-1 = 0 (Y _n-1 = 1), from the equation (7), B + y + 1 = 2 ⁿ +2 ^(n-1) + y _n-2 2 ^(n-2) + … + Y ₀ 2 ⁰ It becomes (8). Further, _assuming that y _n-1 = 1 (Y _n-1 = 0), according to the equation (7), B + y + 1 = 2 ⁿ +2 ⁿ + y _n-2 2 ^(n-2) + ... + y ₀ 2 ⁰ (9 ). Since y ₋ 0> 0 when y _n−1 = 1, the first and second terms on the right side of the equation (9) can be ignored. Therefore, from equations (8) and (9), B + y + 1 = Y _n-1 2 ⁿ + Y _n-1 2 ^(n-1) + y _n-2 2 ^(n-2) + ... + y ₀ 2 ⁰ (10) It can be expressed as.

On the other hand, the quotient exponent XY + B can be expressed as XY + B = X- (Y-B) = X- (Y + b + 1) (11) using the bit inversion data b of the bias B. Since b + 1 corresponds to the two's complement of B, b + 1 = 2 ⁿ +2 ^(n-1) +1 (12). Equation (5), from (12), Y + b + 1 = Y n-1 2 (n-1) + Y n-2 2 (n-2) + ... + Y 0 2 0 +2 n +2 (n-1) +1 = 2 n It can be expressed as + (Y _n-1 +1) 2 ^(n-1) + Y _n-2 2 ^(n-2) + ... + Y ₀ 2 ⁰ +1 (13).

Assuming that Y _n-1 = 0 (y _n-1 = 1), from the equation (13), Y + b + 1 = 2 ⁿ +2 ^(n-1) + Y _n-2 2 ^(n-2) + ... + Y ^₀ 2 ₀ +1 ... (14). Further, _assuming that Y _n-1 = 1 (y _n-1 = 0), from the equation (13), Y + b + 1 = 2 ⁿ +2 ⁿ + Y _n-2 2 ^(n-2) + ... + Y ₀ 2 ⁰ +1 (( 15) When Y _n-1 = 1 then Y−B> 0, so the first and second terms on the right side of equation (15) can be ignored. Therefore, from equations (14) and (15), Y + b + 1 = y _n-1 2 ⁿ + y _n-1 2 ^(n-1) + Y _n-2 2 ^(n-2) + ... + Y ₀ 2 ⁰ +1 (16) ) Can be expressed as

According to equation (10), the subtraction B in equation (4)
+ Y + 1 has the same value as the most significant bit of the second exponent Y as the upper 2 bits, and the lower (n−) of the second exponent Y.
1) It is understood that the data is (n + 1) -bit data having the inversion of bits as the lower (n-1) bits. If this subtraction B + y + 1 is subtracted from the first index X, the product index X + Y
-B can be obtained.

According to the equation (16), the subtraction Y + b + 1 in the equation (11) has the inversion of the most significant bit of the second exponent Y as the upper 2 bits, and the lower ( It can be seen that the data is obtained by adding 1 to the (n + 1) -bit data having the same value as the (n-1) -bit as the lower (n-1) bits. Subtracting this subtraction Y + b + 1 from the first index X gives the quotient index XY + B.

At the time of multiplication, the 1-bit inverter 51.1 does not perform the inversion operation, and the (n-1) 1-bit inverters 51.
2 to 51. Control signals CS1, CS2 and CS3 are supplied so that n performs an inverting operation and the logic gate 52 outputs the output of the 1-bit inverter 51.1 as it is. Therefore, in the subtractor 53, IA = X, IB = B + y
It becomes +1. The subtraction result P in this case is P = IA-IB = X- (B + y + 1) (17), and it is understood from the equation (4) that the subtraction result P is equal to X + Y-B. The output selector 55 selects the subtraction result P as the product index Ez and outputs it.

At the time of division, the 1-bit inverter 51.1 performs the inverting operation, and (n-1) 1-bit inverters 51.2
~ 51. Control signals CS1, CS2 and CS3 are supplied so that n does not perform the inverting operation and the logic gate 52 outputs the output of the 1-bit inverter 51.1 as it is. Therefore, in the subtractor 53, IA = X, IB = Y + b
Becomes The subtraction result Q in this case is Q = IA- (IB + 1) = X- (Y + b + 1) (18), and it can be seen from the equation (11) that the subtraction result Q is equal to XY + B. The output selector 55 selects and outputs the subtraction result Q as the quotient index Ez.

At the time of addition and subtraction, n 1-bit inverters 5
1.1-51. The control signals CS1 and CS1 are controlled so that n does not perform the inverting operation and the logic gate 52 outputs 0.
CS2 and CS3 are supplied. Therefore, the subtractor 53
In IA = X, IB = Y. Two subtraction results P and Q in this case are P = IA-IB = XY ... (19) Q = IA- (IB + 1) = X- (Y + 1) ... (20).

As described above, the exponential difference (X-
It is necessary to find the absolute value of Y). When X−Y ≧ 0, the subtraction result P of the subtractor 53 is the absolute value to be obtained, but when XY <0, Y−X needs to be obtained.
Here, whether or not XY <0 can be determined by whether or not there is a borrow generated from the most significant bit in the operation of XY.
With borrow, XY <0. On the other hand, Y-X is obtained by inverting all the bits of the subtraction result Q. The reason is as follows: X−Y = − (Y−X) = INV (Y−X) +1 (21). Here, INV (W) means an inversion operation of all bits of W. From the formula (21), INV (Y−X) = X−Y−1 = X− (Y + 1) (22). Therefore, Y−X = INV (X− (Y + 1)) (23). That is, Y-X is obtained by inverting all the bits of the subtraction result Q of the equation (20) by the (n + 1) -bit inverter 54.

At the time of addition / subtraction, the output selector 55 selects the output of the (n + 1) -bit inverter 54 if there is a borrow generated from the most significant bit in the operation of the subtractor 53, and the subtraction result P of the subtractor 53 if there is no borrow. Select. The most significant bit of the (n + 1) -bit output of the output selector 55 is supplied to the swapper 15 as the swap signal SW, and the remaining n bits are supplied to the right shifter 16 as the right shift amount RSA.

The first exponential arithmetic unit 1 in FIGS. 1 and 3
If the internal configuration of FIG. 4 is adopted in FIG. 1, the hardware of the first to third exponent arithmetic units 11, 13, and 14 has a very similar configuration with the adder / subtractor as the main configuration. Therefore, the floating-point arithmetic operation units of FIGS. 1 and 3 can have a well-balanced pipeline configuration. The multiplier 24,
25 and the description of the internal configuration of the priority encoder 22 will be omitted.

[0061]

As described above, according to the first arithmetic operation unit of the present invention, since the mantissa digit aligning means and the mantissa multiplying / dividing means are arranged in parallel, the case of addition and subtraction As a result of the processing of the two mantissas aligned with each other and the processing of the intermediate product or the intermediate quotient in the case of multiplication / division being performed by the same addition / subtraction means, single addition of floating point numbers and single Subtraction, single multiplication and single division can be performed.

According to the second arithmetic operation device of the present invention, since the product of (n + m) bits is divided and input to the adder / subtractor, digit addition / subtraction accompanied by rounding of two mantissas in the case of addition / subtraction is adopted. The same processing and rounding addition of the product or quotient to the required number of bits in the case of multiplication and division result in single addition, single subtraction and single addition of floating point numbers with a small amount of hardware. Multiplication and single division can be performed.

According to the exponential arithmetic unit of the present invention, two subtraction results P = IA-IB and Q = IA- (IB + 1).
And a (n + 1) -bit inverter for obtaining the inversion of the subtraction result Q are used to calculate the absolute value of the exponent difference in the case of addition and subtraction, the product exponent in the case of multiplication, and the In this case, since the quotient index and the quotient index are calculated, the index calculator can be used for addition, subtraction, multiplication and division.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a floating-point arithmetic operation device according to a first embodiment of the present invention.

2A and 2B are diagrams for explaining the operation of the adder / subtractor in FIG.

FIG. 3 is a block diagram showing a configuration of a floating point arithmetic unit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an internal configuration example of a first exponential arithmetic unit in FIGS. 1 and 3.

[Explanation of symbols]

 11 First Exponential Arithmetic Unit 12 Exponent Selector 13 Second Exponential Arithmetic Unit 14 Third Exponential Arithmetic Unit 15 Swapper 16 Right Shifter 17 First Mantissa Selector 18 Second Mantissa Selector 19, 20 1-bit Right Shifter 21 Addition / Subtraction Device 22 priority encoder 23 left shifter 24, 25 multiplier 26 first mantissa selector 27 second mantissa selector 28 logic gate 29 shift amount selector 51.1 to 51. n 1-bit inverter 52 Logic gate 53 Subtractor 54 (n + 1) bit inverter 55 Output selector

Claims (14)

[Claims] 1. An exponent and a mantissa of an augend operand as an exponent and a mantissa of a first operand, and an exponent and a mantissa of an addend of a operand are used as an exponent and a mantissa of a second operand. Is the exponent and mantissa of the third operand as the exponent and mantissa of the third operand, and the exponent and mantissa of the mantissa or the dividend operand are the exponent and mantissa of the fourth operand as the exponent and mantissa of the fourth operand, respectively. And a mantissa, which are arithmetic units for floating-point numbers, and digit aligning means for performing digit alignment between the mantissa of the first operand and the mantissa of the second operand. From the mantissa of the operand and the mantissa of the fourth operand, the intermediate product or the intermediate quotient in the form of two intermediate values. Multiply / divide means for calculating, and one of the two mantissas aligned in the case of addition / subtraction, and one of the two intermediate values in the case of multiplication / division as first data. A first selecting means for selecting the second mantissa of the two digit-matched mantissas in the case of addition and subtraction, and a second of the two intermediate values in the case of multiplication and division. An arithmetic operation device comprising: a second selecting means for selecting as data and an adding / subtracting means for performing addition / subtraction of the first and second data. 2. The arithmetic operation device according to claim 1, wherein the multiplication / division means calculates an intermediate product in the form of an intermediate sum and a carry from the mantissa of the third operand and the mantissa of the fourth operand. An arithmetic operation device comprising a multiplier for generating. 3. The arithmetic operation unit according to claim 1, wherein the digit aligning means sets a mantissa of an operand having a larger exponent of the first and second operands as a first numerical value, and An arithmetic operation device comprising a swapper for outputting a mantissa of an operand as a second numerical value, and a right shifter for performing a right shift process on the second numerical value. 4. The arithmetic operation unit according to claim 3, wherein in the case of addition and subtraction, a signal indicating a magnitude relationship between the exponent of the first operand and the exponent of the second operand is supplied to the swapper, and The absolute value of the difference between the exponent of the first operand and the exponent of the second operand is supplied to the right shifter as a shift amount, and in the case of multiplication / division, the third value is supplied.
A first exponent arithmetic unit for calculating a product exponent or a quotient exponent from the exponent of the operand and the exponent of the fourth operand; and, in the case of addition and subtraction, the exponent of the first operand and the exponent of the second operand. An arithmetic operation device further comprising: an exponent selector for selecting a larger exponent of the exponents and selecting the calculated product exponent or quotient exponent in the case of multiplication and division. 5. The arithmetic operation device according to claim 4, wherein the first exponent operation device sets the exponent of the first operand or the exponent of the third operand to an n-bit first exponent X, The exponent of the second operand or the exponent of the fourth operand is the n-bit second exponent Y, and the exponent bias is B = 2.
⁽ⁿ⁻¹⁾ −1, in the case of addition and subtraction, the n-bit intermediate data composed of the second exponent Y itself is used as the most significant bit of the second exponent Y in the case of multiplication. Lower part (n−) of the second index Y
1) Inversion of the n-bit intermediate data consisting of the inversion of each bit and the inversion of the most significant bit of the second exponent Y and the lower order (n-1) of the second exponent Y in the case of division. And n-bit 1-bit inverters for obtaining n-bit intermediate data respectively, and (n + 1) -bit subtraction data IB, in the case of addition and subtraction, in the case of multiplication and division A logic gate for adding the value of the most significant bit of the n-bit intermediate data obtained by the n 1-bit inverters to the upper digit of the n-bit intermediate data, and the first exponent. The first subtraction result P = IA-IB and the second subtraction result Q = IA- (I
B + 1), a (n + 1) -bit inverter for obtaining the inversion of each of the (n + 1) bits forming the second subtraction result Q, and X ≧ Y and addition and subtraction Is a signal indicating that the exponent of the first operand is not less than the exponent of the second operand, and the absolute value XY of the difference between the exponent of the first operand and the exponent of the second operand. Selecting the first subtraction result P so as to output, and a signal indicating that the exponent of the first operand is smaller than the exponent of the second operand when X <Y and addition / subtraction, 1
The result of the (n + 1) -bit inverter is output so as to output the absolute value Y−X of the difference between the exponent of the operand and the exponent of the second operand, and in the case of multiplication, the product exponent X +
And an output selector for selecting the first subtraction result P so as to output Y−B, and for selecting the second subtraction result Q so as to output the quotient index X−Y + B in the case of division. An arithmetic operation device characterized by being provided. 6. The arithmetic operation device according to claim 4, wherein the right shifter further has a function of generating a rounding bit, and the adder / subtractor performs rounding using the rounding bit together with addition and subtraction. The arithmetic operation device includes an adder / subtractor, and the arithmetic operation device is interposed between the first and second selection means and the addition / subtraction means, and selectively operates the first arithmetic operation unit according to a type of arithmetic operation.
And two 1-bit right shifters for performing 1-bit right shift processing on the second data, and a second exponent operation for correcting the exponent selected by the exponent selector according to the 1-bit right shift processing. An arithmetic operation device further comprising a device. 7. An arithmetic operation unit according to claim 6, further comprising: a priority encoder for determining the number of leading zero-value bits by detecting the position of the first non-zero-value bit of the result of said addition / subtraction means. A left shifter for performing a left shift process with the obtained number of zero-valued bits as a shift amount on the result of the adding / subtracting means, and an exponent corrected by the second exponent arithmetic unit to the left shift process. An arithmetic operation device further comprising a third exponential operation device for performing correction in accordance therewith. 8. The exponent and mantissa of the augend operand as the exponent and mantissa of the first operand, and the exponent and the mantissa of the operand of the operand are the exponent and mantissa of the addend operand as the exponent and the mantissa of the second operand, respectively. Is the exponent and mantissa of the third operand as the exponent and mantissa of the third operand, and the exponent and mantissa of the mantissa or the dividend operand are the exponent and mantissa of the fourth operand as the exponent and mantissa of the fourth operand, respectively. And a mantissa, which are arithmetic units for floating-point numbers, and multiply and divide to calculate a product or quotient of (n + m) bits from the mantissa of the third operand and the mantissa of the fourth operand. Arithmetic means, the mantissa of the first operand in the case of addition and subtraction, and the ( + M) first selection means for selecting the upper n bits of the product or quotient of the bits as the first data, and the mantissa of the second operand in the case of addition and subtraction, and the multiplication and division in the case of multiplication and division. Is a second selecting means for selecting the lower m bits of the product or quotient of the (n + m) bits as the second data; and, in the case of addition and subtraction, the first data and the second data. And a digit for generating a first rounding bit, and in the case of multiplication / division, outputting the first data and generating a second rounding bit from the second data. Aligning means, in the case of addition and subtraction, rounding using the first rounding bit together with addition and subtraction of the digitized first and second data, and in the case of multiplication and division for the second rounding Circle of the first data using bits Arithmetic apparatus characterized by comprising a subtraction means for performing. 9. The arithmetic operation device according to claim 8, wherein said digit aligning means is a larger one of said first and second operands relating to said first and second data in the case of addition and subtraction. The mantissa of the operand having the exponent is output as the first numerical value and the mantissa of the other operand is output as the second numerical value, and in the case of multiplication / division, the first data is the first numerical value and the second data is A swapper for outputting as a second numerical value, and in the case of addition and subtraction, digit matching of the first and second numerical values and generation of the first rounding bit,
An arithmetic operation device comprising a right shifter for performing a right shift process on each of the second numerical values so as to generate the second rounding bit in the case of multiplication and division. 10. The arithmetic operation device according to claim 9, wherein in the case of addition and subtraction, a signal indicating a magnitude relationship between the exponent of the first operand and the exponent of the second operand is supplied to the swapper, and The absolute value of the difference between the exponent of the first operand and the exponent of the second operand is supplied to the right shifter as a shift amount, and in the case of multiplication / division, the third value is supplied.
A first exponent arithmetic unit for calculating a product exponent or a quotient exponent from the exponent of the operand and the exponent of the fourth operand; and, in the case of addition and subtraction, the exponent of the first operand and the exponent of the second operand. An arithmetic operation device further comprising: an exponent selector for selecting a larger exponent of the exponents and selecting the calculated product exponent or quotient exponent in the case of multiplication and division. 11. The arithmetic operation device according to claim 10, wherein the first exponent operation device sets an exponent of the first operand or an exponent of the third operand to an n-bit first exponent X, The exponent of the second operand or the exponent of the fourth operand is the n-bit second exponent Y, and the exponent bias is B = 2.
⁽ⁿ⁻¹⁾ −1, in the case of addition and subtraction, the n-bit intermediate data composed of the second exponent Y itself is used as the most significant bit of the second exponent Y in the case of multiplication. Lower part (n−) of the second index Y
1) Inversion of the n-bit intermediate data consisting of the inversion of each bit and the inversion of the most significant bit of the second exponent Y and the lower order (n-1) of the second exponent Y in the case of division. And n-bit 1-bit inverters for obtaining n-bit intermediate data respectively, and (n + 1) -bit subtraction data IB, in the case of addition and subtraction, in the case of multiplication and division A logic gate for adding the value of the most significant bit of the n-bit intermediate data obtained by the n 1-bit inverters to the upper digit of the n-bit intermediate data, and the first exponent. The first subtraction result P = IA-IB and the second subtraction result Q = IA- (I
B + 1), a (n + 1) -bit inverter for obtaining the inversion of each of the (n + 1) bits forming the second subtraction result Q, and X ≧ Y and addition and subtraction Is a signal indicating that the exponent of the first operand is not less than the exponent of the second operand, and the absolute value XY of the difference between the exponent of the first operand and the exponent of the second operand. Selecting the first subtraction result P so as to output, and a signal indicating that the exponent of the first operand is smaller than the exponent of the second operand when X <Y and addition / subtraction, 1
The result of the (n + 1) -bit inverter is output so as to output the absolute value Y−X of the difference between the exponent of the operand and the exponent of the second operand, and in the case of multiplication, the product exponent X +
And an output selector for selecting the first subtraction result P so as to output Y−B, and for selecting the second subtraction result Q so as to output the quotient index X−Y + B in the case of division. An arithmetic operation device characterized by being provided. 12. The arithmetic operation device according to claim 10, wherein the arithmetic unit is interposed between the digit aligning unit and the adding / subtracting unit, respectively.
Two 1-bit right shifters for selectively performing 1-bit right shift processing on the two outputs of the digit aligning means in accordance with the type of arithmetic operation, and the 1-bit right shift processing for the exponent selected by the exponent selector. An arithmetic operation device further comprising: a second exponential operation device for making correction according to the above. 13. The arithmetic unit according to claim 12, further comprising: a priority encoder for determining the number of leading zero-value bits by detecting the position of the first non-zero-value bit in the result of the adding / subtracting means. A left shifter for performing a left shift process with the obtained number of zero-valued bits as a shift amount on the result of the adding / subtracting means, and an exponent corrected by the second exponent arithmetic unit to the left shift process. An arithmetic operation device further comprising a third exponential operation device for performing correction in accordance therewith. 14. The exponent of the augend operand or the exponent of the minuend operand is the second exponent as the exponent of the first operand.
The exponent of the add operand or the exponent of the subtractive operand as the exponent of the operand of, the exponent of the multiplicand operand as the exponent of the third operand, or the exponent of the dividend operand, and the exponent of the multiplier operand as the exponent of the fourth operand An exponent arithmetic unit for a floating-point number to which an exponent is given, wherein the exponent of the first operand or the exponent of the third operand is a first exponent X of n bits, and the exponent of the second operand is The exponent or the exponent of the fourth operand is the n-bit second exponent Y, and the exponent bias is B = 2.
⁽ⁿ⁻¹⁾ −1, in the case of addition and subtraction, the n-bit intermediate data composed of the second exponent Y itself is used as the most significant bit of the second exponent Y in the case of multiplication. Lower part (n−) of the second index Y
1) Inversion of the n-bit intermediate data consisting of the inversion of each bit and the inversion of the most significant bit of the second exponent Y and the lower order (n-1) of the second exponent Y in the case of division. And n-bit 1-bit inverters for obtaining n-bit intermediate data respectively, and (n + 1) -bit subtraction data IB, in the case of addition and subtraction, in the case of multiplication and division A logic gate for adding the value of the most significant bit of the n-bit intermediate data obtained by the n 1-bit inverters to the upper digit of the n-bit intermediate data, and the first exponent. The first subtraction result P = IA-IB and the second subtraction result Q = IA- (I
B + 1), a (n + 1) -bit inverter for obtaining the inversion of each of the (n + 1) bits forming the second subtraction result Q, and X ≧ Y and addition and subtraction Is a signal indicating that the exponent of the first operand is not less than the exponent of the second operand, and the absolute value XY of the difference between the exponent of the first operand and the exponent of the second operand. Selecting the first subtraction result P so as to output, and a signal indicating that the exponent of the first operand is smaller than the exponent of the second operand when X <Y and addition / subtraction, 1
The result of the (n + 1) -bit inverter is output so as to output the absolute value Y−X of the difference between the exponent of the operand and the exponent of the second operand, and in the case of multiplication, the product exponent X +
And an output selector for selecting the first subtraction result P so as to output Y−B, and for selecting the second subtraction result Q so as to output the quotient index X−Y + B in the case of division. An exponent calculation device characterized by being provided.