JPH0851639A - Video signal processor and video signal recording medium reproducing device - Google Patents

Abstract

PURPOSE:To eliminate the need of a crystal oscillator for generating clocks for control by supplying signals whose frequency is determined to a microcomputer for controlling the device main body as clock signals. CONSTITUTION:When the instruction of operation start is supplied in a standby state, the microcomputer 1 performs the control for supplying power to a chrominance signal separation circuit 2, a video mechanism part 3 and a video circuit part 4. Then, the connection of a switch 15 is switched and the output of an input circuit 14 is led to a CPU 11. Thus, the CPU 11 is shifted from a low-speed operation for which the signals of approximately 32KHz are the clock signals to a high-speed operation for which the signals of approximately 14MHz outputted from a multiplying circuit 23 are the clock signals. That is, the microcomputer 1 is shifted to the high-speed operation capable of the digital control of the capstan motor or the like of the video mechanism part 3. In the state, the microcomputer 1 performs the control of operations instructed by the operations from an outside or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device and a video signal, in which a signal having a fixed frequency generated for processing a video signal is applied as a clock signal to a microcomputer for controlling the main body of the device. The present invention relates to a recording medium reproducing device.

[0002]

2. Description of the Related Art In a video cassette recorder, a microcomputer is used to control the operation of the apparatus main body and the rotational speed of a capstan motor or the like. Further, the microcomputer is configured to perform the operation of measuring the time even during a power failure in which the supply of commercial power is stopped. FIG. 3 shows a conventional technique for performing the above-mentioned operation.
Is provided with two oscillation circuits 95 and 96. The oscillator circuit 95 includes a 32.768 KHz crystal oscillator 9
2 is connected, and a crystal oscillator 93 of 12 MHz or the like is connected to the oscillation circuit 96. In the standby state for operation, only the oscillation circuit 95 is operated and the oscillation circuit 9
The output of 5 is led to the CPU 97. Therefore, the microcomputer 91 performs the time counting operation with low power consumption. It also performs the required control operation in the standby state. On the other hand, when it is in the operating state, the output of the oscillation circuit 96 is guided to the CPU 97. Therefore, the microcomputer 91 performs a high speed operation according to a high frequency clock to control the rotation speed of the capstan motor or the like, or to control other operations.

[0003]

As described above, the microcomputer 91 has the crystal oscillator 92 for generating the clock in the standby state and the crystal oscillator 93 for generating the clock in the operating state. It is connected. That is, the microcomputer 91 requires two types of crystal oscillators 92 and 93. However, since the crystal oscillators 92 and 93 are expensive elements, using the two types of crystal oscillators 92 and 93 causes a problem that the price of the device increases.

The present invention was devised to solve the above problems, and an object of the present invention is to provide a signal of a fixed frequency generated for processing a video signal to a clock. A video signal processing device that can eliminate the need for a crystal oscillator that generates a control clock during operation of the device body by giving the signal to a microcomputer that controls the device body without increasing the number of circuits. Another object of the present invention is to provide a video signal recording medium reproducing apparatus. Further, the object of the invention described in claim 2 is to enable the microcomputer to operate at a high speed by supplying a clock signal of high frequency even when the crystal oscillator for control during the operation of the apparatus main body is not required. An object is to provide a video signal processing device. An object of the invention of claim 4 is to provide a microcomputer by supplying a clock signal to the microcomputer even when the crystal oscillator for control during the operation of the apparatus main body is unnecessary and in the standby state of the operation. An object of the present invention is to provide a video signal recording medium reproducing apparatus capable of performing a standby process.

[0005]

In order to solve the above-mentioned problems, a video signal processing apparatus according to the invention of claim 1 is a reference signal generation circuit provided with at least an oscillation circuit for generating a reference signal corresponding to a burst signal. And a YC separation circuit that separates a video signal into a luminance signal and a chrominance signal using the output of the reference signal generation circuit as a clock, and is applied to a device that controls the operation of the device body using a microcomputer, The output of the reference signal generation circuit is supplied to the microcomputer as a clock signal. In the video signal processing device according to the second aspect of the present invention, the reference signal generation circuit is provided with a multiplication circuit for multiplying the output frequency of the oscillation circuit, and the YC separation circuit uses the output of the multiplication circuit as a clock to generate the color signals. It is applied to a device that separates from a luminance signal, and the output of the multiplication circuit is given to the microcomputer as a clock signal. A video signal recording medium reproducing apparatus according to a third aspect of the present invention is applied to an apparatus that reproduces a video signal recording medium and controls the operation of the apparatus main body using a microcomputer, and reproduces from the video signal recording medium. The output of the reference signal generation circuit that sends out the reference signal corresponding to the carrier wave of the color signal is given to the microcomputer as a clock signal to the color signal restoration circuit that restores the color signal based on the received signal.
Further, the video signal recording medium reproducing apparatus according to the invention of claim 4 has a configuration including at least a power supply control section for supplying operation power supply to the microcomputer and the oscillation circuit in a standby state of the operation as the apparatus main body. There is.

[0006]

The operation of the invention according to claim 1 will be described below. A reference signal generation circuit provided with at least an oscillation circuit that generates a reference signal corresponding to a burst signal, and a YC separation circuit that separates a video signal into a luminance signal and a chrominance signal using the output of the reference signal generation circuit as a clock. Is an indispensable block in a video signal processing device that separates a video signal into a color signal and a luminance signal. Therefore, applying the output of the reference signal generation circuit to the microcomputer as a clock signal means that the clock signal is externally supplied to the microcomputer without increasing the number of clock signal generation circuits supplied to the microcomputer.

The operation of the invention according to claim 2 will be described below.
The output frequency of the oscillation circuit is a frequency determined by the target video signal, and is 3.58 MHz when the video signal is an NTSC signal, for example. Therefore, the output of the multiplication circuit has a frequency that is an integral multiple thereof, and has a high frequency. Since the high-frequency signal is supplied to the microcomputer as a clock signal, the microcomputer operates at high speed.

The operation of the invention according to claim 3 will be described below.
A reference signal generation circuit that sends a reference signal corresponding to a carrier of a color signal to a color signal restoration circuit that restores a color signal based on a signal reproduced from a video signal recording medium is indispensable in a reproduction apparatus for a video signal recording medium. Is a block. Therefore, applying the output of the reference signal generation circuit to the microcomputer as a clock signal means that the clock signal is externally supplied to the microcomputer without increasing the number of clock signal generation circuits supplied to the microcomputer.

The operation of the invention of claim 4 will be described below.
A signal that is a clock signal for the microcomputer is generated even in the standby state. Therefore, the microcomputer also operates in the standby state, and executes the predetermined operation in the standby state.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a video signal processing device according to the invention described in claims 1 and 2.

The video signal processing device according to the present invention is a device that includes, as a process within the device body, signal processing for separating a video signal which is a composite signal into a luminance signal and a chrominance signal. A television set or a video cassette recorder which processes a video signal such as an NTSC signal, a PAL signal, or a SECAM signal. In this embodiment, NT
It is a video cassette recorder that handles SC signals,
When roughly classified, it includes a microcomputer 1, a color signal separation circuit 2, a video mechanism section 3, and a video circuit section 4.

The microcomputer 1 is a block for controlling the operation as a video cassette recorder, and the CPU 11 which is the main part of the control, and the peripheral circuits 12, 32.76 which serve as an interface between the CPU 11 and the outside.
The oscillation circuit 13 to which the 8 KHz crystal oscillator 5 is connected, the input circuit 14 to which an external clock is input, and the output of the oscillation circuit 13 and the output of the input circuit 14 are switched to form a CPU.
A switch 15 for leading to 11 is provided.

The video mechanism unit 3 is a block composed of a rotary head, a capstan motor, a loading mechanism, etc., and the rotational speed of the capstan motor, the loading operation, etc. are controlled by the bidirectionally connected microcomputer 1. It The video circuit unit 4 performs a predetermined process on the circuit for recording the received video signal or a video signal given from the outside in the video cassette, and performs a predetermined process on the signal reproduced from the video cassette. This is a block for sending the video signal obtained by the above to the outside. The operation is controlled by the bidirectionally connected microcomputer 1.

The color signal separation circuit 2 uses a video signal (composite signal) 25 sent from the video circuit section 4 as a source signal, separates the source signal into a color signal 26 and a luminance signal 27, and separates the color signal. 26 and the luminance signal 27 are blocks for transmitting to the video circuit unit 4, and the reference signal generation circuit 6
And a YC separation circuit 24. The reference signal generation circuit 6 uses the 3.58 MHz crystal oscillator 21 as an oscillation element to generate a reference signal phase-synchronized with the burst signal in the video signal 25, and the oscillation circuit 22.
It is composed of a multiplication circuit 23 that multiplies the reference signal generated by 4 by 4. The reference signal generated by the oscillator circuit 22 is sent to the video circuit unit 4 as a signal for detecting a color difference signal. Then, the reference signal multiplied by 4 by the multiplication circuit 23 is sent to the YC separation circuit 24 and the input circuit 14 as a clock signal. The YC separation circuit 24 is a comb-type filter, and includes a delay element (CCD) that delays the video signal using the reference signal multiplied by the multiplication circuit 23 as a clock signal. Then, by detecting the line correlation, the video signal 25
Is separated into a color signal 26 and a luminance signal 27.

The operation of the embodiment having the above structure will be described below. In the standby state where commercial power is supplied and the video cassette recorder does not operate, power is supplied to the microcomputer 1.
No power is supplied to the video mechanism unit 3, the video circuit unit 4, and the color signal separation circuit 2. Further, the switch 15 guides the output of the oscillation circuit 13 to the CPU 11. Therefore, the microcomputer 1 performs a low-speed operation using a signal of approximately 32 KHz as a clock, and controls the timekeeping operation as a clock and the operation set as the standby state. The operation set as the standby state is the detection of the operation of the power switch for instructing the start of the operation as the video cassette recorder, the detection of the operation start instruction from the remote controller, or the like. In a power outage where commercial power supply is stopped,
The microcomputer 1 performs a timing operation with a backup power supply (not shown).

When an instruction to start the operation is given in the standby state, the microcomputer 1 controls to supply power to the color signal separation circuit 2, the video mechanism section 3 and the video circuit section 4. Next, the connection of the switch 15 is switched to guide the output of the input circuit 14 to the CPU 11. Therefore, the CPU 11 operates at a low speed using a signal of about 32 KHz as a clock signal, and outputs from the multiplying circuit 23 to about 14
The operation shifts to high-speed operation using the MHz signal as the clock signal. That is, the microcomputer 1 shifts to a high-speed operation capable of digitally controlling the capstan motor of the video mechanism unit 3. In this state, the microcomputer 1 controls the operation instructed by an external operation or the like.

When the instruction to shift to the standby state is given, the microcomputer 1 switches the switch 1
5 connection is switched, and the output of the oscillation circuit 13 is set to the CPU 11
Give to. Next, the video circuit unit 4, the video mechanism unit 3,
The power supply to the color signal separation circuit 2 is stopped.

FIG. 2 is a block diagram showing the electrical construction of an embodiment of a video signal recording medium reproducing apparatus according to the inventions described in claims 3 and 4. The video signal recording medium reproducing apparatus according to the present invention is an NTSC signal, a PAL signal, or an SE.
This is a device for reproducing a recording medium on which a video signal such as a CAM signal is recorded. The present embodiment is a video cassette player that reproduces a video cassette recorded with an NTSC signal.
1, a video reproduction unit 32, a color signal restoration circuit 33, a reference signal generation circuit 34, and a power supply control unit 36.

The microcomputer 31 is a block for controlling the operation as a video cassette player, and receives a CPU 38 which is a main part of control, a peripheral circuit 37 which is an interface between the CPU 38 and the outside, and an external clock. The input circuit 39 is provided. The video playback unit 32 includes a rotary head, a capstan motor,
The block is composed of a loading mechanism, a reproduction signal processing circuit, and the like. The rotational speed of the capstan motor, the loading operation, and the like are controlled by a bidirectionally connected microcomputer 31.

The color signal restoration circuit 33 includes a video reproduction section 32.
Is a block for converting the low-frequency converted color signal 41 taken out in step 2 into a color signal (carrier color signal) 42 carried by a carrier wave, based on the reference signal generated by the reference signal generation circuit 34. The converted color signal 41 is converted into the carrier color signal 42. The reference signal generation circuit 34 is
This is a block that generates a reference signal of the carrier color signal 42 by using the crystal oscillator 35 of 3.58 MHz as an oscillation element, and sends the generated reference signal to the color signal restoration circuit 33. The generated reference signal is used as a clock signal for the input circuit 3
9 is sent. The power supply control unit 36 supplies power to the microcomputer 31 and the reference signal generation circuit 34 in a standby state in which commercial power is supplied and does not operate as a video cassette player. This block supplies power to the block.

The operation of the embodiment having the above configuration will be described below. When commercial power is supplied, the microcomputer 31 and the reference signal generation circuit 34 are always supplied with power. Therefore, the reference signal generated by the reference signal generation circuit 34 is applied to the input circuit 39. Therefore, the microcomputer 31 always operates using the reference signal generated by the reference signal generation circuit 34 as a clock when commercial power is supplied. That is, in the standby state, the microcomputer 31 receives an instruction to start the operation and controls to supply power to all blocks. Then, the video cassette (not shown) is reproduced by performing control according to an instruction such as reproduction. Then, the reproduced video signal is sent to the outside by the output 43.

As described above, in the embodiment shown in FIG. 2, power is supplied to the microcomputer 31 and the reference signal generating circuit 34 even in the standby state. Further, the microcomputer 31 operates with a clock of 3.58 MHz which is a relatively high frequency. Therefore, the power consumption in the standby state becomes a load in which the operating region of the self-excited switching power supply is in the stable range. Therefore, it is possible to supply the DC source 44 supplied to the power supply control unit 36 with an inexpensive self-excited switching power supply.

[0023]

According to the first aspect of the present invention, there is provided a video signal processing device, comprising: a reference signal generating circuit provided with at least an oscillation circuit for generating a reference signal corresponding to a burst signal; and an output of the reference signal generating circuit. As a clock, a YC separation circuit that separates a video signal into a luminance signal and a chrominance signal is provided, and is applied to a device that controls the operation of the device body using a microcomputer. The output of the reference signal generation circuit is given to the microcomputer as a clock signal. Therefore, the output generated in the block, which is indispensable for the device, is given to the microcomputer as a clock signal, so that a crystal oscillator that generates a control clock during the operation of the device body without increasing the number of circuits. Can be eliminated.

According to a second aspect of the present invention, in the video signal processing device, the reference signal generation circuit is provided with a multiplication circuit for multiplying the output frequency of the oscillation circuit, and the YC separation circuit uses the output of the multiplication circuit as a clock. It is applied to a device that separates a color signal and a luminance signal. The output of the multiplication circuit is given to the microcomputer as a clock signal.
Therefore, a high-frequency signal is supplied to the microcomputer as a clock signal, so that the microcomputer can be operated at high speed even when the crystal oscillator for control during the operation of the apparatus body is unnecessary. There is.

A video signal recording medium reproducing apparatus according to a third aspect of the present invention is applied to an apparatus for reproducing the video signal recording medium and controlling the operation of the apparatus main body by using a microcomputer. Then, the microcomputer uses the output of the reference signal generation circuit that sends the reference signal corresponding to the carrier of the color signal to the color signal restoration circuit that restores the color signal based on the signal reproduced from the video signal recording medium as a clock signal. Is given to. Therefore, the output generated in the block, which is indispensable for the device, is given to the microcomputer as a clock signal, so that a crystal oscillator that generates a control clock during the operation of the device body without increasing the number of circuits. Can be eliminated.

Further, the video signal recording medium reproducing apparatus according to the invention of claim 4 is provided with at least a power supply control section for supplying an operation power supply to the microcomputer and the oscillation circuit in a standby state of the operation as the apparatus main body. It has a structure. Therefore, the microcomputer operates even in the standby state, so that the microcomputer can perform the standby process.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a video signal processing device according to the inventions of claims 1 and 2. FIG.

FIG. 2 is a block diagram showing an electrical configuration of an embodiment of a video signal recording medium reproducing apparatus according to the invention described in claims 3 and 4.

FIG. 3 is a block diagram showing a configuration of a microcomputer according to a conventional technique.

[Explanation of symbols]

 1 Microcomputer 2 Color signal separation circuit 6 Reference signal generation circuit 22 Oscillation circuit 23 Multiplication circuit 24 YC separation circuit 31 Microcomputer 33 Color signal restoration circuit 34 Reference signal generation circuit 36 Power supply control section

Claims (4)

[Claims] 1. A reference signal generation circuit provided with at least an oscillation circuit for generating a reference signal corresponding to a burst signal, and a video signal separated into a luminance signal and a chrominance signal using the output of the reference signal generation circuit as a clock. And a YC separation circuit for controlling the operation of the apparatus main body using a microcomputer, wherein the output of the reference signal generation circuit is given to the microcomputer as a clock signal. apparatus. 2. The reference signal generation circuit includes a multiplication circuit that multiplies the output frequency of the oscillation circuit, and the YC separation circuit uses the output of the multiplication circuit as a clock to generate the color signal and the luminance signal. 2. The video signal processing apparatus according to claim 1, wherein in the separation device, the output of the multiplication circuit is given to the microcomputer as a clock signal. 3. A color signal that restores a color signal based on a signal reproduced from the video signal recording medium in a device that reproduces the video signal recording medium and controls the operation of the apparatus main body by using a microcomputer. A video signal recording medium reproducing apparatus characterized in that an output of a reference signal generating circuit for transmitting a reference signal corresponding to the carrier wave of the color signal is given to the microcomputer as a clock signal to the restoring circuit. 4. The image according to claim 3, further comprising a power supply control unit that supplies an operation power supply to at least the microcomputer and the oscillation circuit in a standby state of the operation of the apparatus body. Signal recording medium reproducing device.