JP3149901B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates a stated frequency signal that is generated for processing the video signal, as a clock signal, the video signal processing equipment given to the microcomputer for controlling the apparatus main body .

[0002]

2. Description of the Related Art In a video cassette recorder, a microcomputer is used for controlling the operation as an apparatus main body and controlling the rotation speed of a capstan motor and the like. Further, the microcomputer is configured to perform the operation of measuring the time even at the time of a power failure when the supply of commercial power is stopped. FIG. 2 shows a conventional technique for performing the above-described operation.
Are provided with two oscillation circuits 95 and 96. The oscillation circuit 95 has a crystal oscillator 9 of 32.768 kHz.
2 and the oscillation circuit 96 is connected to a crystal oscillator 93 of 12 MHz or the like. In the standby state of the operation, only the oscillation circuit 95 is operated and the oscillation circuit 9 is operated.
5 is sent to the CPU 97. Therefore, the microcomputer 91 performs the clocking operation with low power consumption. In addition, the control operation required in the standby state is performed. On the other hand, when operating, the output of the oscillation circuit 96 is guided to the CPU 97. Therefore, the microcomputer 91 performs a high-speed operation according to a high-frequency clock, and controls the rotation speed of the capstan motor or the like, or controls other operations.

[0003]

As described above, the microcomputer 91 includes the crystal oscillator 92 for generating the clock in the standby state and the crystal oscillator 93 for generating the clock in the operation state. It is connected. That is, the microcomputer 91 needs two types of crystal oscillators 92 and 93. However, since the crystal oscillators 92 and 93 are expensive elements, the use of two types of crystal oscillators 92 and 93 has caused a problem that the price of the device increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has as its object to control a main body of a device by using a signal having a fixed frequency generated for processing a video signal as a clock signal. A video signal processing device and a video signal recording medium reproducing device that can eliminate the need for a crystal oscillator that generates a control clock during operation of the device main body without increasing the number of circuits by providing the microcomputer to the microcomputer. To provide. In addition to the above object, a video signal processing apparatus capable of operating a microcomputer at high speed by supplying a high frequency clock signal even when a crystal oscillator for control during the operation of the apparatus body is unnecessary. Is to provide .

[0005]

According to the present invention, there is provided a video signal processing apparatus comprising: a reference signal generation circuit provided with at least an oscillation circuit for generating a reference signal corresponding to a burst signal; A YC separation circuit that separates a video signal into a luminance signal and a chrominance signal using the output of the signal generation circuit as a clock, wherein the microcomputer controls the operation of the apparatus main body using the microcomputer; an oscillation circuit for generating a clock signal for low-speed operation by using the crystal oscillator, the slow
A switch for switching and outputting an output of an oscillation circuit for generating an operation clock signal and an output of the reference signal generation circuit; and when the supply of power to the reference signal generation circuit is stopped, the switch is provided. Is for the low speed operation
The switch sends out the output of the reference signal generation circuit when power is supplied to the reference signal generation circuit, and the microcomputer sends out the output of the switch when the power is supplied to the reference signal generation circuit. The output is operated as a clock signal. Further, in addition to the above configuration, the burst signal is supplied to the reference signal generation circuit.
A multiplying circuit for multiplying the output frequency of the oscillation circuit that generates the reference signal corresponding to the signal , and the YC separation circuit is applied to a device that separates a chrominance signal and a luminance signal using the output of the multiplication circuit as a clock; The output of the multiplying circuit is provided to a microcomputer as a clock signal .

[0006]

The operation of the present invention will be described below. A reference signal generation circuit provided with at least an oscillation circuit for generating a reference signal corresponding to the burst signal; a YC separation circuit for separating a video signal into a luminance signal and a chrominance signal using an output of the reference signal generation circuit as a clock; Is an indispensable block in a video signal processing device that separates a video signal into a color signal and a luminance signal. Therefore, providing the output of the reference signal generation circuit to the microcomputer as a clock signal means that the clock signal is externally supplied to the microcomputer without increasing the number of clock signal generation circuits supplied to the microcomputer.

[0007] Further action will be described below. The output frequency of the oscillation circuit is a frequency determined by a target video signal. For example, when the video signal is an NTSC signal, the output frequency is 3.58 MHz. For this reason, the output of the multiplication circuit has a frequency that is an integral multiple of that, and has a high frequency. Since the high frequency signal is supplied to the microcomputer as a clock signal, the microcomputer operates at high speed .

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a video signal processing device according to the present invention.

A video signal processing device according to the present invention is a device that includes, as a process in the device main body, signal processing for separating a video signal, which is a composite signal, into a luminance signal and a chrominance signal. It is a television or a video cassette recorder that processes video signals such as NTSC signals, PAL signals, or SECAM signals. In this embodiment, NT
It is a video cassette recorder that handles SC signals,
When roughly classified, a microcomputer 1, a color signal separation circuit 2, a video mechanism unit 3, and a video circuit unit 4 are provided.

The microcomputer 1 is a block for controlling the operation as a video cassette recorder. The microcomputer 11 is a main part of the control, and the peripheral circuits 12 and 32.76 are interfaces between the CPU 11 and the outside.
An oscillation circuit 13 to which an 8 KHz crystal oscillator 5 is connected, an input circuit 14 to which an external clock is input, and a CPU that switches between the output of the oscillation circuit 13 and the output of the input circuit 14
There is provided a switch 15 for leading to 11.

The video mechanism section 3 is a block comprising a rotary head, a capstan motor, a loading mechanism, and the like. The rotation speed or the loading operation of the capstan motor is controlled by a microcomputer 1 connected in two directions. You. The video circuit unit 4 performs a predetermined process on a circuit for recording a received video signal or an externally supplied video signal on a video cassette, and performs a predetermined process on a signal reproduced from the video cassette. This is a block for sending the video signal obtained as described above to the outside. The operation is controlled by the microcomputer 1 connected in two directions.

The color signal separation circuit 2 uses a video signal (composite signal) 25 sent from the video circuit section 4 as a source signal, separates the source signal into a color signal 26 and a luminance signal 27, and separates the separated color signal. 26 and a luminance signal 27 to the video circuit unit 4.
And a YC separation circuit 24. The reference signal generation circuit 6 uses a 3.58 MHz crystal oscillator 21 as an oscillation element to generate a reference signal synchronized with a burst signal of the video signal 25 and an oscillation circuit 22.
Is multiplied by 4 to multiply the generated reference signal. The reference signal generated by the oscillation circuit 22 is sent to the video circuit unit 4 as a signal for detecting a color difference signal. The reference signal quadrupled by the multiplying circuit 23 is sent to the YC separation circuit 24 and the input circuit 14 as a clock signal. The YC separation circuit 24 is a comb filter, and includes a delay element (CCD) that delays a video signal using the reference signal multiplied by the multiplication circuit 23 as a clock signal. Then, by detecting the line correlation, the video signal 25 is detected.
Into a color signal 26 and a luminance signal 27.

The operation of the embodiment having the above configuration will be described below. In a standby state where commercial power is supplied and the operation as a video cassette recorder is not performed, power is supplied to the microcomputer 1.
Power is not supplied to the video mechanism unit 3, the video circuit unit 4, and the color signal separation circuit 2. The switch 15 guides the output of the oscillation circuit 13 to the CPU 11. Therefore, the microcomputer 1 performs a low-speed operation using a signal of approximately 32 KHz as a clock, and controls a clock operation as a clock and an operation set as a standby state. The operation set as the standby state includes detection of operation of a power switch for instructing start of operation as a video cassette recorder, detection of operation start instruction from a remote controller, and the like. In the power outage state where the supply of commercial power is stopped,
The microcomputer 1 performs a timing operation with a backup power supply (not shown).

When an operation start instruction is given in the standby state, the microcomputer 1 controls to supply power to the color signal separation circuit 2, the video mechanism section 3, and the video circuit section 4. Next, the connection of the switch 15 is switched, and the output of the input circuit 14 is led to the CPU 11. For this reason, the CPU 11 starts the low-speed operation using the signal of about 32 KHz as the clock signal,
The operation shifts to a high-speed operation using a MHz signal as a clock signal. That is, the microcomputer 1 shifts to a high-speed operation in which digital control of the capstan motor and the like of the video mechanism unit 3 is possible. In this state, the microcomputer 1 controls an operation specified by an external operation or the like.

When an instruction to shift to the standby state is given, the microcomputer 1 operates the switch 1
5 and the output of the oscillation circuit 13 is
Give to. Next, the video circuit unit 4, the video mechanism unit 3,
Then, the supply of power to the color signal separation circuit 2 is stopped .

[0016]

According to the present invention, there is provided a video signal processing apparatus comprising: a reference signal generating circuit having at least an oscillation circuit for generating a reference signal corresponding to a burst signal; A YC separation circuit for separating signals into a luminance signal and a chrominance signal, wherein the microcomputer controls the operation as an apparatus body using a quartz oscillator for low-speed operation. An oscillation circuit that generates a clock signal; and a switch that switches and outputs an output of the oscillation circuit that generates the clock signal for the low-speed operation and an output of the reference signal generation circuit. when the supply of power is stopped, the switch sends the output of the oscillation circuit for generating a clock signal for said low-speed operation, the When power is supplied to the quasi-signal generation circuit, the switch sends the output of the reference signal generating circuit, wherein the microcomputer has a configuration to operate the output outputted from the switch as a clock signal. For this reason, an output generated in a block which is indispensable as a device is supplied to a microcomputer as a clock signal, so that a crystal oscillator which generates a control clock during operation of the device body without increasing the number of circuits. Is unnecessary.

Further, a bar is added to the reference signal generation circuit.
A multiplying circuit for multiplying an output frequency of an oscillation circuit for generating a reference signal corresponding to the strike signal . The YC separation circuit is applied to a device for separating a chrominance signal and a luminance signal using the output of the multiplication circuit as a clock. ing. The output of the multiplication circuit is provided to the microcomputer as a clock signal. Because a high-frequency signal is supplied to the microcomputer as a clock signal, the microcomputer can operate at high speed even when a crystal oscillator for control during the operation of the apparatus main body is not required. I have .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a video signal processing device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a microcomputer according to the related art.

[Explanation of symbols]

1 microcomputer 2 color signal separating circuit 6 the reference signal generating circuit 22 the oscillation circuit 23 multiplying circuit 24 YC separation circuits

Claims (2)

(57) [Claims] 1. A reference signal generation circuit provided with at least an oscillation circuit for generating a reference signal corresponding to a burst signal, and a video signal is separated into a luminance signal and a chrominance signal using an output of the reference signal generation circuit as a clock. A YC separation circuit for controlling the operation of the apparatus body using a microcomputer, wherein the microcomputer includes: an oscillation circuit that generates a clock signal for low-speed operation using a crystal oscillator; Low
A switch for switching and outputting an output of an oscillation circuit for generating a clock signal for high-speed operation and an output of the reference signal generation circuit, and when the supply of power to the reference signal generation circuit is stopped, The switch generates the clock signal for the low-speed operation.
The output of the oscillation circuit to be generated is transmitted, and when power is supplied to the reference signal generation circuit, the switch transmits the output of the reference signal generation circuit, and the microcomputer outputs the output transmitted from the switch. A video signal processing device that operates as a clock signal. 2. The method according to claim 2, wherein the reference signal generation circuit is configured to generate the burst signal.
A multiplying circuit for multiplying an output frequency of an oscillation circuit for generating a reference signal corresponding to the signal , wherein the YC separation circuit separates the chrominance signal and the luminance signal using an output of the multiplication circuit as a clock 2. The video signal processing device according to claim 1, wherein an output of the multiplying circuit is provided to the microcomputer as a clock signal .