JPH0851152A - Manufacture of electrode wiring and processing equipment thereof - Google Patents

Manufacture of electrode wiring and processing equipment thereof

Info

Publication number
JPH0851152A
JPH0851152A JP18701294A JP18701294A JPH0851152A JP H0851152 A JPH0851152 A JP H0851152A JP 18701294 A JP18701294 A JP 18701294A JP 18701294 A JP18701294 A JP 18701294A JP H0851152 A JPH0851152 A JP H0851152A
Authority
JP
Japan
Prior art keywords
substrate
wiring
region
electrode wiring
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18701294A
Other languages
Japanese (ja)
Inventor
Kenji Hinode
憲治 日野出
Nobuyoshi Kobayashi
伸好 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18701294A priority Critical patent/JPH0851152A/en
Publication of JPH0851152A publication Critical patent/JPH0851152A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a wiring metal into a connecting hole section having a high aspect ratio with a sufficient coating rate by a method wherein a metallic region machined in a specified shape is formed, the region of a substance of a different kind uniformly covering the metallic region is applied and formed, stress is applied and the metallic region is deformed. CONSTITUTION:A polycrystalline silicon electrode wiring 21 and a tungsten wiring are shaped onto a substrate 11, a foundation insulating film 32 for forming a wiring by this invention is formed, and a connecting hole 41 with a lower layer is bored. An electrode wiring 23 is buried and shaped into the connecting hole 41 by a forming process of a metallic film 23 having a high ductility consisting of Al, Cu, an alloy thereof, etc., and succeeding pressure treatment. That is, the region of a substance 24 of a different kind uniformly coating the region of the metallic film 23 or the surface of the substrate 11 is applied and formed or mounted, stress having a component in the vertical direction is applied to the surface of the substrate 11, and the region of the metallic film 23 is deformed. Accordingly, the connecting hole 41 having a high aspect ratio can be filled with a metal abounding in ductility by a simple treatment, thus realizing an improvement in the reliability of the connecting hole wiring.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置用電極配線に
係り、特に、高アスペクト比の縦方向の接続孔配線の形
成に好適な電極配線の製造方法および処理装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device electrode wiring, and more particularly to a method and a processing apparatus for manufacturing electrode wiring suitable for forming a vertical connection hole wiring having a high aspect ratio.

【0002】[0002]

【従来の技術】半導体装置の高集積化に対応するため配
線では多層化という方法が採用されている。この多層配
線における層間の接続孔や、半導体基板内に形成された
能動部分との接続電極との接続孔は、集積度の増加とと
もにアスペクト比(深さ/孔径の比)が高くなってい
る。現在の代表的な金属膜形成法であるスパッタ法で
は、このようにアスペクト比の高い接続孔に十分な被覆
率の膜を形成することが困難であり、幾つかの新しい方
法もしくは従来法を改良した方法が検討され、適用され
始めている。その代表的なものを次にあげる。
2. Description of the Related Art In order to cope with high integration of semiconductor devices, a method of forming multiple layers in wiring is adopted. The aspect ratio (ratio of depth / hole diameter) of the connection hole between the layers in the multilayer wiring and the connection hole with the connection electrode with the active portion formed in the semiconductor substrate is increased as the integration degree is increased. It is difficult to form a film with sufficient coverage in such a high aspect ratio contact hole by the sputtering method, which is the current typical metal film forming method, and some new methods or conventional methods have been improved. The methods have been studied and are being applied. The representative ones are listed below.

【0003】 CVD法によるブランケットW(もし
くはAl)膜の形成 選択CVD法によるプラグ電極配線の形成(Wもし
くはAl) バイアスもしくは高温スパッタ法による凹部の埋め
込み(Al合金) 膜形成後の高温処理による凹部の埋め込み(Al合
金) 膜形成後の加圧処理による凹部の埋め込み(Al合
金) 〜はスパッタ法を前提にしており制御が比較的容易
である。
Formation of Blanket W (or Al) Film by CVD Method Formation of Plug Electrode Wiring by Selective CVD Method (W or Al) Filling of Cavity by Bias or High Temperature Sputtering Method (Al Alloy) Cavity by High Temperature Treatment After Film Formation (Al alloy) The filling of the concave portion by the pressure treatment after the film formation (Al alloy) is based on the sputtering method and is relatively easy to control.

【0004】[0004]

【発明が解決しようとする課題】の方法は、特開平3
−225829 号,特開平5−29470号公報、および特願平4−
229723号明細書で提案されているものである。基本的に
は膜を形成した基板を等方的に加圧して凹部へAl合金
を押し込むものであるが次のような課題が残っている。
The method of [Problems to be Solved by the Invention]
-225829, JP-A-5-29470, and Japanese Patent Application No. 4-
It is proposed in the specification of 229723. Basically, the substrate on which the film is formed is isotropically pressed to press the Al alloy into the recess, but the following problems remain.

【0005】 埋め込み特性が不十分で、膜が連続で
気密な状態でないと十分に押し込まれない。膜が変形し
て破断するとそれ以上埋め込まれない。深い凹部の埋め
込みには実際必要以上の厚さのAl合金膜を形成し、一
旦、埋め込んだ後、一部を除去する等のプロセスが必要
になる。
The embedding property is insufficient and the film is not sufficiently pushed unless it is in a continuous and airtight state. When the membrane deforms and breaks, it is not embedded any more. In order to fill deep recesses, a process of forming an Al alloy film having a thickness more than necessary, once filling, and then partially removing it is necessary.

【0006】 気体,液体を圧力媒体とする等方加圧
法となるため装置の危険度(爆発等)が高い。圧力を下
げるには高温が必要になる。
Since the isotropic pressurization method uses gas or liquid as a pressure medium, the degree of danger (explosion, etc.) of the device is high. High temperature is required to reduce the pressure.

【0007】本発明の目的は、プロセスが簡単で制御性
が良く、かつ埋め込み特性が良い電極配線の製造方法を
提供することにある。
An object of the present invention is to provide a method of manufacturing an electrode wiring which has a simple process, good controllability, and good embedding characteristics.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するた
め、本発明ではAl,Cu,Ag,Au等の延性の高い
金属膜の形成工程と、それに引き続く加圧処理により基
板表面に形成した凹部へ電極配線を埋設形成するもので
ある。その際、特に変形させる金属より弾性率の小さい
異種物質のバッファ層を金属膜上に設ければ、加圧のた
めに一軸性の圧縮力を用いることが可能となり、比較的
容易に高圧力が達成できるので処理の低温化,高速化を
図ることができ、上記と、特にの課題を解決でき
る。また、変形させる金属より弾性率の大きい異種物質
のバッファ層を金属膜上に設ければ、金属層を特に厚膜
化せずに等方性の圧力を加えても高い埋め込み特性を得
ることができ、上記の課題を解決できる。
In order to achieve the above object, according to the present invention, a step of forming a highly ductile metal film of Al, Cu, Ag, Au, etc., and a recess formed on the surface of the substrate by a subsequent pressure treatment. The electrode wiring is buried and formed. At that time, in particular, if a buffer layer made of a different material having a smaller elastic modulus than the metal to be deformed is provided on the metal film, it becomes possible to use a uniaxial compressive force for pressurization, and the high pressure can be relatively easily applied. Since this can be achieved, the processing temperature can be lowered and the processing speed can be increased, and the above and particularly the problems can be solved. Further, if a buffer layer of a different material having a higher elastic modulus than the metal to be deformed is provided on the metal film, a high embedding property can be obtained even if an isotropic pressure is applied without increasing the thickness of the metal layer. Therefore, the above problems can be solved.

【0009】[0009]

【作用】面心立方構造の金属(Al,Cu,Ag,Au
やその合金等)は延性に富み、応力を加えると、ある程
度まで破断せずに変形する。この性質を利用して、凹凸
のある基板上に被着形成した金属膜を基板表面の形状に
沿うコンフォーマルな形に変形させ金属膜被着の際に生
じた空洞等を消滅させることができる。最も効果的に金
属膜を変形させるには施す応力の向きを適正にする必要
がある。通常利用できる加圧法では等方的な圧力もしく
は一方向性(一軸性)の圧力は容易に発生できるが、両
者の中間的な圧力は発生しにくく、実際望ましいのはこ
の様な中間的な方向を持つ圧力である。
Operation: Face-centered cubic metal (Al, Cu, Ag, Au
And its alloys) are rich in ductility, and when stress is applied, they deform to some extent without breaking. By utilizing this property, the metal film deposited on the uneven substrate can be transformed into a conformal shape that conforms to the shape of the substrate surface, and the cavities and the like generated during the deposition of the metal film can be eliminated. . In order to most effectively deform the metal film, it is necessary to set the direction of the applied stress to be appropriate. Isotropic pressure or unidirectional (uniaxial) pressure can be easily generated by the pressurizing method that can be usually used, but intermediate pressure between both is difficult to generate. Actually, it is desirable to use such an intermediate direction. Is a pressure with.

【0010】孔の埋め込みを例にとって少し詳しく説明
する。孔周辺の金属は孔に向かって基板面と平行に移動
させ、また孔直上の金属は孔の内部に向かって基板面に
垂直に移動させなければ効率的な埋め込みはできない。
金属膜の場所に対応して必要な移動方向の力を加えるの
が最も望ましいが、現実に場所によって力の向きを制御
して変えるのは非常に難しい。そこで中間的な向きの応
力を加えるのが最も効率的と考えられる。
The embedding of holes will be described in some detail. Efficient embedding cannot be achieved unless the metal around the hole is moved parallel to the substrate surface toward the hole, and the metal immediately above the hole is moved toward the inside of the hole perpendicularly to the substrate surface.
It is most desirable to apply a necessary force in the moving direction corresponding to the location of the metal film, but it is very difficult to control and change the direction of the force in reality. Therefore, it is considered most effective to apply stress in an intermediate direction.

【0011】本発明のバッファ層を用いた方法によれば
通常の、等方的もしくは一方向性の加圧装置でも望まし
い向きの圧力を加えることができる。等方的な加圧装置
を用いる場合は、金属膜より変形しにくい(弾性定数が
大きい)材料でバッファ層を形成するとよく、一方向性
の加圧装置を用いる場合は、金属膜より変形しやすい
(弾性定数が小さい)材料でバッファ層を形成するとよ
いことになる。
According to the method using the buffer layer of the present invention, it is possible to apply a pressure in a desired direction even with a normal, isotropic or unidirectional pressure device. When an isotropic pressure device is used, the buffer layer should be made of a material that is more difficult to deform than the metal film (has a large elastic constant). When a unidirectional pressure device is used, the buffer layer should not be deformed. It is preferable to form the buffer layer with a material that is easy (having a small elastic constant).

【0012】[0012]

【実施例】【Example】

(実施例1)図1ないし図4は本発明の実施例を示すシ
リコン半導体装置の断面図である。図1から図4の順に
工程を経て配線系を製造した。
(Embodiment 1) FIGS. 1 to 4 are sectional views of a silicon semiconductor device showing an embodiment of the present invention. A wiring system was manufactured through steps in the order of FIG. 1 to FIG.

【0013】この配線系は次のような通常のシリコン半
導体素子製造工程および本発明の処理とで作成した。即
ち、シリコン基板11の表面に能動部分を作成した後、
絶縁膜層を介しながら多結晶シリコンの電極配線21,
タングステン配線22を形成し、本発明の配線を形成す
るための下地絶縁膜32を形成し、下層との接続孔41
を開口した。引き続き、Al−1%Si合金膜23をス
パッタ法で形成した。スパッタ法では段差被覆率が低い
ため、図1に示すように接続孔内部は埋まらずに空洞が
残った。この基板表面にPIQ層24をスピンコート法
で形成し450℃でベーク(加熱)した。
This wiring system was prepared by the following ordinary silicon semiconductor device manufacturing process and the process of the present invention. That is, after forming the active portion on the surface of the silicon substrate 11,
Polycrystalline silicon electrode wiring 21, with an insulating film layer interposed,
A tungsten wiring 22 is formed, a base insulating film 32 for forming the wiring of the present invention is formed, and a connection hole 41 with a lower layer is formed.
Opened. Then, the Al-1% Si alloy film 23 was formed by the sputtering method. Since the step coverage is low in the sputtering method, as shown in FIG. 1, the inside of the connection hole was not filled and a cavity remained. The PIQ layer 24 was formed on the surface of the substrate by spin coating and baked (heated) at 450 ° C.

【0014】図2に示すように、この基板を油圧プレス
機のヘッド51下にセットし、圧力を印加した。この状
態で基板の断面を観察すると接続孔部にあった空洞は消
滅し、接続孔はAl合金23で満たされた。
As shown in FIG. 2, this substrate was set under the head 51 of a hydraulic press and pressure was applied. When the cross section of the substrate was observed in this state, the cavities in the connection holes disappeared and the connection holes were filled with Al alloy 23.

【0015】接続孔部の空洞をAlで満たすための最低
圧力は加圧時間,素子の構造や膜厚,金属の種類にもよ
るが、Al合金では室温では約100MPa程度、温度
を上げると所要圧力は次第に減少し、200℃(絶対温
度でほぼ融点の1/2)では50MPa程度、さらに高
温ではより低圧力になり、400℃では20MPa程度
まで下がる。
The minimum pressure for filling the cavity of the connection hole with Al depends on the pressurizing time, the structure and film thickness of the element, and the type of metal, but for Al alloys, it is about 100 MPa at room temperature, and it is necessary to raise the temperature. The pressure gradually decreases, and becomes about 50 MPa at 200 ° C. (about 1/2 of the melting point in absolute temperature), becomes lower at higher temperature, and drops to about 20 MPa at 400 ° C.

【0016】その後油圧プレス機のヘッド51から基板
をはずし、酸素を用いたプラズマアッシング装置でPI
Q層24を除去し、図3の構造とする。引き続きホトエ
ッチング法によりAlの領域23を図4のように所望の
形状にパターニングする。Alの領域内にある空洞の割
合が少ない場合は、このようにパターニングした後、P
IQ層を設けて圧力を印加してもよい。
After that, the substrate was removed from the head 51 of the hydraulic press machine, and the plasma ashing device using oxygen was used for PI.
The Q layer 24 is removed to obtain the structure shown in FIG. Subsequently, the Al region 23 is patterned into a desired shape by photoetching as shown in FIG. When the ratio of the cavities in the Al region is small, after patterning as described above, P
An IQ layer may be provided and pressure may be applied.

【0017】本実施例はAl−1%Si合金膜を用いて
行ったが、純Al,Al−Cu(−Si)合金等でもほ
ぼ同様な条件で埋め込みができる。また、Al−Ge
等、非常に低い共晶温度(424℃)を有する合金では
上記の条件よりさらに低温で埋め込みができる。また、
これらAl合金層の上下等に高融点金属の層を設けた積
層膜でも同様に埋め込みが可能である。このように材料
および膜形成条件による多少の変動はあるが、Alを主
成分とする合金ではこの処理法により十分な信頼度のあ
る埋め込みができる。
Although this embodiment was carried out using an Al-1% Si alloy film, pure Al, Al--Cu (-Si) alloy, etc. can be embedded under substantially the same conditions. In addition, Al-Ge
For example, alloys having a very low eutectic temperature (424 ° C.) can be embedded at a temperature lower than the above conditions. Also,
It is possible to similarly embed a laminated film in which layers of refractory metal are provided above and below these Al alloy layers. Although there are some variations depending on the material and the film forming conditions as described above, with an alloy containing Al as a main component, this treatment method enables filling with sufficient reliability.

【0018】また下地基板への影響等の問題がなければ
Al合金より高融点の材料についても同様に適用するこ
とができる。たとえば銅では400〜500℃以上で同
様の効果を得ることができた。
Further, a material having a melting point higher than that of an Al alloy can be similarly applied if there is no problem such as influence on the base substrate. For example, with copper, a similar effect could be obtained at 400 to 500 ° C. or higher.

【0019】PIQの弾性定数はAlの1/10以下
で、膜厚がAlと同程度から100倍程度の範囲では良
好な埋め込みが実現できた。
The elastic constant of PIQ is 1/10 or less of that of Al, and good embedding can be realized when the film thickness is in the range of about 100 to 100 times that of Al.

【0020】さらに簡便な方法としてローラ等による加
圧でも埋め込みは可能であり、その際はバッファ層厚を
厚めにし、Alの膜厚の数倍以上の方が埋め込み特性は
良好であった。
As a simpler method, it is possible to embed by pressing with a roller or the like. In that case, the embedding characteristics were better when the buffer layer thickness was made thicker and the film thickness of Al was several times or more.

【0021】(実施例2)図5ないし図8は本発明の実
施例を示すシリコン半導体装置の断面図である。図5か
ら図8の順に工程を経て配線系を製造した。この配線系
も実施例1と同様に次のような通常のシリコン半導体素
子製造工程および本発明の処理とで作成した。
(Embodiment 2) FIGS. 5 to 8 are sectional views of a silicon semiconductor device showing an embodiment of the present invention. A wiring system was manufactured through steps in the order of FIG. 5 to FIG. This wiring system was also manufactured by the following ordinary silicon semiconductor device manufacturing process and the process of the present invention as in the first embodiment.

【0022】即ち、シリコン基板11表面に能動部分を
作成した後、絶縁膜層を介しながら多結晶シリコンの電
極配線21,タングステン配線22を形成し、本発明の
配線を形成するための下地絶縁膜32を形成し、下層と
の接続孔41を開口した。それと同時に配線を形成する
べき位置に溝を形成した。引き続き、Al−1%Si合
金膜23をスパッタ法で形成した。スパッタ法では段差
被覆率が低いため、図5に示すように接続孔内部は埋ま
らずに空洞が残った。この基板表面に十分前処理(平滑
化,洗浄,脱気等)したテフロンシート25を設置し
た。
That is, after forming the active portion on the surface of the silicon substrate 11, the polycrystalline silicon electrode wiring 21 and the tungsten wiring 22 are formed with the insulating film layer interposed therebetween to form the underlying insulating film for forming the wiring of the present invention. 32 was formed, and the connection hole 41 with the lower layer was opened. At the same time, a groove was formed at the position where the wiring should be formed. Then, the Al-1% Si alloy film 23 was formed by the sputtering method. Since the step coverage is low in the sputtering method, as shown in FIG. 5, the inside of the connection hole was not filled and a cavity remained. A Teflon sheet 25 that had been sufficiently pretreated (smoothed, washed, deaerated, etc.) was placed on the surface of this substrate.

【0023】図6に示すように、この基板を油圧プレス
機のヘッド51下にセットし、圧力を印加した。この状
態で基板の断面を観察すると接続孔部にあった空洞は消
滅し、接続孔はAlで満たされた。やはりこの場合も加
熱により埋め込みに必要な圧力を下げることができた。
As shown in FIG. 6, this substrate was set under the head 51 of a hydraulic press and pressure was applied. When the cross section of the substrate was observed in this state, the cavities in the connection holes disappeared and the connection holes were filled with Al. In this case as well, the pressure required for filling could be lowered by heating.

【0024】その後油圧プレス機のヘッド51から基板
をはずし、テフロンシートを取外し、図7の構造とす
る。
After that, the substrate is removed from the head 51 of the hydraulic press and the Teflon sheet is removed to obtain the structure shown in FIG.

【0025】配線を形成すべき溝部以外に残ったAl2
3を、図8のように研磨もしくはエッチバックにより除
去すれば、所望の形状にパターニングされたAlの領域
23′が形成される。
Al2 remaining in the groove other than the groove for forming the wiring
3 is removed by polishing or etchback as shown in FIG. 8, the Al region patterned into a desired shape
23 'is formed.

【0026】テフロンの弾性定数はAlの1/10以下
で、膜厚がAlと同程度から100倍程度の範囲では良
好な埋め込みが実現できた。
The elastic constant of Teflon is 1/10 or less of that of Al, and good embedding can be realized when the film thickness is in the range of about 100 to 100 times that of Al.

【0027】(実施例3)図9ないし図11は本発明の
実施例を示すシリコン半導体装置の断面図である。図9
から図11の順に工程を経て配線系を製造した。この配
線系は次のような通常のシリコン半導体素子製造工程お
よび本発明の処理とで作成した。
(Embodiment 3) FIGS. 9 to 11 are sectional views of a silicon semiconductor device showing an embodiment of the present invention. Figure 9
Then, the wiring system was manufactured through the steps in the order of FIG. This wiring system was created by the following ordinary silicon semiconductor device manufacturing process and the process of the present invention.

【0028】即ち図9のように、シリコン基板11の表
面に能動部分を作成した後、絶縁膜層を介しながら多結
晶シリコンの電極配線21,タングステン配線22を形
成し、本発明の配線を形成するための下地絶縁膜32を
形成し、下層との接続孔41を開口した。引き続き、A
l−1%Si合金膜23,W層26をスパッタ法で積層
して形成した。スパッタ法では段差被覆率が低いため、
図9に示すように接続孔内部はAl合金で埋まらずに空
洞が残った。
That is, as shown in FIG. 9, after forming an active portion on the surface of the silicon substrate 11, an electrode wiring 21 and a tungsten wiring 22 of polycrystalline silicon are formed with an insulating film layer interposed therebetween to form the wiring of the present invention. A base insulating film 32 for forming the film is formed, and a connection hole 41 with the lower layer is opened. Continue to A
The 1-1% Si alloy film 23 and the W layer 26 were formed by laminating by a sputtering method. Since the step coverage is low in the sputtering method,
As shown in FIG. 9, the inside of the connection hole was not filled with the Al alloy and a cavity remained.

【0029】図10に示すように、この基板を加圧タン
ク中にセットし、圧力を印加した。この状態で基板の断
面を観察すると接続孔部にあった空洞は消滅し、接続孔
はAlで満たされた。
As shown in FIG. 10, this substrate was set in a pressure tank and pressure was applied. When the cross section of the substrate was observed in this state, the cavities in the connection holes disappeared and the connection holes were filled with Al.

【0030】接続孔部の空洞をAlで満たすための最低
圧力は加圧時間,素子の構造や膜厚,金属の種類にもよ
るが室温では約300MPa程度、温度を上げると次第
に減少し、200℃(絶対温度でほぼ融点の1/2)で
は200MPa程度、さらに高温ではより低圧力にな
り、400℃では100MPa程度まで下がる。
The minimum pressure for filling the cavity of the connection hole with Al depends on the pressurizing time, the structure and film thickness of the element, and the kind of metal, but it is about 300 MPa at room temperature, and gradually decreases when the temperature is raised to 200 At 200C (about 1/2 of the melting point in absolute temperature), the pressure is about 200 MPa, at higher temperatures, the pressure is lower, and at 400C, it is about 100 MPa.

【0031】引き続きホトエッチング法によりAlの領
域23およびWの領域26を、図11のように所望の形
状にパターニングする。Wの領域26が厚すぎる場合は
この領域を除去した後パターニングする。Alの領域内
にある空洞の割合が少ない場合は、パターニングと加圧
工程を前後させ、このようにパターニングした後、圧力
を印加してもよい。
Subsequently, the Al region 23 and the W region 26 are patterned into a desired shape by a photoetching method as shown in FIG. If the W region 26 is too thick, it is patterned after removing this region. When the proportion of the cavities in the Al region is small, the patterning and the pressurizing step may be performed before and after the patterning is performed, and then the pressure may be applied.

【0032】Wの弾性定数はAlの5倍程度で、膜厚が
Alと同程度から10倍程度の範囲では良好な埋め込み
が実現できた。
The elastic constant of W is about 5 times that of Al. Good embedding can be realized when the film thickness is in the range of about 10 times that of Al.

【0033】[0033]

【発明の効果】本発明によれば、高アスペクト比の接続
孔をAl合金もしくは延性に富んだ金属により簡単な処
理で埋め込むことができ、接続孔配線の信頼性向上を実
現することができるので、集積密度の高い各種半導体装
置の実現に極めて有用である。
According to the present invention, a high aspect ratio contact hole can be filled with an Al alloy or a metal rich in ductility by a simple process, and the reliability of the contact hole wiring can be improved. It is extremely useful for realizing various semiconductor devices with high integration density.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 1 is a sectional view showing a wiring forming process according to an embodiment of the present invention.

【図2】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 2 is a cross-sectional view showing a wiring forming process according to an embodiment of the present invention.

【図3】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 3 is a cross-sectional view showing a wiring forming process according to an embodiment of the present invention.

【図4】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 4 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【図5】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 5 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【図6】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 6 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【図7】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 7 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【図8】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 8 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【図9】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 9 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【図10】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 10 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【図11】本発明の一実施例の配線形成工程を示す断面
図。
FIG. 11 is a cross-sectional view showing a wiring forming process of an example of the present invention.

【符号の説明】[Explanation of symbols]

11…シリコン基板、21…多結晶シリコン電極配線、
22…タングステン配線、23…Al−1%Si合金
膜、24…PIQ樹脂層、26…W膜、31,32…層
間絶縁膜、41…接続孔部、51…油圧プレス装置のヘ
ッド。
11 ... Silicon substrate, 21 ... Polycrystalline silicon electrode wiring,
22 ... Tungsten wiring, 23 ... Al-1% Si alloy film, 24 ... PIQ resin layer, 26 ... W film, 31, 32 ... Interlayer insulating film, 41 ... Connection hole part, 51 ... Head of hydraulic press device.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】次の工程を兼ね備えることを特徴とする電
極配線の製造方法。 (a)凹部を形成した基板上に、層状もしくは所定の形
状に加工した金属の領域を形成する工程、(b)前記金
属の領域もしくは前記基板の表面を一様に覆う異種物質
の領域を被着形成もしくは設置する工程、(c)前記基
板面に垂直方向の成分を持つ応力を加え、前記金属の領
域を変形させる工程。
1. A method of manufacturing electrode wiring, which further comprises the following steps. (A) a step of forming a layered or predetermined-shaped metal region on a substrate having a concave portion, and (b) a region of a different substance that uniformly covers the metal region or the surface of the substrate. Forming or installing, (c) applying a stress having a vertical component to the surface of the substrate to deform the metal region.
【請求項2】請求項1において、前記異種物質の弾性率
が金属の弾性率より小さく、前記応力の主成分が前記基
板面に垂直方向の圧縮力である電極配線の製造方法。
2. The method of manufacturing an electrode wiring according to claim 1, wherein the elastic modulus of the different substance is smaller than that of metal, and the main component of the stress is a compressive force in a direction perpendicular to the substrate surface.
【請求項3】請求項1において、前記異種物質の弾性率
が金属の弾性率より大きく、前記応力が等方的圧縮力で
ある電極配線の製造方法。
3. The method of manufacturing an electrode wiring according to claim 1, wherein the elastic modulus of the different substance is larger than that of metal, and the stress is an isotropic compressive force.
【請求項4】請求項1,2または3において、加熱状態
で応力を加え前記金属の領域を変形させる電極配線の製
造方法。
4. The method of manufacturing an electrode wire according to claim 1, wherein stress is applied in a heated state to deform the metal region.
【請求項5】請求項1,2,3または4において、変形
される前記金属の領域がアルミニウム,銅,銀,金,白
金,パラジウム,ニッケルもしくはそれらの合金からな
る電極配線の製造方法。
5. The method for manufacturing an electrode wiring according to claim 1, 2, 3 or 4, wherein the deformed metal region is made of aluminum, copper, silver, gold, platinum, palladium, nickel or an alloy thereof.
【請求項6】請求項1の(a)のみ、もしくは(a)と
(b)の処理を施した基板を搬送して所定の位置に設置
する機構,所定の温度に保ち(c)の処理を施す機構,
減圧後、基板をとりはずす機構を有する基板の処理装
置。
6. A mechanism for transporting a substrate which has been subjected to the treatments of (a) and (a) and (b) and setting it at a predetermined position, and a treatment of (c) at a predetermined temperature. Mechanism for applying
A substrate processing apparatus having a mechanism for removing a substrate after depressurization.
JP18701294A 1994-08-09 1994-08-09 Manufacture of electrode wiring and processing equipment thereof Pending JPH0851152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18701294A JPH0851152A (en) 1994-08-09 1994-08-09 Manufacture of electrode wiring and processing equipment thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18701294A JPH0851152A (en) 1994-08-09 1994-08-09 Manufacture of electrode wiring and processing equipment thereof

Publications (1)

Publication Number Publication Date
JPH0851152A true JPH0851152A (en) 1996-02-20

Family

ID=16198663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18701294A Pending JPH0851152A (en) 1994-08-09 1994-08-09 Manufacture of electrode wiring and processing equipment thereof

Country Status (1)

Country Link
JP (1) JPH0851152A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011519485A (en) * 2008-05-01 2011-07-07 オヴォニクス,インコーポレイテッド Method of forming electrodes in a phase change memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011519485A (en) * 2008-05-01 2011-07-07 オヴォニクス,インコーポレイテッド Method of forming electrodes in a phase change memory device

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