JPH05251441A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form a surface of an insulating film and a surface of wiring in the same plane, to flatten them and to superpose many wiring layers. CONSTITUTION:An insulator 102 is selectively formed on a region except a region to be formed with a wiring metal, and metal 104 is selectively buried in the region to be formed with the wiring metal, thereby completely flattening the surface. Accordingly, many wiring layers can be superposed. Further, since a thickness of a wiring 105 is decided according to the thickness of the insulator 102, it can be arbitrarily decided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for forming a wiring metal body.

[0002]

2. Description of the Related Art Conventionally, for metal wiring of a semiconductor integrated circuit, as shown in FIG. 3A, an insulating film 102 is deposited on one main surface of a semiconductor substrate 101, and then metal is deposited on the entire surface by photolithography. A wiring metal 105 is formed by anisotropic etching, an insulating film 102 is deposited, and a planarizing material 110 such as a coating organic film is applied, as shown in FIG. The insulating film 102 is flattened by an etch-back method in which the insulating film 102 is flattened by etching at the same etching rate, and further progressed to the wiring forming process of the upper layer. Further, as shown in FIG. 3C, there is also a method of applying a coating glass 111 to flatten it instead of the etch back method.

[0003]

In the above-mentioned prior art,
There is a limit to the flattening of the interlayer insulating film, and the thickness of the wiring metal cannot be arbitrarily determined, so that the electric resistance of the metal wiring increases.

The reason will be described below.

When a planarizing material such as a coating organic film is applied, the film thickness thereof depends on the shape of the base. For example, when the flattening material 110 is applied with a thickness a, as shown in FIG. 4A, the flattening material 110 is applied with a thickness a in a wide flat region 112 without wiring, but is thick even in the wide wiring region 113. Since the coating is applied at a, a step difference in the thickness of the wiring 105 remains in the entire semiconductor chip. Further, as shown in FIG. 4B, the thickness of the coating / planarizing material 110 is a even on the wiring regions 114 arranged at narrow intervals, similarly to the wide wiring. If the wiring is a multi-layered wiring of about 2 to 3 layers, this step is not a problem, but if the wiring is a multi-layered wiring, the step becomes large and there is a limit to the multilayering of the wiring.
Further, as is apparent from this, the thickness of the wiring metal is limited due to the balance with the flattening, so that the thickness cannot be arbitrarily determined. It goes without saying that the thinner the wiring, the more advantageous it is for planarization, and the lower the wiring, the thinner the wiring resistance increases.

In order to solve this problem, as shown in FIG. 4 (c), a wide flat region 112 without wiring is formed.
It is also proposed to form a dummy wiring pattern 115 to suppress the step, but in this case, since the dummy wiring pattern 115 is not connected to anywhere, even if carriers are injected, it cannot escape to any other place. This affects wiring and causes malfunction of the semiconductor integrated circuit.

[0007]

SUMMARY OF THE INVENTION The present invention basically comprises a step of selectively forming an insulator in a region excluding a region where a wiring metal body is to be formed in forming a wiring metal body of a semiconductor integrated circuit device. As a specific method for selectively forming an insulator in a region other than the region where the wiring metal body is to be formed, a wiring is formed after forming an insulating film on the entire surface As a specific method of burying the metal in the wiring metal body formation scheduled area, the method includes the step of selectively removing only the metal body formation scheduled area. A specific example in which the metal in a region other than the region where the wiring metal body is to be formed is selectively removed by etching back or polishing, and the metal is formed so as to fill the region where the wiring metal body is to be formed. As a method, but also as a constituent using a plating.

[0008]

First Embodiment As shown in FIG. 1A, an insulating film 102 is formed on one main surface of a semiconductor substrate 101, for example, a normal pressure CV.
After deposition by the D method or the like, photolithography and anisotropic etching selectively remove only the wiring formation planned region. The etching depth at this time becomes the thickness of the wiring.

Next, as shown in FIG. 1B, a metal 104 is deposited so as to fill the etching region 103, and the metal 1 is left so that the metal remains only in the wiring formation planned region.
04 is etched to form the wiring 105 as shown in FIG.

As is apparent from this description, according to the present invention, the surface of the insulating film and the surface of the wiring are the same, and the surfaces are completely flattened, so that wiring layers can be stacked as desired. Furthermore, since the thickness of the wiring is determined by the etching depth,
It can be decided arbitrarily.

[0011]

Second Embodiment of the Invention In the first embodiment, the basic idea of the present invention was explained, but there are some points that cannot be realized by the present technology. For example, aluminum or gold is generally used as a wiring metal of a semiconductor integrated circuit device, but a method of depositing these metals so as to fill the etching region 103 as shown in FIG. 1B is currently experimental. Has been studied but has not been developed to a practical level.

Therefore, an embodiment will be described with a currently available technique.

As in the first embodiment, as shown in FIG. 1A, an insulating film 102 is deposited on one main surface of a semiconductor substrate 101 by, for example, an atmospheric pressure CVD method, followed by photolithography and anisotropy. Only the area where wiring is to be formed is selectively removed by etching. The depth of the etching region 103 at this time becomes the thickness of the wiring.

Next, as shown in FIG. 2A, tungsten 106 is sputtered on the entire surface in a state where the etching region 103 is not buried, and gold 107 is plated with the tungsten 106 as an electrode. Gold plated has good step coverage and can completely fill the etching region 103. Finally, the gold 107 and the tungsten 106 in the region other than the etching region 103 are removed by, for example, aqua regia, and the wiring 105 is formed as shown in FIG. 2B.

[0015]

Third Embodiment of the Invention In the second embodiment, the metal is removed by etch back, but in this case, when the wiring width becomes large, the metal must be deposited thick to fill the wiring formation planned region. Therefore, polishing can be used to avoid it. That is, as in the case of FIG. 2A, after the wiring formation planned region is filled with tungsten 106 and gold 107, the gold 107 and tungsten 106 are removed by polishing, and the wiring 105 is formed as in FIG. 2B. To do. In this type of semiconductor device, the insulating film 102 is usually made of silicon oxide, silicon nitride, or the like, and is harder than metal, so that polishing is stopped on the surface of the insulating film 102 if an abrasive is selected appropriately.
Therefore, if a wide wiring is to be formed by etching back, as shown in FIG. 2C, metal must be deposited at least ½ of this width. As shown in 2 (d), the gold 107 may be deposited by the thickness of the wiring.

[0016]

Fourth Embodiment of the Invention The present invention can of course be combined with, for example, a technique for filling a through hole with a selective CVD metal.

As shown in FIG. 2E, the first wiring 10
After filling the through holes formed on the surface 8 with selective CVD tungsten 109 or the like, an insulating film 102 is deposited to form a second film.
The area where the wiring is to be formed is etched to expose the surface of the embedded tungsten 109. After that, as in the above-mentioned embodiment,
By burying a metal in the wiring formation planned region, a connection portion of the wiring 105 can be formed as shown in FIG.

[0018]

The present invention has the effect of significantly increasing the degree of integration of a semiconductor integrated circuit and the operating speed because wirings of any thickness can be stacked in any number of layers.

In the trial production by the inventors, five layers each having a layer thickness of 1 were formed, but there was no problem in yield and the operating speed was 10
% Improved.

[Brief description of drawings]

FIG. 1 is a sectional view of an apparatus for explaining an embodiment of the present invention.

FIG. 2 is a sectional view of an apparatus for explaining another embodiment of the present invention.

FIG. 3 is a cross-sectional view of a device for explaining a conventional technique and its problems.

FIG. 4 is a cross-sectional view of a device for explaining a conventional technique and its problems.

[Explanation of symbols]

 101 Semiconductor Substrate 102 Insulating Film 103 Etching Area 104 Metal 105 Wiring 106, 109 Tungsten 107 Gold 108 First Wiring 110 Flattening Agent 111 Coating Glass 112 Wide Flat Area 113 Wide Wiring Area 114 Wiring Areas with Narrow Spacing 115 Dummy wiring pattern

Claims (5)

[Claims] 1. When forming a wiring metal body of a semiconductor integrated circuit device, a step of selectively forming an insulator in a region excluding the wiring metal body formation scheduled region, and selectively forming the wiring metal body formation scheduled region in the region. A method of manufacturing a semiconductor integrated circuit device, comprising a step of burying a metal. 2. A method for selectively forming an insulator in a region other than a region where a wiring metal body is to be formed includes a step of forming an insulating film over the entire surface and then selectively removing only the region where a metal wiring body is formed. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein 3. A method of selectively burying a metal in a wiring metal body formation scheduled region is to form the metal in a state of filling the wiring metal body formation scheduled region and then etch back the wiring metal body formation scheduled region by etching back. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the metal in the area to be removed is selectively removed. 4. A method of selectively embedding a metal in a wiring metal body formation planned region is to remove the wiring metal body formation planned region by polishing after forming a metal on the entire surface in a state of filling the wiring metal body formation planned region. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the metal in the region is selectively removed. 5. A method of forming a metal on the entire surface in a state where the wiring metal body formation scheduled region is embedded, wherein a first metal is formed on the entire surface in a state where the wiring metal body formation scheduled region is not embedded, and then the first metal is formed. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the metal is deposited by plating with one electrode.