JPH0850274A - Display device - Google Patents

Abstract

PURPOSE:To provide a display device capable of preventing disturbance of display control signals, disturbance of display images occurring in the abnormality of the voltage supplied to driving means and destruction of driving means. CONSTITUTION:The plural display control signals are supplied from a control circuit 16 via a shut-off circuit 18 to respective driving circuits of a liquid crystal display device 11 in order to drive a liquid crystal display panel 12. This shut-off circuit 18 does not supply the electric power to the respective driving circuits unless the conditions to be predetermined are satisfied. The undesired images are, therefore, not displayed on the liquid crystal display panel 12 and the destruction of the driving circuits by application of excessive burden on the respective driving circuits is prevented even if the abnormality is generated in the display control signals by certain cause. Since the electric power to be supplied to the respective driving circuits is also supplied via the shut-off circuit 18, the destruction of the respective driving circuits is prevented even if the abnormality arises in the voltage to be supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device suitable for use in a liquid crystal display device or the like.

[0002]

2. Description of the Related Art FIG. 13 is a diagram showing a schematic configuration of a general liquid crystal display device 1. The liquid crystal display device 1 includes a liquid crystal display panel 2, a common drive circuit 3, a segment drive circuit 4, a control circuit 5, and a power supply 6.

The liquid crystal display panel 2 is constructed by interposing a liquid crystal layer between a pair of substrate members. Each of the pair of substrate members has a plurality of strip-shaped electrodes that are parallel to each other and are arranged at equal intervals on one surface of a light-transmissive substrate made of glass, plastic, or the like, and substantially the entire one surface on which the strip-shaped electrodes are formed. It is composed of an alignment film for covering. The pair of substrate members are arranged at predetermined intervals so that the longitudinal directions of the strip electrodes of the respective substrate members are orthogonal to each other and the alignment films formed on the respective substrate members are opposed to each other, and The vicinity of the peripheral portion of the member is adhered with an adhesive. A liquid crystal material forming a liquid crystal layer is injected and sealed in a space formed by the pair of substrate members and an adhesive.

The liquid crystal display panel 2 constructed as described above
, Cn (the reference numeral c is used to generically refer to them) as the strip electrodes arranged on one substrate member, and the strip electrodes arranged on the other substrate member are segment electrodes s1, , sm (reference numeral s is used for generic name). Common electrode c
, A predetermined drive signal is applied from the common drive circuit 3, and a predetermined drive signal is applied from the segment drive circuit 4 to the segment electrode s.

In the liquid crystal display panel 2, the liquid crystal material interposed at each intersection of the common electrode c and the segment electrode s is 1.
It becomes a picture element. Therefore, in the liquid crystal display panel 2 shown in FIG. 13, n × m picture elements are arranged in a matrix. An image is displayed by selectively driving this picture element.

The common drive circuit 3 includes a control circuit 5 which will be described later.
Controlled by, the signal of a predetermined potential (hereinafter, referred to as “scanning signal”) is sequentially applied to the common electrode c one by one in a predetermined period (hereinafter, referred to as “one display period”). A period during which the scanning signal is applied to one common electrode c is defined as one horizontal display period.

The segment drive circuit 4 displays the display data D on the segment electrode s for each horizontal display period based on the display data D0 to D7 (reference numeral D is used for generic name) given from the control circuit 5 described later. A potential signal (hereinafter, referred to as “display signal”) based on is applied.

The segment drive circuit 4 has a plurality of shift registers respectively corresponding to the segment electrodes s, and shifts the display data D given in response to the clock signal XCK given from the control circuit 5 while sequentially shifting it. Write to. When all the display data D are written in the shift register, the display signals corresponding to the written display data D are collectively applied to the segment electrodes s. The writing of the display data D is performed within the horizontal display period in which the display signal is applied to the display data D written immediately before the display data D to be written.

The control circuit 5 supplies a plurality of signals for controlling each drive circuit. The control circuit 5 controls the clock signals YD,
LP is supplied to the common drive circuit 3, and display data D and clock signals XCK and LP are supplied to the segment drive circuit 4. The clock signal YD is a clock signal that defines the one display period. The clock signal LP is a clock signal that defines the one horizontal display period. Therefore, the signal LP has n pulses within one display period.
The clock signal XCK is a clock signal that defines the write operation to the shift register included in the segment drive circuit 4 as described above, and has m pulses within one horizontal display period.

Further, the control circuit 5 supplies an inversion control signal M to the common drive circuit 3 and the segment drive circuit 4, respectively. The inversion control signal M is a signal instructing to invert the polarity of the drive voltage applied to each picture element of the liquid crystal display panel 2. Generally, the liquid crystal material used for the liquid crystal display panel 2 is destroyed when a DC voltage is applied for a long time. Therefore, it is necessary to reverse the polarity of the voltage applied to the liquid crystal material, which is a picture element, from the positive polarity to the negative polarity or from the negative polarity to the positive polarity every predetermined period. By supplying the inversion control signal M to each drive circuit, the polarity of the drive voltage applied to the liquid crystal material can be inverted at regular intervals.

The power supply circuit 6 supplies drive voltages to the common drive circuit 3 and the segment drive circuit 4, respectively.

FIG. 14 is a timing chart showing the operation of the liquid crystal display device 1. FIG. 14 particularly shows the operation of the common drive circuit 3. FIG. 14A shows a waveform diagram of the clock signal YD. The clock signal YD is a signal that is at the high level only for the period W1 for each display period W2. FIG. 14 (2) is a waveform diagram of the clock signal LP. The clock signal LP is a clock signal having a period W3, and the period W3 corresponds to one horizontal display period. During the high level period W1 of the clock signal YD, the clock signal L
It is set to be shorter than the period W3 of P, longer than the high level period of the clock signal LP, and becomes high level at the timing including the high level period.

FIG. 14 (3) shows the common electrode c1.
FIG. 14 (4) is a waveform diagram of the scanning signal applied to the common electrode c2, and FIG. 14 (4) is a waveform diagram of the scanning signal applied to the common electrode c2. The common drive circuit 3 latches the high level of the clock signal YD at the time t0 when the clock signal LP falls by the latch circuit corresponding to the common electrode c1,
The high level is maintained until the next falling time t1 of the clock signal LP. While the scanning signal applied to the common electrode c1 is at the high level, the scanning signal having a predetermined potential is applied to the common electrode c1. Similarly, the scanning signal is applied to the common electrode c2 during the period W3 from the time t1. Thereafter, scanning signals are applied line by line to the common electrodes c3 to cn one by one.

In the liquid crystal display device 1 configured and operated as described above, there is a technique for preventing the circuit from being broken due to an abnormal operation caused by the instability of the voltage of the power supplied when the power is turned on. Japanese Patent Fairness 5-2128
No. According to the above-mentioned publication, a switch is provided on the line for supplying the liquid crystal voltage of the drive circuit, and the switch is turned on / off by the logic given by the processing circuit. In addition, the latch circuit that latches the data for selecting the voltage to be applied to the liquid crystal display panel 2 can be reset so that the voltage is not applied when it is not desired.

[0015]

In the liquid crystal display device 1 configured as described above, only the abnormality of the voltage supplied to the drive circuit is monitored, and no countermeasure is taken when the abnormality of the display control signal occurs. Has not been taken, and the measures are insufficient.

15 to 20 are timing charts showing the operation of the liquid crystal display device 1 at the time of abnormality. In each timing chart, signals with the same reference numerals have the same period unless otherwise specified. Further, if the symbols indicating the cycle and the period are the same, they are the same cycle and period.

FIG. 15 is a timing chart when the high level period of the clock signal YD is longer than the proper period. FIG. 15 (1) shows that the period W4 in which the clock signal YD is high level is longer than the proper period W1 and is high level during the period W4 which is, for example, about three times the cycle W3 of the clock signal LP. It is a waveform diagram of the clock signal YD in the case. In the period W4, FIG.
As shown in (2), a plurality of high-level periods of the clock signal LP are included. Therefore, as shown in FIG. 15 (3), the scanning signal is applied to the common electrode c1 during the time t10 to t13, and as shown in FIG. 15 (4), the common electrode c2 is supplied with the time. t11-t14
The scanning signal is applied during the period. Therefore, during the times t11 to t13, the common electrodes c1 and c2 are simultaneously selected.

Therefore, since the display signal from the segment drive circuit 4 is applied to the two common electrodes at the same time,
The displayed image is disturbed, and good display cannot be obtained.
Further, since a plurality of common electrodes are simultaneously selected and a scanning signal is supplied to each common electrode, a relatively large current flows inside the common drive circuit 3, latchup occurs, and the drive circuit may be destroyed. There is a nature.

FIG. 16 is a timing chart when the low level period of the clock signal YD is shorter than the proper period. FIG. 16A shows that a period W5 in which the clock signal YD is at a low level is an appropriate period (period W
2 is a waveform diagram of a clock signal YD when the clock signal YD becomes shorter than (2 minus the period W1) and is, for example, about twice the period W3 of the clock signal LP. Since the low level period W5 of the clock signal YD is short, all the common electrodes c cannot be scanned during one display period. FIG.
As shown in 6 (3), the common electrode c1 has a time t20.
The scanning signal is applied between t21, t22, t22 and t23, and t24 and t25, and as shown in FIG. 16D, the common electrode c2 is time t21 to t22 and t23 to t24.
The scanning signal is applied during the period, and as shown in FIG. 16 (5), the common electrode c3 is subject to the times t22 to t23 and t24 to.
The scanning signal is applied during t25. Therefore, during the time t22 to t23 and t24 to t25, the common electrode c
1, c3 will be selected at the same time.

Therefore, since the display signal from the segment drive circuit 4 is simultaneously applied to the two common electrodes, the displayed image is disturbed and a good display cannot be obtained. In addition, a plurality of common electrodes are simultaneously selected, and in order to supply a scanning signal to each common electrode, the common drive circuit 3
A relatively large current flows inside the, causing latch-up,
The drive circuit may be destroyed.

FIG. 17 is a timing chart when the cycle of the clock signal LP is shorter than the cycle W3. FIG. 17 (1) shows that the clock signal LP has a shorter cycle W3, for example, a cycle W6 that is shorter than the cycle of the clock signal that defines the operating speed of the common drive circuit 3. It is a wave form diagram of LP. Since the sufficient time for operation cannot be taken, the common drive circuit 3 cannot operate properly. Therefore, the selection signal for the common electrode is not selected for a certain period of time, and a DC voltage is applied to the panel, which may damage the liquid crystal material.

FIG. 18 is a timing chart when the clock signal LP is interrupted on the way. FIG.
8 (1) is a waveform diagram of the clock signal LP in which the high-level period does not appear after the time ti (1 ≦ i ≦ n−1). As shown in FIG. 18C, the common electrode ci + 1 selected at the time ti remains selected after the time ti. Therefore, a direct current component is applied to the panel, which may damage the liquid crystal material.

FIG. 19 is a timing chart when the display permission signal DI becomes high level earlier than the logic power supply VDD. After the power is turned on, the display permission signal DI becomes high level if there is no abnormality in the clock signal to permit the power supply to each drive circuit, and becomes low level when the abnormality occurs to cut off the power supply. The display permission signal DI shown in FIG. 19 (1) becomes high level at time t30, and the logic power supply VDD shown in FIG. 19 (2) becomes high level at time t31. Since the display permission signal DI becomes the high level before the logic power supply VDD becomes the high level, the voltage of the display permission signal DI becomes the liquid crystal display device 1.
Through the circuit inside, the source of the logic power VDD is reached. Therefore, other circuits may malfunction and the liquid crystal display panel 2 may be damaged.

FIG. 20 is a timing chart in the case where the display permission signal DI becomes high level earlier than the liquid crystal power supply VEE. Display permission signal DI shown in FIG. 20 (1)
Becomes high level at time t40, and the liquid crystal power supply VEE shown in FIG. 20 (2) becomes high level at time t41.
When the display permission signal DI becomes the high level before the liquid crystal power supply VEE becomes the high level, the operation is started by the display permission signal DI even though the withstand voltage circuit in the drive circuit is not powered. Then, a load is applied to the drive circuit to turn on the liquid crystal power supply VEE,
The drive circuit may be damaged.

The above-mentioned abnormality occurs under various situations. For example, it occurs when the control circuit 5 enters a transient state and is not stable when the power is turned on and when a plurality of display modes included in the liquid crystal display device are switched. When designing equipment that incorporates a liquid crystal display,
It occurs when designing without considering the signal sequence when the power is turned on. Further, in the production process of the liquid crystal display device, the signal line of the clock signal YD is short-circuited with other signal lines due to defective soldering or the like. Furthermore, when the liquid crystal display device is incorporated in a device such as a personal computer, it also occurs when the signal line of the clock signal YD comes into contact with the signal line of another circuit board.

It is an object of the present invention to disturb display control signals,
It is an object of the present invention to provide a display device capable of preventing a display image from being disturbed due to an abnormality in a voltage supplied to a drive unit and destroying the drive unit.

[0027]

The present invention comprises display means and
Drive means for driving the display means, and the drive means,
The control means for supplying a display control signal and electric power necessary for driving the display, the first detecting means for detecting that the cycle of the display control signal is a normal value, and the voltage of the supplied electric power are:
Second detection means for detecting that the voltage is equal to or higher than a predetermined level, and the voltage of the electric power supplied is lower than or equal to the predetermined level in response to the outputs of the first detection means and the second detection means. And a means for cutting off the supply of electric power to the drive means when at least one of the fact that the cycle of the display control signal is out of the range of a predetermined value is generated. It is a display device.

[0028]

According to the present invention, the display means such as a liquid crystal display panel is driven by the drive means to display an image.
The drive means is supplied with a control signal and electric power required for display drive from the control means. Here, the first detection means detects that the cycle of the display control signal is a normal value,
The second detection means detects that the voltage of the supplied power is equal to or higher than a predetermined level. It is detected that at least one of the fact that the signal cycle is out of the range of the predetermined value and the voltage of the supplied power is equal to or less than the predetermined voltage is generated by each of the detecting means. Then, the power supply to the driving means is cut off. Therefore, when the cycle of the display control signal becomes abnormal, or when the supplied voltage is equal to or lower than the predetermined voltage, the power supply to the driving unit is cut off, and an undesired image is generated due to the abnormality of the display control signal. It is not displayed on the display means, and the drive means is not destroyed by the supply of an abnormal level voltage. Since all of these operations can be performed in the display device, it is not necessary to input a control signal from the outside.

[0029]

FIG. 1 is a diagram showing a schematic structure of a liquid crystal display device 11 which is an embodiment of the present invention. Liquid crystal display device 1
1 is a liquid crystal display panel 12, a common drive circuit 13,
The first segment drive circuit 14, the second segment drive circuit 15, a control circuit 16, a power supply circuit 17, and a cutoff circuit 18 are included.

The liquid crystal display panel 12 is constructed by interposing a liquid crystal layer between a pair of substrate members. The pair of substrate members are
Each of the translucent substrates made of glass, plastic, etc. is composed of a plurality of strip-shaped electrodes that are parallel to each other and arranged at equal intervals on one surface of the substrate, and an alignment film that covers almost the entire surface of the one surface where the strip-shaped electrodes are formed. It In the present embodiment, the strip electrode formed on the one substrate member is divided at an intermediate position of the length in the longitudinal direction. Of the two divided electrode groups, one electrode group is the first segment electrode group and the other electrode group is the second segment electrode group. The first segment electrode group includes the first segment electrodes us1 and us
, ..., us 640 (the reference numeral us is used when collectively referred to), and the second segment electrode group is
, Ds640 (the reference numeral ds is used when collectively referred to).
Further, the strip electrodes formed on the other substrate member are replaced by the common electrodes c1, c2. ..., c480 (reference numeral c is used for generic name).

In the liquid crystal display panel 12, the liquid crystal material interposed at each intersection of the first segment electrode us, the second segment electrode ds and the common electrode c constitutes one picture element. Therefore, in the picture element display panel 12 shown in FIG. 1, 640 × 480 picture elements are arranged in a matrix. An image is displayed by selectively driving this picture element.

The common drive circuit 13 is controlled by a control circuit 16 which will be described later, and sequentially applies a predetermined scanning signal to the common electrode c one by one in one display period. 1
The period during which the scanning signal is applied to the common electrode c of the book is
It becomes one horizontal display period.

The common drive circuit 13 includes a first common drive circuit 19 and a second common drive circuit 20. The first common drive circuit 19 applies a scanning signal line by line to the common electrodes c1 to c240 one by one. Further, the second common drive circuit 20 applies the scanning signal line by line to the common electrodes c241 to c480 one by one. The first common drive circuit 19 and the second common drive circuit 20 operate simultaneously within one display period and at the same timing. Therefore, in one horizontal display period, two scanning signals are simultaneously applied to the upper common electrode and the lower common electrode, for example, the common electrodes c1 and c241 and the common electrodes c2 and c242. In this way, the electrodes are divided into the upper portion and the lower portion of the liquid crystal display panel 12, and the two electrode groups are simultaneously scanned, so that one horizontal display period can be set to 2 as compared with the case where the electrodes are not divided.
The length can be doubled, and the picture element can be driven well.

The first common drive circuit 19 is the drive circuit 2
1 and 22 are included. The drive circuit 21 has common electrodes c1 to c1.
20 is in charge of scanning, the drive circuit 22 is the common electrode c12
Responsible for scanning 1 to c240. Second common drive circuit 2
0 includes drive circuits 23 and 24. The drive circuit 23 is in charge of scanning the common electrodes c241 to c360,
Reference numeral 4 is in charge of scanning the common electrodes c361 to c480.

The first segment drive circuit 14 has display data UD0 to UD7 supplied from a control circuit 16 described later.
1st segment electrode us for every 1 horizontal display period based on
A signal voltage corresponding to the display data is applied to. The second segment drive circuit 15 applies a signal voltage corresponding to the display data to the second segment electrode ds for each horizontal display period based on display data LD0 to LD7 provided from the control circuit 16 described later. First segment drive circuit 14
And the second segment drive circuit 15 operates simultaneously and at the same timing. Therefore, for example, in one horizontal display period in which the common electrodes c1 and c241 are operating,
The picture element at the intersection of the common electrode c1 and the first segment electrode us is driven, and the picture element at the intersection of the common electrode c241 and the second segment electrode ds is driven.

The control circuit 16 supplies a plurality of signals for controlling each circuit. The plurality of signals supplied from the control circuit 16 include display data UD0 to UD7 and LD0 to LD.
7, clock signals XCK, LP, YD, and a polarity inversion signal M described later. The display data UD0 to UD7 are
It is provided to the first segment drive circuit 14. The display data LD0 to LD7 are given to the second segment drive circuit 15. The clock signal XCK is given to the first segment drive circuit 14 and the second segment drive circuit 15, respectively. The clock signals LP and YD are supplied to the cutoff circuit 1 described later.
It is given to each drive circuit via 8. Clock signal LP
Are applied to the first segment drive circuit 14, the second segment drive circuit 15, and the common drive circuit 13, respectively, and the clock signal YD is applied to the common drive circuit 13.

The power supply circuit 17 generates a plurality of types of voltages from the reference voltage by the configuration described later, and the common drive circuit 1
3, the first segment drive circuit 14 and the second segment drive circuit 15, respectively.

The cutoff circuit 18 detects an abnormality in the clock signals YD and LP and the power supply voltage supplied to each drive circuit by the configuration described later, and sets the display permission signal DI to low level and outputs it to each drive circuit. The display permission signal DI is a signal for controlling the voltage applied to the liquid crystal panel 12, and becomes low level when the cutoff circuit 18 detects the abnormality,
The selector will be described later so that the voltage is not applied. To display it, set it to high level in advance.

FIG. 2 is a circuit diagram showing a configuration example of the cutoff circuit 18. The cutoff circuit 18 includes flip-flops 25 and 2
6, 27, 71, inverters 28, 29, 59, A
ND gates 67 and 68, counters 56 and 57, and voltage monitoring ICs (Integrated Circuits) 65 and 66
And a monostable multivibrator 69, 70. The cutoff circuit 18 receives the input clock signal L
When there is an abnormality in P, YD and the power supplies VDD, VEE, the display permission signal DI which is an output is set to low level.
With respect to the clock signal YD, the case where the signal is abnormal includes the case where the period during which the clock signal YD is at the high level is longer than the normal time and the case where the cycle of the clock signal YD is shorter than the normal time. Regarding the clock signal LP, there are a case where the cycle of the clock signal LP is longer than a normal time and a case where the cycle of the clock signal LP is shorter than a normal time. Furthermore, regarding the voltage level of the power supply, the logic power supply VDD
If the voltage level of is lower than normal, and the liquid crystal power supply VEE
When the voltage level of is lower than the normal level.

The clock signal YD is input to the D input of the flip-flop 25, and the clock signal LP inverted by the inverter 28 is input as a clock pulse. The clock signal YD inverted by the inverter 29 is input as an inverted reset pulse. Signal SA that is the Q output of flip-flop 25
Is applied to the D input of the flip-flop 26. The flip-flop 25 latches the signal level of the clock signal YD supplied to the D input at the falling timing of the clock signal LP and outputs it as the Q output, and is reset at the falling timing of the clock signal YD.

The signal SA, which is the Q output of the flip-flop 25, is input to the D input of the flip-flop 26,
As the clock pulse and the inversion reset pulse, signals similar to those of the flip-flop 25 are input.
The signal SB, which is the inverted Q output of the flip-flop 26, is
It is input to the AND gate 68. Flip-flop 26
Latches the level of the signal SA, which is the Q output of the flip-flop 25, at the falling timing of the clock signal LP, outputs the level of the signal SA as the inverted Q output, and is reset at the falling timing of the clock signal YD. .

The signal SC is input to the inverting load input of the counter 56. The signal SC is the output of the AND gate 67 to which the signal VEEOK output from the voltage monitoring IC 65 described later, the signal VDDOK output from the voltage monitoring IC 66 described below, and the clock signal YD inverted by the inverter 29 are input. is there. A clock signal LP inverted by the inverter 28 is input as a clock pulse of the counter 56, and a signal having a constant potential is input to the inversion clear terminal CL. A signal SD obtained by inverting a CA output of a counter 57, which will be described later, by an inverter 59 is input to the EP input, and a signal having a constant potential is input to the ET input. Moreover, the preset input of data is not performed. The CA output of the counter 56 is the counter 57
Is input to the ET input of.

The inverted load input of the counter 57, the clock pulse, and the signal SD input to the EP input are the same as the signals input to the counter 56, and the inversion clear terminal CL is also a constant potential. Signal is being input. The CA output of the counter 56 is input to the ET input. In the counter 57, a signal having a constant potential is input to the preset A input. One of the CA outputs of the counter 57 is input to the D input of the flip-flop 27 described later, and the other is input to the inverter 59 to output the signal SD.
become.

The counters 56 and 57 are connected in series, each load a predetermined set value when the signal SC falls, and perform a counting operation at each fall of the clock signal LP. Since the set value in this embodiment is "10h (hexadecimal number)", the initial value of the counter 57 is "1h" and the initial value of the counter 56 is "0h".

Since the ET input is always at the high level, the counter 56 performs the counting operation every time the CK input is input. The counter 56 sets the CA output, which is the ET input of the counter 57, to the high level when the count value reaches “Fh”. The CA output is at high level when the count value of the counter is "Fh", and is at low level otherwise. Since the ET input is at the high level, the counter 57 performs the counting operation at the falling timing of the clock signal LP to be input next, and the count value increases by 1 from the initial value to become “2h”. At the same time, the count value of the counter 56 becomes "0h", and the CA output also becomes low level. Since the CA output becomes low level, the counter 57 does not perform the counting operation at the trailing edge of the clock signal LP input next. When the clock signal LP falls 239 times between the fall of the clock signal YD and the rise of the clock signal YD again, the count values of the counters 56 and 57 both become “Fh” and the CA output of the counter 57 goes high. Become a level. The signal LCYDL which is one CA output of the counter 57 is
It is input to the D input of the flip-flop 27. The other CA output is inverted by the inverter 59 and the signal S
It is input to the EP input of each counter as D. When the signal input to the EP input is low level, each counter does not perform counting operation. The same operation is performed for each cycle of the clock signal YD.

The voltage monitoring ICs 65 and 66 monitor the voltage levels of the power supplies VEE and VDD, respectively, and when the voltage levels exceed a certain level, their outputs become high. The signal VEEOK which is the output of the voltage monitoring IC 65 and the signal VDDOK which is the output of the voltage monitoring IC 66 are logically ANDed by the AND gate 67 including the inverted clock signal YD, and the signals SC of the counters 56 and 57 are obtained. Input to inverted load input. The signal VEEOK and the signal VDDOK are input to the AND gate 68. Further signal VDD
OK is an output of the cutoff circuit 18.

A clock signal LP is input to the A input of the monostable multivibrator 69, and a signal of a constant potential is input to the B input. A signal having a constant potential is input to the inverting reset input. The Q output of the monostable multivibrator 69 is A as the signal LPDOMAX.
It is input to the ND gate 68. The width of the pulse output from the monostable multivibrator 69 is determined by the pulse width setting unit 7
Determined by 2.

A clock signal LP is input to the A input of the monostable multivibrator 70, and a signal of a constant potential is input to the B input. The clock signal LP is input to the inverting reset input. The Q output of the monostable multivibrator 70 is input to the D input of the flip-flop 71 as the signal LPOSMIN. The width of the pulse output from the monostable multivibrator 70 is set by the pulse width setting unit 73. Flip-flop 71
The signal LPOSMIN is input to the D input of, and the clock signal LP is input as a clock pulse. Further, the signal LP which is the inverted Q output of the flip-flop 71
DUMIN is input to the AND gate 68.

The pulse width setting units 72 and 73 are composed of resistors and capacitors and determine the output pulse width of the monostable multivibrators 69 and 70. The output pulse widths determined by the pulse width setting units 72 and 73 are different.

Five signals are input to the AND gate 68, which are ANDed and input to the inverting reset input of the flip-flop 27 as the inverted signal DSPRST. AN
The D gate 68 has a signal VDDOK, a signal VEEOK,
Signal SB, signal LPDOMAX, and signal LPDUM
Five IN signals are input.

The signal LCYDL is input to the D input of the flip-flop 27, and the clock signal YD is input as a clock pulse. Also, flip-flop 2
The inverted signal DSPRST is input as the inverted reset input of 7. The Q output of the flip-flop 27 is supplied to each drive circuit as the display permission signal DI.

FIG. 3 is a circuit diagram showing a configuration example of the drive circuit 21 which constitutes the common drive circuit 13. Drive circuit 21
24 to 24 have the same configuration, the drive circuit 2 is used here.
1 will be described as an example. The drive circuit 21 includes 120 flip-flops F1 to F120, 120 selectors E1 to E120, and an inverter 30. In the drive circuit 21, one flip-flop and one selector correspond to one common electrode.

The clock signal YD is input to the D input of the flip-flop F1, and the inverted clock signal LP which is the output of the inverter 30 is input as a clock pulse. The Q output of the flip-flop F1 is the selector E
1 and the next stage flip-flop F2
Input to the D input of. The flip-flop F1 latches the level of the clock signal YD at the falling timing of the clock signal LP and outputs the latched level as a Q output.

Flip-flop Fi (i = 2-120)
, The Q output of the previous flip-flop Fi-1 is input to the D input, and the inverted clock signal LP that is the output of the inverter 30 is input as a clock pulse. The Q output of the flip-flop Fi is input to the selector Ei and also to the D input of the next-stage flip-flop Fi + 1. The Q of the flip-flop F120
The output is input only to the selector E120. The flip-flop Fi is the Q of the previous flip-flop Fi-1.
The output level is latched at the falling timing of the clock signal LP, and the latched level is output as the Q output.

The selector Ei (i = 1 to 120) has voltage signals V0, V1, which are input from the power supply circuit 17, which will be described later, according to the levels of the Q output of the flip-flop Fi, the polarity inversion signal M, and the display permission signal DI. Any one of V4 and V5 is selected and used as a scanning signal for the common electrode ci.
Output to.

FIG. 4 is a circuit diagram showing a configuration example of the power supply circuit 17. The power supply circuit 17 includes six resistors R1 to R6 and 5
The amplifiers 31 to 35 are included. These resistors R1 to R6
Are connected in series in this order. The reference voltage VEE is applied to the end opposite to the connection side of the resistor R1, and the end opposite to the connection side of the resistor R6 is set to the ground potential. Resistance R
The ratio of the resistance values of 2 to R6 is R2: R3: R4: R5:
R6 = 1: 1: a: 1: 1 is selected. Power supply circuit 17
Outputs a plurality of different voltages obtained by resistance-dividing the reference voltage VEE by resistors R1 to R6 as drive voltages V0 to V5.

The voltage at the connection point between the resistors R1 and R2 is made into a low impedance by the amplifier 31, and the drive voltage V0 is set.
Is output as The voltage at the connection point between the resistors R2 and R3 is converted into low impedance by the amplifier 32 and output as the driving voltage V1. The voltage at the connection point between the resistors R3 and R4 is converted into low impedance by the amplifier 33 and output as the driving voltage V2. The voltage at the connection point between the resistors R4 and R5 is converted into low impedance by the amplifier 34 and output as the driving voltage V3. The voltage at the connection point between the resistors R5 and R6 is converted into low impedance by the amplifier 35 and output as the driving voltage V4. The ground potential is output as the driving voltage V5.

FIG. 5 shows the selector E provided in the drive circuit 21.
It is a circuit diagram which shows the structural example of 1. Selectors E1 to E12
Since 0 has the same structure, the selector E1 will be described as an example. The selector E1 has four switching elements 3
6 to 39 and a logic circuit 40. The switching elements 36 to 39 are realized by transistors or the like, and conduction / cutoff is controlled by control signals G1 to G4 from the logic circuit 40. Driving voltages V0, V1, V4 and V5 are applied to the respective one ends of the switching elements 36 to 39, and the other ends thereof are commonly connected. Therefore, the selector E1 controls the conduction / interruption of the switching elements 36 to 39 as appropriate so that the driving voltages V0, V1,
One of V4 and V5 can be selected and output.

The logic circuit 40 performs a logical operation on the basis of the Q output of the flip-flop F1, the polarity inversion signal M, and the display permission signal DI to generate the control signals G1 to G4, and the respective gates of the switching elements 36 to 39. Output to the terminal.
A truth table for the logic circuit 40 is shown in Table 1 below.

[0060]

[Table 1]

FIG. 6 is a block diagram showing a configuration example of the control circuit 16. The original oscillation circuit 41 generates a clock signal having a predetermined frequency and supplies it to the frequency dividing circuit 42. The frequency divider circuit 42 divides the supplied clock signal by a predetermined frequency division ratio and outputs it. The output signal of the frequency dividing circuit 42 is given to the mask circuit 43 and the frequency dividing circuit 44. The mask circuit 43 outputs the output signal of the frequency dividing circuit 42 as it is for one predetermined horizontal display period, and interrupts it for a predetermined retrace period to generate and output the clock signal XCK. The frequency dividing circuit 44 divides the output signal of the frequency dividing circuit 42 by a predetermined frequency dividing ratio and outputs the divided signal.

The output signal of the frequency dividing circuit 44 is the counter 4
5, applied to the frequency dividing circuit 46 and the counter 47. The counter 45 counts the number of pulses of the output signal of the frequency dividing circuit 44, and outputs a pulse each time a predetermined count value is reached, thereby generating the clock signal LP. The frequency dividing circuit 46 divides the output signal of the frequency dividing circuit 44 by a predetermined frequency dividing ratio to generate a clock signal YD. Counter 47
Counts the number of pulses of the output signal of the frequency dividing circuit 44, and outputs a pulse each time a predetermined count value is reached,
The polarity inversion signal M is generated.

A CPU (Central Processing Unit) 48 controls the operations of the circuits 41 to 47 described above. The CPU 48 controls the video signal generation circuit 50,
The display data UD0 to UD7 and LD0 to LD7 are output.

FIG. 7 is a circuit diagram showing a configuration example of the first segment drive circuit 14. Since the first and second segment drive circuits 14 and 15 have the same configuration, the first segment drive circuit 14 will be described as an example here. The first segment drive circuit 14 includes latch circuits H1 to H64.
0, L1 to L640 and flip-flops J1 to J64
0, selectors K1 to K640, and inverters 51 and 5
Including 2 and. In the drawing, the segment electrodes us1,
Only the configuration related to us2 is shown.

The flip-flop J1 receives a predetermined level at the D input, latches the D input level at the rising timing of the output of the inverter 52, that is, the falling timing of the clock signal XCK, and outputs the latched level as the Q output. Output as. The Q output of the flip-flop J1 is input as the clock pulse of the latch circuit H1,
It is also input to the D input of the flip-flop J2. Therefore, the latch circuit H1 receives the first clock signal XC.
When K is input, the display data input to the D input is latched and output as the Q output.

Like the flip-flop J1, the flip-flop J2 latches the Q output level of the flip-flop J1 at the falling timing of the clock signal XCK and outputs it as the Q output. Flip flop J2
Q output is input to the CK input of the latch circuit H2 and the D input of the flip-flop J3 (not shown). Regarding the flip-flop J2, when the first clock signal XCK is input, the Q output of the flip-flop J1 is low level, but when the next clock signal XCK is input, the Q output of the flip-flop J1 is high. Since it is the level, the Q output of the flip-flop J2 also becomes the high level. In this way, the flip-flops J1, J2, ...
The Q outputs of the above sequentially become high level every time the clock signal XCK falls.

The Q outputs of the flip-flops J1, J2, ... Are input as clock pulses to the latch circuits H1, H2 ,. Therefore, the display data U
By inputting D0 to UD7 in synchronization with the timing of the clock signal XCK, the latch circuits H1, H2, ...
Latches the input display data in order. The Q outputs of the latch circuits H1, H2, ... Are given to the D inputs of the latch circuits L1, L2 ,.

The latch circuits L1, L2, ... Latch the display data input to the D input at the rising timing of the output signal from the inverter 51, that is, at the falling timing of the clock signal LP, and output it as the Q output. Output. Therefore, in one horizontal display period, the display data to be displayed in the next horizontal display period are sequentially output to the latch circuit H.
1, H2, ... Is written (latched), and when all the writing is completed, the clock signal LP is applied so that the written display data are simultaneously selected by the selectors K1, K2.
2, ...

The selector K1 performs a logical operation based on the Q output of the latch circuit I1, the polarity inversion signal M, and the display permission signal DI, and based on the logical operation result, the drive voltage V0,
One of V2, V3 and V5 is selected and output to the segment electrode us1. For selector K2, ...
It is similar to the selector K1. The configuration of the selectors K1, K2, ... Is the same as the configuration of the selector shown in FIG. The difference is that a driving voltage V2 is applied instead of the driving voltage V1, and a driving voltage V3 is applied instead of the driving voltage V4.
Is given. A truth table of the logical operation of the selector K is shown in Table 2 below.

[0070]

[Table 2]

In the cutoff circuit 18, the operation of each component making the same judgment is shown by a timing chart.
Signals not shown in the timing chart are assumed to be normal.

FIG. 8 is a timing chart showing the operation of the flip-flops 25 and 26. In the timing chart shown in FIG. 8, when the high level period of the clock signal YD is longer than the normal period, the display permission signal DI is set to low level.

In FIG. 8, it is assumed that the periods W1 to W4 have the same length as in FIGS. 14 and 15 described above. At time t50, as shown in FIG. 8 (1), when the clock signal YD rises to the high level, the display permission signal DI which is the Q output of the flip-flop 27 becomes the high level. FIG.
At the falling time t51 of the clock signal LP shown in (2), the flip-flop 25 latches the level of the clock signal YD, and the signal SA which is the Q output becomes high level as shown in FIG. 8 (3). When the clock signal YD is normal, the time t is indicated by a chain double-dashed line in the drawing.
Since it falls to the low level between 51 and t52, the signal S
Since A also becomes low level and the signal SB which is the inverted Q output of the flip-flop 26 shown in FIG. 8 (4) also remains at high level, the flip-flop 27 is not reset and the display permission signal DI remains at high level. Is.

Next, the operation when the clock signal YD is in an abnormal state, that is, when the high level period of the clock signal YD is longer than the normal period as shown in FIG. 8A, will be described. In this case, since the clock signal YD is at the high level at the next falling time t52 of the clock signal LP, the signal SA which is the Q output of the flip-flop 25 remains at the high level. Therefore, the flip-flop 26 receives the signal SA at the time t52.
Of the signal Q, which is the inverted Q output, falls to the low level, and AN
The inverted signal DSPRST which is the output of the D gate 68 falls to the low level. Therefore, the flip-flop 27 is reset, and the display permission signal DI which is the Q output becomes low level. After that, at time t53 when the clock signal YD falls to the low level, the flip-flops 25, 2
Both 6 are reset, the signal SA falls to the low level, and the signal SB rises to the high level.

FIG. 9 is a timing chart showing the operation of the counters 56 and 57. In the timing chart shown in FIG. 9, when the clock signal LP rises a predetermined number of times during the period W2 of the clock signal YD, the display permission signal DI is set to the high level.

In FIG. 9, it is assumed that the periods W1 to W3 have the same length as that in FIG. 9 at time t60
As shown in (1), the signals VEEOK and VDDOK have risen to the high level. When the clock signal YD shown in FIG. 9 (2) rises to the high level at time t62,
The signal SC becomes low level. The inverted load inputs of the counters 56 and 57 become high level, and the counters 56 and 57
Reads a predetermined value. When the clock signal YD falls to the low level at time t63, the counters 56 and 57 start counting operations, respectively. Figure 9
Each time the clock signal LP shown in (3) falls at the period W3 from the time t64, the counters 56 and 57 perform the counting operation, respectively. At time t65, the number of falling times (count value) from time t64 becomes “239”, and the counter 57
The signal LCYDL shown in FIG. 9 (4), which is the CA output of, becomes high level. When the clock signal YD rises at time t66, since the signal LCYDL is at high level, the display permission signal DI, which is the Q output of the flip-flop 27, becomes at high level. The signal LCYDL becomes low level when the clock signal LP falls at time t67.

FIG. 10 is a timing chart showing the operation of the monostable multivibrator 69. In the timing chart shown in FIG. 10, the display permission signal DI is set to the low level when the cycle of the clock signal LP becomes longer than the period W3.

In FIG. 10, it is assumed that the clock signal LP is in a normal state before time t70. When the clock signal LP rises to the high level at time t70, the monostable multivibrator 69 operates during the period W7 from time t71 to time t72 determined by the pulse width setting unit 72.
The signal LPDOMAX indicated by 0 (2) is set to the high level. As a result, the inverted reset pulse input to the flip-flop 27 becomes high level, and the display permission signal DI shown in FIG. 10C remains at high level. Period W
7 is set longer than W3, and signal LPDOMAX
When the clock signal LP rises to the high level at time t71 when is high level, the signal LPDOMAX further becomes the high level for the period W7 from the time t71.
When clock signal LP is in an abnormal state, that is, when clock signal LP does not rise to the high level after time t71, signal LPDOMAX falls to the low level at time t72. As a result, the display permission signal DI becomes low level.

FIG. 11 is a timing chart showing the operations of the monostable multivibrator 70 and the flip-flop 71. In the timing chart shown in FIG. 11, when the cycle of the clock signal LP becomes shorter than the period W3, the display permission signal DI is set to low level. In FIG. 11, it is assumed that the clock signal LP is in a normal state before time t80.

At time t80, when the clock signal LP shown in FIG. 11 (1) rises and goes to a high level, the monostable multivibrator 70 has the pulse width setting section 73 set to the period W8 shown in FIG. The signal LPOSMIN shown in () is set to a high level. Signal LPOSM
During the period W8 when IN is at the high level, the clock signal LP
It is set shorter than the period W3 which is one cycle. Therefore, when the clock signal LP rises to the high level at time t82, the signal LPOSMIN is at the low level, so that the signal LPDUMIN which is the inverted Q output of the flip-flop 71 becomes at the high level. Therefore, the flip-flop 27 is not reset, and the display permission signal DI becomes high level.

Next, when the clock signal LP is in an abnormal state, that is, when the clock signal LP becomes high level in a period shorter than the period W3 of the normal state of the clock signal LP or the period W8 in which the signal LPOSMIN is high level. Will be explained. At time t82, the clock signal L
Since P rises to a high level, the signal LPOSM
IN also goes high. Next, at time t83 when the clock signal LP becomes high level, the signal LPOSMIN remains high level, so the signal LPDUMIN which is the inverted Q output of the flip-flop 71 falls and becomes low level. Therefore, the flip-flop 27 is reset and the display permission signal DI becomes low level.

FIG. 12 is a circuit diagram for explaining the second embodiment of the present invention. In this embodiment, the common drive circuit 1
It is assumed that the third segment drive circuit 14, the second segment drive circuit 15, and the second segment drive circuit 15 have no input terminal for the display permission signal DI. In such a case, FIG.
The power supply circuit 61 as shown in FIG. Power circuit 6
1 includes transistors 62 and 63, a plurality of resistors R7 to R10, and the cutoff circuit 18 shown in the first embodiment, in addition to the components of the power supply circuit 17 described above. The supply of the reference voltage VEE from the constant voltage generation circuit 64 is controlled according to the ON / OFF of the display permission signal DI.

In the power supply circuit 61, the constant voltage generation circuit 6
The reference voltage VEE from 4 is given to one end of the resistor R1 via the transistor 62. Transistor 62
A resistor R7 is connected between the emitter and the base of the. The base of the transistor 62 is connected to the emitter of the transistor 63 via the resistor R8. Transistor 63
Is connected to the ground potential GND. The transistor 63 is connected to the base of the cutoff circuit 1 via the resistor R9.
The display permission signal DI from 8 is applied, and the resistor R10 is connected between the base and the collector.

When the display permission signal DI is at high level, the transistor 63 becomes conductive and collector current flows,
As a result, the transistor 62 becomes conductive and the reference voltage VEE is supplied to the resistor R1. When the display permission signal DI is low level, the transistor 63 is cut off and the collector current does not flow. Therefore, the transistor 62 is also cut off and the supply of the reference voltage VEE to the resistor R1 is cut off.
Also in this embodiment, the same effect as that of the above-mentioned embodiment can be obtained.

[0085]

As described above, according to the present invention, at least one of the detection of an abnormality in the display control signal and the voltage of the power supplied to the driving means being below a predetermined level. When this occurs, the power supply to the driving means is forcibly cut off, so that an undesired image is not displayed based on the abnormal display control signal. In addition, it is possible to prevent an undesired operation of the driving unit based on an abnormal display control signal. further,
It is possible to prevent the driving unit from being destroyed by supplying unstable power at an undesired timing.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a liquid crystal display device 11 that is a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a cutoff circuit 18.

FIG. 3 is a circuit diagram showing a configuration example of a drive circuit 21 forming a common drive circuit 13.

FIG. 4 is a circuit diagram showing a configuration example of a power supply circuit 17.

5 is a circuit diagram showing a configuration example of a selector E1 included in the drive circuit 21. FIG.

FIG. 6 is a circuit diagram showing a configuration example of a control circuit 16.

FIG. 7 is a circuit diagram showing a configuration example of a first segment drive circuit 14.

FIG. 8 shows a flip-flop 2 included in the cutoff circuit 18.
It is a timing chart which shows operation of 5 and 26.

9 is a timing chart showing the operation of counters 56 and 57 included in the cutoff circuit 18. FIG.

FIG. 10 is a timing chart showing an operation of the monostable multivibrator 69 included in the cutoff circuit 18.

11 is a timing chart showing the operation of the monostable multivibrator 70 and the flip-flop 71 included in the cutoff circuit 18. FIG.

FIG. 12 is a power supply circuit 6 used in the second embodiment of the present invention.
It is a circuit diagram which shows the structural example of 1.

FIG. 13 is a diagram showing a schematic configuration of a general liquid crystal display device 1.

FIG. 14 is a timing chart showing the operation of the liquid crystal display device 1.

FIG. 15 is a timing chart when the high level period of the clock signal YD is longer than normal.

FIG. 16 is a timing chart when the low level period of the clock signal YD is shorter than normal.

FIG. 17 is a timing chart when the cycle W3 of the clock signal LP is shortened.

FIG. 18 is a timing chart when the clock signal LP is interrupted.

FIG. 19 is a timing chart when the display permission signal DI becomes high level earlier than the logic power supply VDD.

FIG. 20 is a timing chart when the display permission signal DI becomes a high level earlier than the liquid crystal power supply VEE.

[Explanation of symbols]

 11 liquid crystal display device 12 liquid crystal display panel 13 common drive circuit 14 first segment drive circuit 15 second segment drive circuit 16 control circuit 17 power supply circuit 18 cutoff circuit 25, 26, 27, 71 flip-flop 28, 29, 59 inverter 56, 57 counter 65,66 voltage monitoring IC 67,68 AND gate 69,70 monostable multivibrator

Claims (1)

[Claims] 1. A display unit, a drive unit for driving the display unit, a control unit for supplying the display unit with a display control signal and electric power required for display drive, and a cycle of the display control signal is normal. Detecting means for detecting that the voltage of the supplied power is higher than or equal to a predetermined level, the first detecting means and the second detecting means In response to the output of, at least one of the voltage of the supplied power being below a predetermined level and the period of the display control signal being out of the range of the predetermined value, And a means for cutting off the supply of electric power to the driving means when the display device is on.