JPH0846602A - Two-way circuit system - Google Patents

Abstract

PURPOSE:To provide the two-way circuit system able to propagate a signal simultaneously even in the reverse direction while the signal is propagated in one direction between 1st and 2nd two-way circuits without the need for external special control. CONSTITUTION:First and second 2-way circuits 1, 2 have transistors(TRs) 11, 21 of different conduction types respectively, each control gate electrode connects to a reception terminal 17 (27) and other electrode connects to a bus terminal 19 (29), and the circuits 1, 2 has a logic circuit deciding an output signal providing an output to transmission terminals 18, 28 based on a signal from the bus terminals 19, 29 and an input signal given to reception terminals 17, 27. When a high level H and a low level L are respectively given to the reception terminals of each 2-way circuits, a threshold level of each logic circuit is decided based on a potential '(Vh+Vl)/2' of the bus terminal and four combination states of the high level H and the low level L at the reception terminals 17, 27 and the transmission terminals 18, 28 are realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bidirectional circuit system capable of bidirectionally propagating data on a bus signal line, and a bidirectional circuit used in this system.

[0002]

2. Description of the Related Art Conventionally, this type of bidirectional circuit system and bidirectional circuit are described in "CMOS Digital Circuit Manual" (Yojiro Yokoi, page 204, Radio Technology Co., Ltd.). In this system, in order to propagate data bidirectionally through a bus signal line, bidirectional circuits having the same configuration are connected to both ends of the bus signal line, and the respective bidirectional circuits are mutually connected. The transmission gate system is used to transmit data from one side to the other on the bus signal line at different times.

More specifically, as shown in FIG. 4, the bidirectional circuit system includes two bidirectional circuits 4 connected to both ends of the bus signal line 3, and the bidirectional circuits are It has the same circuit configuration. Therefore, here
Only one of the bidirectional circuits 4 will be mainly described. The illustrated bidirectional circuit 4 includes a reception terminal 45, a control terminal 46,
The bus terminal 48 includes a transmission terminal 47 and a bus terminal 48.
Is connected to one end of the bus signal line 3. The bidirectional circuit 4 is composed of an LSI, and specifically, P
It has a channel transistor 41, an N-channel transistor 42, a NOT circuit 43, and a buffer circuit 44. In this case, the P-channel transistor 41 and N
The sources and drains of the channel transistors 42 are commonly connected and are connected to the reception terminal 45 and the bus terminal 48. Also, the P-channel transistor 41 and N
The gate of the channel transistor 42 is connected to the control terminal 46 directly and via the NOT circuit 43, respectively. Further, the common connection terminal of the drain is the buffer circuit 44.
It is connected to the transmission terminal 47 via.

Next, the circuit operation described above will be described.
Transistors 41, 42 and NOT circuit 43 form a transmission gate circuit and control terminal 46
When the input is low potential L, the input signal from the receiving terminal 45 is output to the bus terminal 48. That is, the control terminal 46
Is at a low potential L, the gate of the P-channel transistor 41 is at a low potential L and the transistor 41 is in a conductive state, that is, in an "ON" state. On the other hand, negation circuit 4
The high potential H is applied to the gate of the N-channel transistor 42 connected through the inverter No. 3, and the transistor 42 also becomes conductive, that is, "ON". In this state, the input signal from the receiving terminal 45 is propagated to the bus terminal 48 from the source S of both transistors 41 and 42 through the drain D.

On the other hand, when the input of the control terminal 46 is at the high potential H, the transistors 41 and 42 are both in the non-conducting state, that is, the "OFF" state, contrary to the above, and the sources of the transistors 41 and 42, The impedance between the drains becomes high, and the input signal from the bus terminal 48 can be propagated to the transmission terminal 47 via the buffer circuit 44.

According to this structure, when the low potential L is applied to one of the control terminals 46 of the two bidirectional circuits and the high potential H is applied to the other, the bidirectionality of the low potential L is given. High potential H from the receiving terminal 45 of the circuit through the bus signal line 3.
The signal can be propagated to the transmission terminal 47 of the bidirectional circuit. On the other hand, when propagating the input signal in the opposite direction, at the control terminals 46 of the two connected bidirectional circuits,
One of the control terminals 46 of the bidirectional circuit 4 has a low potential L.
To a high potential H, and the potential of the control terminal of the other bidirectional circuit 4 is changed from a high potential H to a low potential L,
The input signal can be propagated in the opposite direction.

[0007]

In the above-described conventional bidirectional circuit system, the bidirectional circuit having the same structure, which is formed by the LSI, is connected to both ends of the bus signal line, and
It is necessary to control the potential of the control terminal 46 of each bidirectional circuit to a low potential L on the transmitting side and to set the potential of the control terminal on the receiving side to a high potential H. According to this configuration, not only a circuit for controlling transmission and reception from the outside is required between the two bidirectional circuits, but also in the state where the signal is propagated in one direction,
There is a problem that signals cannot be propagated in the opposite direction.

An object of the present invention is to eliminate the need for external special control between two bidirectional circuits connected by a bus signal line, and to propagate signals in one direction, and also in the opposite direction. The purpose is to provide a bidirectional circuit system capable of transmitting signals at the same time.

[0009]

According to the present invention, there is provided a first receiving terminal, a first transmitting terminal, and a first bus terminal, the first bus terminal being connected to one end of a bus signal line. A first bidirectional circuit that outputs a signal from the first receiving terminal to the first bus terminal while outputting a signal from the first bus terminal to the first transmitting terminal; Receiving terminal,
A second transmission terminal and a second bus terminal are provided, the second bus terminal is connected to the other end of the bus signal line, and the signal from the second reception terminal is sent to the second bus terminal. on the other hand,
A second bidirectional circuit for outputting a signal from the second bus terminal to the second transmission terminal, wherein the first and second bidirectional circuits are simultaneously provided to the first and second receiving terminals. Even when a signal is given, the bidirectional circuit system is obtained, which is characterized in that the signal appears as it is at the second and first transmission terminals simultaneously.

Further, according to the present invention, in a bidirectional circuit capable of bidirectionally propagating a signal through the bus signal line, the source is connected to the high potential Vh, and the drain is a predetermined resistance value R.
Connected to the low potential Vl and the bus terminal through a resistor having a gate, and further connected to the bus terminal and a P-channel transistor whose gate is connected to the reception terminal, and to a high level H or with a predetermined threshold value. When the level determining means for determining the low level L and outputting, and the output level of the level determining means and the level received from the receiving terminal are input, and the potential of the bus terminal is approximately “(Vh + Vl) / 2”, A bidirectional circuit is provided, which is provided with a reception signal output means for outputting a level different from the level input from the reception terminal to the transmission terminal.

Further, according to the present invention, in a bidirectional circuit capable of bidirectionally propagating a signal through a bus signal line, a source is connected to a high potential Vh via a resistor having a predetermined resistance value R.
And a bus terminal, a drain thereof is connected to a low potential Vl, and a gate thereof is connected to a receiving terminal, and an N-channel transistor connected to the bus terminal, and a high level H or low with a predetermined threshold value. When the level determination means that determines and outputs the level L, the output level of the level determination means, and the level received from the reception terminal are input, and the potential of the bus terminal is approximately "(Vh + Vl) / 2", transmission is performed. A bidirectional circuit having a reception signal output means for outputting a level different from a level input from the reception terminal to a terminal is obtained.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a bidirectional circuit system according to an embodiment of the present invention. The bidirectional circuit system shown in FIG. 1 is connected to both ends of a bus signal line 3. It has respective bidirectional circuits 1 and 2. As is clear from the figure, one bidirectional circuit 1 (hereinafter, referred to as a first bidirectional circuit) has a P-channel transistor 11 as a switch element, and the other bidirectional circuit (hereinafter,
The second bidirectional circuit 2 is an N-channel transistor 2
It can be seen that 1 is provided as a switch element, and both have different configurations. Each of the bidirectional circuits 1 and 2 has receiving terminals 17 and 27 for receiving an input signal, a transmitting terminal 18 for outputting an input signal from the bus signal line 3 as a transmitting signal,
28 and the bus terminals 19 and 29, and the control terminal as shown in FIG. 4 is not provided.

First, the high potential Vh is directly applied to the source of the P-channel transistor 11 of the first bidirectional circuit 1, and the low potential Vl is applied to the drain thereof via the resistor 12. The drain is connected to the bus terminal 19. The gate of the transistor 11 is connected to the reception terminal 17.

On the other hand, the high potential Vh is applied to the source of the N-channel transistor 21 of the second bidirectional circuit 2 via the resistor 22, and the source is connected to the bus terminal 29. The low potential Vl is directly applied to the drain. Further, the gate is connected to the reception terminal 27.

Further, the bus terminal 1 of the first bidirectional circuit 1
A buffer circuit 13, a NOT circuit 14, an exclusive OR circuit 15, and an AND circuit 16 are provided between the transmission line 9 and the transmission terminal 18.
Is connected. Here, the buffer circuit 13 and
A bus terminal 19 is connected to the input side of the NOT circuit 14, and a reception terminal 17 and a buffer circuit 13 are connected to the input side of the exclusive OR circuit 15. Moreover, the logical product circuit 16 is connected to the output side of the exclusive OR circuit 15 and the NOT circuit 14 on the input side, and to the transmission terminal 18 on the output side.

Similarly, the bus terminal 2 of the second bidirectional circuit
The buffer circuit 23, the NOT circuit 24, the exclusive OR circuit 25, and the logical product circuit 26 are also provided between the transmission line 9 and the transmission terminal 28.
Is connected.

Here, the transistors 11 and 21 have the same resistance value between the source S and the drain D when conducting, and the resistors 12 and 22 are sufficiently larger than the resistance value when conducting the transistors 11 and 21. It has the same resistance value R. The buffer circuits 13 and 23 are provided with the first threshold potential S1,
The NOT circuits 14 and 24 have a second threshold potential S2. The potentials S1 and S2 are set by the following equation.

(Vh + Vl) / 2>S1> Vl (1) Vh>S2> (Vh + Vl) / 2 (2) Next, FIG. 1 shows the state diagram of FIG. The signal transmission / reception operation will be described with reference to the above.

In the first operation, as shown in FIG. 2A, the transmission terminal 18, while the high level H is input to both the reception terminals A17 and 27 of the bidirectional circuits 1 and 2, 28
This is an operation for outputting a high level H to both. Receiving terminal 1
When a high level H is input to each of 7 and 27, the source S and the drain D of the transistor 11 become non-conductive, and the source S and the drain D of the transistor 21 are disconnected.
Conductive state between and.

As a result, the bus terminals 19 and 29 are both at the low potential Vl, the buffer circuits 13 and 23 output the low level L from the equation (1), and the negation circuits 14 and 24 are high from the equation (2). Output level H. In this state, since the exclusive OR circuits 15 and 25 output the high level H, the logical product circuits 16 and 26 which input the high level H and the high level H output from the NOT circuits 14 and 24 are transmitted. High level H is output to terminals 18 and 28,
It can be seen that a high level H signal can be transmitted in both directions simultaneously.

In the second operation, as shown in FIG. 2B, a low level L is input to the receiving terminal 17 of the bidirectional circuit 1 and a high level H is input to the receiving terminal 27 of the bidirectional circuit 2. Is input, the high level H is output to the transmission terminal 18,
On the other hand, this is an operation of outputting a low level L to the transmission terminal 28. It is understood that by this operation, the low level L and high level H signals are simultaneously propagated in both directions and sent to the other transmission terminal.

Specifically, when the low level L is input to the receiving terminal 17, the source S of the transistor 11 is
A high potential Vh is output from the first bidirectional circuit 1 to the bus terminal 19 due to conduction between the drain D and the drain D. On the other hand, when the high level H is input to the receiving terminal 27, the source S and the drain D of the transistor 21 are also in the conductive state, but the low potential Vl is supplied to the bus terminal 29.

These bus terminals 19 and 29 are connected to the bus signal line 3
The bus signal line 3 is connected to "(Vh +
The potential becomes Vl) / 2 ". Therefore, the buffer circuit 1
3, 23 output the high level H from the equation (1), and the NOT circuits 14 and 24 output the high level H from the equation (2). In this state, the exclusive OR circuit 15 is at the high level H.
To output the high level H and the high level H output from the NOT circuit 14, the AND circuit 16 outputs the high level H to the transmission terminal 18. On the other hand, since the exclusive OR circuit 25 outputs the low level L, the low level L
The AND circuit 26 which receives the high level H output from the NOT circuit 24 outputs the low level L to the transmission terminal 28.

In the third operation, as shown in FIG. 2C, the high level H is applied to the receiving terminal 17 of the first bidirectional circuit 1.
Is input and the low level L is input to the reception terminal A27 of the second bidirectional circuit 2, the low level L is input to the transmission terminal 18.
Is output and a high level H is output to the transmission terminal 28.

When the receiving terminal A17 inputs the high level H, the source S and the drain D of the transistor 11 are non-conductive, and the low potential Vl is connected to the bus terminal 19. On the other hand, when the receiving terminal 27 inputs the low level L, the source S and the drain D of the transistor 21 are
The high potential Vh is connected to the bus terminal 29, although it is also in a non-conductive state between and. Also, these bus terminals C19, 29
Are connected by a bus signal line 3.

As a result, the bus signal line 3 becomes "(Vh + V
1) / 2 ″, the buffer circuits 13 and 23 output the high level H from the equation (1), and the negation circuit 1
4 and 24 output the high level H from the equation (2). In this state, the exclusive OR circuit 15 outputs the low level L, and therefore the AND circuit 16 which inputs the low level L and the high level H output from the NOT circuit 14 receives the low level L at the transmission terminal 18. Is output. On the other hand, since the exclusive OR circuit 25 outputs the high level H, the AND circuit 26 which inputs the high level H and the high level H output from the NOT circuit 24 outputs the high level H to the transmission terminal 28. it can.

The fourth operation is, as shown in FIG. 2D, the receiving terminal 1 of the first and second bidirectional circuits 1 and 2.
This is an operation of outputting the low level L to both of the transmission terminals 18 and 28 while the low level L is input to both 7 and 27. When the low level L is input to each of the receiving terminals 17 and 27, the source S and the drain D of the transistor 11 are
Becomes conductive with the source S of the transistor 21.
The drain and the drain D are not electrically connected.

As a result, the bus terminals 19 and 29 are both at the high potential Vh, the buffer circuits 13 and 23 output the high level H from the equation (1), and the negation circuits 14 and 24 are low from the equation (2). Output level L. In this state, the exclusive OR circuits 15 and 25 output the high level H, and therefore the logical product circuits 16 and 26 which input the high level H and the low level L output from the NOT circuits 14 and 24 are transmitted. The low level L is output to the terminals 18 and 28.

In this example, as shown in FIG. 1, in addition to the transistors 11 and 21 and the resistors 12 and 22,
It is composed of logic circuits, but this structure is an example,
The present invention is not limited to the above description as long as it has the same function.

For example, the bidirectional circuit 5 shown in FIG.
6 includes transistors 51 and 61 and a resistor 5
Reference numerals 2 and 62 have the same functions as the transistors 11 and 12 and the resistors 21 and 22 included in the bidirectional circuits 1 and 2, and the connections to the reception terminal and the bus terminal are also the same. The level determination means 53 and 63 are bus terminals 59 and 69.
The potentials "Vh", "(Vh + Vl) / 2", and "Vl" are determined, converted to a predetermined level value, and output. According to this result, the transmission signal output means 54 and 64 are set to the reception terminal 5
Input the inputs of 7, 67 and the output of the level determination means,
The reception terminals 57, 67 and the transmission terminals 58, 68 have a configuration in which four states as shown in FIG. 2 can be formed and output to the transmission terminals 58, 68.

[0032]

As described above, according to the present invention, one transistor has the source S connected to the high potential Vh and the drain D connected to the low potential Vl via the bus terminal and the resistor.
And the receiving terminal is connected to the gate. In the other transistor, the source S is connected to the bus terminal and the high potential Vh via a resistor, and the drain D
Is connected to the low potential Vl, and the gate is connected to the receiving terminal.

With this configuration, different high level H and low level L are provided to the receiving terminals of each of the two bidirectional circuits connected.
When and are input, the potential of the bus terminal to output "(Vh
+ Vl) / 2 ", the threshold potential is determined based on the high level H and low level L at the receiving terminal and the transmitting terminal.
By realizing the four combined states, signals can be simultaneously propagated on the bus signal line connecting the two bidirectional circuits.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment according to the present invention.

FIG. 2 is a state diagram showing an example state produced by FIG.

FIG. 3 is a functional block diagram showing an embodiment in which FIG. 1 is divided into blocks.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1, 2, 4, 5, 6 Bidirectional circuit 3 Bus signal line 11, 21, 51, 61 Transistor 12, 22, 52, 62 Resistor 13, 23 Buffer circuit 14, 24 Negative circuit 15, 25 Exclusive logic Sum circuit 16, 26 Logical product circuit 17, 27, 57, 67 Reception terminal 18, 28, 58, 68 Transmission terminal 19, 29, 59, 69 Bus terminal 53, 63 Level determination means 54, 64 Transmission signal output means

Claims (7)

[Claims] 1. A first reception terminal, a first transmission terminal, and a first bus terminal are provided, the first bus terminal is connected to one end of a bus signal line, and A first bidirectional circuit that outputs a signal from the first bus terminal to the first transmission terminal while transmitting the signal to the first bus terminal; a second reception terminal, a second transmission terminal; And a second bus terminal, the second bus terminal is connected to the other end of the bus signal line, and the signal from the second receiving terminal is sent to the second bus terminal while the second bus terminal is connected to the second bus terminal. Second signal from the terminal
And a second bidirectional circuit for outputting to the transmission terminal of the first and second bidirectional circuits, the first and second bidirectional circuits, even when signals are simultaneously applied to the first and second receiving terminals, Are configured so that they simultaneously appear in the second and first transmission terminals simultaneously, as they are. 2. The first conductive circuit according to claim 1, wherein the first bidirectional circuit includes a control electrode connected to the first receiving terminal and an electrode connected to the first bus terminal. Type transistor and a first logic circuit provided between the first bus terminal, the first reception terminal, and the first transmission terminal, and the second bidirectional circuit includes a second bidirectional circuit. A control electrode connected to the receiving terminal of the second electrode, and an electrode connected to the second bus terminal,
A second conductivity type transistor different from the first conductivity type transistor, and a second logic circuit provided between the second bus terminal, the second reception terminal, and the second transmission terminal. A bidirectional circuit system characterized by being configured. 3. The first and second bidirectional circuits according to claim 2, wherein when signals having different levels are simultaneously applied to the first and second receiving terminals, the first and second bidirectional circuits are connected to a bus signal line. , So that an output signal of a level equal to half the sum of both levels appears on the first and second bus terminals,
Circuits of first and second conductivity type transistors are configured, and the first and second logic circuits respectively have a first threshold level smaller than half of the sum of the two levels. And a circuit having a second threshold level greater than half the sum of the two levels. 4. A first and a second bidirectional circuit, each bidirectional circuit having a transmission terminal, a reception terminal, and a bus terminal, respectively, and connecting the bus terminals of the two circuits by a bus signal line. In a bidirectional system in which a signal can be bidirectionally propagated through a bus signal line, a first bidirectional circuit includes a resistor having a source connected to a high potential Vh and a drain having a predetermined resistance value R. Is connected to the low potential Vl and the bus terminal via the P-channel transistor whose gate is connected to the receiving terminal and the bus terminal, and is set to the high level H or the low level L with a predetermined threshold value. Level determination means for determining and outputting,
When the output level of the level determining means and the level received from the receiving terminal are input and the potential of the bus terminal is approximately “(Vh + Vl) / 2”, a level different from the level input from the receiving terminal to the transmitting terminal is input. A second bidirectional circuit, the source of which is connected to the high potential Vh and a bus terminal via a resistor having a predetermined resistance value R;
The drain is connected to the low potential Vl, and the gate is connected to the N-channel transistor connected to the receiving terminal and the bus terminal, and the high level H or the low level L is determined and output with a predetermined threshold value. The level determining means, the output level of the level determining means and the level received from the receiving terminal are input, and the potential of the bus terminal is almost "(V
In the case of h + Vl) / 2 ", the bidirectional circuit system is provided with a transmission signal output means for outputting a level different from the level input from the reception terminal to the transmission terminal. 5. The bidirectional circuit according to claim 4, wherein the level determination means and the transmission signal output means have a first threshold potential S1 and the input side is connected to the bus terminal. An exclusive OR having a buffer circuit, a NOT circuit having a second threshold potential S2 and having an input side connected to the bus terminal, and an input side connected to the output of the buffer circuit and the receiving terminal. And a logical product circuit for inputting the output of the exclusive OR circuit and the output of the NOT circuit and outputting the output to the transmission terminal, and the first threshold potential S1 is “(Vh +
Vl) / 2 "and a potential greater than" Vl ", and the second threshold potential S2 is less than" Vh "and greater than" (Vh + Vl) / 2 ". Bidirectional circuit system. 6. In a bidirectional circuit capable of bidirectionally propagating a signal through a bus signal line, a source is connected to a high potential Vh and a drain is set to a low potential Vl via a resistor having a predetermined resistance value R. A P-channel transistor connected to the bus terminal and having a gate connected to the receiving terminal, and a high-level H with a predetermined threshold value, connected to the bus terminal.
Alternatively, in the case where the level determination means for determining the low level L and outputting the level, the output level of the level determination means and the level received from the reception terminal are input, and the potential of the bus terminal is approximately “(Vh + Vl) / 2”. And a transmission signal output means for outputting a level different from the level input from the reception terminal to the transmission terminal. 7. A bidirectional circuit capable of bidirectionally propagating a signal through a bus signal line, wherein a source is connected to a high potential Vh via a resistor having a predetermined resistance value R and a bus terminal, and a drain is connected. It is connected to the low potential Vl and further connected to the N-channel transistor whose gate is connected to the receiving terminal and the bus terminal, and has a high level H with a predetermined threshold value.
Alternatively, in the case where the level determination means for determining the low level L and outputting the level, the output level of the level determination means and the level received from the reception terminal are input, and the potential of the bus terminal is approximately “(Vh + Vl) / 2”. And a transmission signal output means for outputting a level different from the level input from the reception terminal to the transmission terminal.