JPH0846509A - Data processing unit - Google Patents

Abstract

PURPOSE:To execute diversified picture by a small hardware configuration by adopting the configuration such that a programmable logic circuit section and a control circuit section are densely coupled. CONSTITUTION:A CPU of the data processing unit 1 is made up of a data path section 2 and a control circuit section 3. Furthermore, an optional logic is realized by a programmable logic circuit section 5. Circuit information is programmed by a configuration circuit section 7 and fed from a memory 13 or 6. The basic CPU operation is executed by allowing the circuit section 3 to read an instruction stored in an instruction memory 12 and to decode the instruction and controlling the path section 2 through the use of the result. For example, in the case of considering a multiplication instruction, the multiplication is to be calculated with several clock signal times by using an ALU 9 and a shifter 8 only with the basic function of the CPU. However, when the circuit section 5 is programmed for a multiplier, the multiplication instruction stored in the memory 12 is executed by one clock by using the circuit section 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a small computer. The present invention relates to a technique for realizing a desired logic circuit with a general-purpose programmable logic circuit. In particular, it relates to rewritable control integrated circuit technology.

[0002]

2. Description of the Related Art A CPU (Central Processing Unit) performs a desired process by executing a program stored in a memory. Therefore, today, a control circuit unit by a CPU is mainly used for control purposes. And put peripheral circuits in the core as Gate Array and others,
A large number of application-specific integrated circuits (ASICs) have been designed in which a general-purpose programmable logic circuit is provided and a series of processing is performed by writing a program corresponding to the purpose.

Conventionally, such a programmable logic circuit for peripheral circuits is basically fixed once one function is written, and at least it cannot be rewritten during operation to be a logic circuit having a different operation. Can not.

[0004]

Therefore, once a program is written in one integrated circuit, it becomes a logical circuit that performs one logical operation, and this integrated circuit cannot be used for different purposes. When a large number of logic circuits are required to perform some processing, it is necessary to prepare a new integrated circuit each time even if they do not overlap in time.

If one programmable logic circuit is commonly used for several processes, it is necessary to configure the functions of the programmable logic circuit in various ways.
Focusing on a specific process, it is necessary to perform wasteful processing due to the large number of unnecessary gate circuits in the programmable logic circuit. There are drawbacks such as

The present invention has been made against such a background, and by enabling one hardware device to be used for different purposes, it is possible to execute various processes with a small hardware configuration. An object is to provide a data processing device. It is another object of the present invention to reduce the load on the control circuit unit that actively controls the peripheral circuit unit and improve the calculation speed.

[0007]

To this end, the present invention provides
It is characterized in that the programmable logic circuit unit and the control circuit unit (CPU) are tightly coupled to each other so that the control circuit unit can control programs and operations of the programmable logic circuit unit.

That is, the present invention provides a control circuit section (3).
A data path unit (2) for connecting the control circuit unit to an external controlled device; and a programmable logic circuit unit (5) for executing a logic circuit operation according to a program set by the data path unit. Is a data processing device mounted in one package.

A feature of the present invention is that the programmable logic circuit section (5) is composed of rewritable elements, and the memories (6, 13) connected to the programmable logic circuit section (5). And a program for changing the logical operation of the programmable logic circuit unit (5) is held in the memory, and the control circuit unit (3) stores the data between the programmable logic circuit unit (5) and the programmable logic circuit unit (5). It is provided with communication means executed via the path section (2) and means for selecting and loading the contents of the memory into the programmable logic circuit section by this communication means.

At least a part of the memory is preferably an internal memory (6) built in the package.

A part of the memory is preferably an external memory (13) connected to the package.

By thus allowing one configuration to be used for different purposes, it is possible to execute various processes with a small hardware configuration. Further, the peripheral circuit portion can be more actively and dynamically changed so as to reduce the load on the CPU function, and the overall processing speed can be improved.

The internal memory (6) is a 2-port memory, and the programmable logic circuit section (5) is logically divided into two and connected to two ports of the internal memory (6). Can also be

Thus, one programmable logic circuit section can be operated as two independent logic circuits.

An accumulator (4) for counting the instructions executed by the control circuit unit (3) is built in the package, and the control circuit unit (3) sets the count value of the accumulator (4) to a predetermined value. It is desirable to include means for activating the means for loading when reached.

As a result, the function to be operated can be automatically changed according to the number of instructions.

It is desirable to have an external clock input terminal. Further, a configuration may be adopted in which a plurality of external clock input terminals are provided, different clock signals are input to the plurality of external clock input terminals, and a part of the programmable logic circuit section is synchronized with the different clock signals.

As a result, when one programmable logic circuit section is operated as two independent logic circuits,
It can also be operated with different clocks.

The programmable logic circuit section (5) is provided with a connection path section for connecting a second programmable logic circuit section (15) mounted in another package, and the control circuit section (3) is provided with this connection path section. The second programmable logic circuit section (15) may be configured to include means for controlling the data path section (2) and the connection path section.

Accordingly, even when the function to be operated cannot be accommodated in one programmable logic circuit unit, the programmable logic circuit unit can be expanded by arbitrarily adding it.

[0021]

The control circuit unit and the external controlled device are connected by the data path unit (2). A programmable logic circuit unit (5) that executes a logic circuit operation according to a program set by the data path unit is mounted in one package together with the control circuit unit.

The programmable logic circuit section (5) is composed of rewritable elements, and the memories (6, 13) connected to the programmable logic circuit section (5) have the logic operation of the programmable logic circuit section (5). The program to be changed is held, and the control circuit unit (3) communicates with the programmable logic circuit unit (5) via the data path unit (2) to the programmable logic circuit unit of the memory. Select content and load.

As described above, by allowing one configuration to be used for different purposes, one piece of hardware can be used as a temporally different device. Thereby, various processes can be executed with a small hardware configuration. Further, the peripheral circuit portion can be more actively changed dynamically so as to reduce the load of the CPU function of the control circuit portion, and the overall processing speed can be improved.

At least a part of the memory is built in the package. Further, a part of the external memory connected to the package can load various programs.

The internal memory (6) is a two-port memory, and the programmable logic circuit section (5) is logically divided into two parts, which are respectively connected to two ports of this internal memory (6). By doing so, two independent programs can be executed in parallel.

By counting the instructions executed by the control circuit unit and executing the load when the accumulated value reaches a predetermined value, the programmable logic unit is automatically operated without any particular operation. It is possible to set the circuit to another function. The function to be operated can be automatically changed according to the number of instructions.

If a plurality of external clock input terminals are provided and different clock signals are input to the plurality of external clock input terminals so that a part of the programmable logic circuit section is synchronized with the different clock signals, independent two clock signals can be provided. It is possible to change and execute one program with different clocks.

The programmable logic circuit section (5) is provided with a connection path section for connecting the second programmable logic circuit section (15) mounted in another package, and the control circuit section (3) is provided with this second programmable logic circuit section (3). Logic circuit part (1
By controlling 5), even when the function to be operated cannot be accommodated in one programmable logic circuit unit, the programmable logic circuit unit can be arbitrarily expanded to expand the programmable logic circuit unit.

According to the present invention, since the peripheral circuit configuration of the control circuit unit is configured by the programmable logic circuit unit and the information can be closely exchanged with the control circuit unit, the peripheral circuit configuration is not at the time of manufacturing. , Can be changed dynamically immediately before or during use.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an apparatus according to the present invention. FIG. 2 is an overall configuration diagram of the embodiment of the present invention.

According to the present invention, the control circuit unit 3, the data path unit 2 for connecting the control circuit unit 3 and the external controlled device 60 shown in FIG. 2, and the program controlled by the data path unit 2 are set. And a programmable logic circuit unit 5 that executes a logic circuit operation according to the above.

Here, the feature of the present invention is that the programmable logic circuit unit 5 is composed of rewritable elements, and the 2-port memory 6 as a memory connected to the programmable logic circuit unit 5 and the external configuration memory. A memory 13 is provided, and a program for changing the logical operation of the programmable logic circuit unit 5 is held in the 2-port memory 6 or the configuration external memory 13, and the control circuit unit 3 is connected to the programmable logic circuit unit 5. And a means for causing the programmable logic circuit portion 5 to select and load the contents of the 2-port memory 6 or the configuration external memory 13 by means of this communication means. It is in. Here, the communication means and the means for selecting and loading are realized by software programmed in the control circuit unit 3. However, since this can be realized by a known technique, detailed description thereof will be omitted.

The 2-port memory 6 is an internal memory built in the package. The configuration external memory 13 is an external memory connected to the package.

In the CPU-embedded data processing device 1, the data path unit 2 and the control circuit unit 3 form a CPU. Further, the programmable logic circuit unit 5 can realize any logic. The circuit information is programmed by the configuration circuit unit 7. The circuit information is the external memory for configuration 13 or 2
It is supplied from the port memory 6.

In the basic CPU operation, after the control circuit section 3 reads the instruction stored in the instruction external memory 12 in synchronization with clock 0, it is decoded by the internal decoder 11 and the result is used for data Shifter 8, A in the pass section 2
LU (Arithmetic and Logical unit)
9, by controlling the register file 10. On the other hand, the programmable logic circuit unit 5 can realize any hardware that operates in synchronization with the clock 1 or the clock 2, and the 2-port memory 6 can be used for data storage as needed. For example, when considering a multiplication instruction, the multiplier is the data path unit 2 only with the basic functions of the CPU.
Since it is not within the range, it is necessary to use the ALU 9 (addition function) and the shifter 8 for several clocks for calculation. However, when the programmable logic circuit unit 5 is programmed as a multiplier, the multiplication instruction stored in the external memory 12 can be executed in one clock by using this programmable logic circuit unit 5. Therefore, the execution time can be shortened.

At this time, the programmable logic circuit section 5 and C
Data transmission / reception between the data path unit 2 and the control circuit unit 3 which are PU units is performed using a bidirectional bus, and a part of the registers of the register file 10 and a part of the logic configuration unit in the programmable logic circuit unit 5 are exchanged. It can also be done by a dedicated line 18 that directly connects A series of control is performed by the control circuit unit 3,
It is sent to the programmable logic circuit section 5 and the data path section 2 through the control lines 19 and 20. Also,
The internal state of the programmable logic circuit unit 5 is also detected using the control line 19. The programming of the programmable logic circuit unit 5 is performed from the configuration circuit unit 7 through the control line 22, and the trigger is triggered by the external signal 24 or the signal from the control circuit unit 3 at the time of initial setting of other circuits. It is given from 21.

Next, an example of using the programmable logic circuit section 5 will be described with reference to FIG. FIG. 3 is a diagram showing an example of use of the programmable logic circuit unit. The programmable logic circuit unit 5 is supplied with two systems of clocks, clock 1 and clock 2, and programmable logic circuit units 50 and 51, which operate with different clocks, can be programmed as shown in FIG. Therefore, 2
It is also possible to configure a circuit for adjusting the speed by using the port memory 6 as a FIFO buffer.

Next, the operation type accumulator 4 will be described with reference to FIG. FIG. 4 is a block diagram of the calculation type accumulator 4. The operation type accumulator 4 accumulates the operations loaded by the control circuit unit 3 for a certain period of time for each type and informs the control circuit unit 3 if a certain accumulated value becomes larger than a preset value. With function. Upon receiving the result, the control circuit unit 3 instructs the configuration circuit unit 7 through the control line 21 to program the corresponding hardware in the programmable logic circuit unit 5. The configuration circuit unit 7 stores hardware information stored in advance in the configuration external memory 13 or hardware information dynamically created on the 2-port memory 6 by the control circuit unit 3 using the data path unit 2. To program the programmable logic circuit section 5 into a desired circuit. When the programming is completed, the configuration circuit section 7 informs the control circuit section 3 of the fact using the control line 21. After that, the control circuit unit 3 controls such that the programmable logic circuit unit 5 does not perform the corresponding operation in the data path unit 2. As a result, the arithmetic operation having a high appearance frequency is executed by the dedicated hardware, and the processing speed is improved.

FIG. 4 shows an example of the configuration of the operation type accumulator 4. The signal output from the control circuit unit 3 each time an instruction is executed is decoded by the decoder 32, and the counter of the corresponding operation of the counter 33 is incremented by 1. Comparator 34 is register 3
The value set in 6 is compared with the value of each counter, and the number of the counter exceeding the value of the register is output to the control circuit unit 3. The counter 33 is periodically reset by the timer 35 to "0". The time setting of the timer 35 and the setting of the value of the register 36 can be performed from the control circuit unit 3 and the outside.

The operation type accumulator 4 is not an individual dedicated circuit but the programmable logic circuit section 5 of FIG.
It can also be realized by programming in the process before processing operation.

The programmable logic circuit unit 5 has a finite circuit scale that can be realized. When the circuit scale to be realized exceeds the capacity of the programmable logic circuit unit 5, the data processor 1 connects the external pin for connection to the connection path unit 70 so that the expansion circuit 14 can be connected as shown in FIGS. I have The expansion circuit 14 includes a 2-port memory 17, a programmable logic circuit section 15, and a configuration circuit section 16.
The two-port memory 6, the programmable logic circuit unit 5, and the configuration circuit unit 7 have the same structure, and the signal lines are wired so that the control circuit unit 3 can also see the same.

Next, an operation example of the apparatus of the present invention will be described with reference to FIGS. 5 and 6 are views showing an operation example of the apparatus according to the present invention. The operation example shown in FIG. 5 is an operation example in which the function loaded in the programmable logic circuit unit 5 is changed by the counter 33 of the operation type accumulator 4 counting up. First, the function A is loaded from the memory (6 or 13) into the programmable logic circuit unit 5 (S1). Then, the function A is executed (S2). Here, the number of execution instructions of the function A is accumulated in the counter 33 as a cumulative count value. When the cumulative count value reaches b (S3), the function A is discarded in the programmable logic circuit unit 5, and another function B is loaded from the memory (6 or 13) (S4). Then, the function B is executed (S5). Subsequently, the number of execution instructions of the function B is accumulated in the counter 33 as a cumulative count value. When the cumulative count value reaches c (S6), the function B is discarded in the programmable logic circuit unit 5, and another function C is loaded from the memory (6 or 13) (S7). In this way,
When the counter 33 of the operation type accumulator 4 counts up, the function loaded in the programmable logic circuit unit 5 is changed.

The operation example shown in FIG. 6 is an operation example in which the function is changed after waiting for an input from the outside. First, the function D is loaded into the programmable logic circuit unit 5 (S1
1). Then, the function D is executed (S12). Function D
Stops when step d is reached (S13). At this time, for example, when an instruction is input from the outside by an operation or an output of external hardware (S14), the programmable logic circuit unit 5 discards the function D and loads the function E (S15). Then, the function E is executed (S1
6).

[0044]

As described above, according to the present invention,
Peripheral circuits that control the interface with the outside can be configured for each application immediately before use or during operation, not at the time of manufacture. According to the present invention, by dynamically changing the contents of the programmable logic circuit, it is possible to assist the CPU function of the control circuit unit and improve the processing capability of the entire circuit. By tightly coupling the CPU function and the programmable circuit unit, the programmable circuit unit can be reprogrammed as a circuit having a different function during operation so as to reduce the load on the CPU function. Thereby, for example, when a process with a large number of multiplications is executed, the dedicated multiplier is configured in the programmable circuit unit during the process, and by using it, the processing speed can be dynamically improved.

That is, according to the present invention, the peripheral circuit portion, which cannot be changed after manufacturing, can be changed so that one structure can be used for different purposes. Many functions can be realized with. According to the present invention, it is possible to realize a data processing device capable of coping with a wide variety of small quantities. Further, according to the present invention, it is possible to realize a data processing device that can more actively and dynamically change the peripheral circuit portion so as to reduce the load on the CPU function and improve the overall processing speed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing an example of use of a programmable logic circuit unit.

FIG. 4 is a block configuration diagram of a calculation type accumulator.

FIG. 5 is a diagram showing an operation example of the device according to the embodiment of the present invention.

FIG. 6 is a diagram showing an operation example of the device according to the embodiment of the present invention.

[Explanation of symbols]

 1 Data Processing Device 2 Data Path Unit 3 Control Circuit Unit 4 Operation Type Accumulator 5, 15, 50, 51 Programmable Logic Circuit Unit 6, 17 2 Port Memory 7, 16 Configuration Circuit Unit 8 Shifter 9 ALU 10 Register File 11 Decoder 12 external memory for instructions 13 external memory for configuration 14 extended circuit 18 dedicated lines 19-22 control lines 23, 24 external signal 32 decoder 33 counter 34 comparator 35 timer 36 register 60 controlled device 70 connection path unit

Claims (8)

[Claims] 1. A control circuit section (3), a data path section (2) for connecting the control circuit section and an external controlled device,
In a data processing device in which a programmable logic circuit unit (5) that executes a logic circuit operation according to a program set by the data path unit is mounted in one package, the programmable logic circuit unit (5) is rewritable. And a memory (6, 13) connected to the programmable logic circuit section (5), which holds a program for changing the logic operation of the programmable logic circuit section (5). The control circuit unit (3) includes a communication unit that is executed between the control unit and the programmable logic circuit unit (5) via the data path unit (2), and the programmable logic circuit unit is connected to the communication unit by the communication unit. A data processing device, comprising: means for selecting and loading the contents of a memory. 2. The data processing device according to claim 1, wherein at least a part of the memory is an internal memory (6) built in the package. 3. The data processing device according to claim 2, wherein a part of the memory is an external memory (13) connected to the package. 4. The internal memory (6) is a two-port memory, and the programmable logic circuit section (5) is logically divided into two and connected to two ports of the internal memory (6), respectively. The data processing device according to claim 2. 5. An accumulator (4) for counting instructions executed by the control circuit section (3) is built in the package, and the control circuit section (3) has a predetermined count value of the accumulator (4). The data processing apparatus according to claim 1, further comprising means for activating the means for loading when a value is reached. 6. An external clock input terminal is provided.
The described data processing device. 7. A plurality of external clock input terminals are provided, different clock signals are input to the plurality of external clock input terminals, and a part of the programmable logic circuit unit is synchronized with the different clock signals. Data processing equipment. 8. The control circuit section (3) is provided with a connection path section (70) for connecting the programmable logic circuit section (5) to a second programmable logic circuit section (15) mounted in another package. The data processing apparatus according to claim 1, further comprising means for controlling the second programmable logic circuit section (15) via the data path section (2) and the connection path section.