JPH0846208A - Thin-film transistor, semiconductor storage device using the same and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate the effect of grain boundary, reduce off leakage current and stabilize the on-resistance at a low value and diminish the dispersion of the on-resistance by placing an active element in a single solid-grown crystal grain having continuous crystal structure. CONSTITUTION:At least the channel regions of a PMOS transistors 103, 104 for load resistance are stored in a single crystal grain having continuous crystal structure, and no grain boundary is contained. Accordingly, a TFT, in which off leakage currents are reduced and which are stabilized at a low resistance value at an on time and in which dispersion is diminished extending over all memory cells, can be used as the PMOS transistors 103, 104. A crystal grain required in a space occupied by the channel region must be arranged for forming the channel region of the TFT in the single crystal grain. It becomes possible, for example, by generating artificial crystal nuclei at desired spatial positions of an a-Si film, and let them grow selectively in solid phase.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device as a nonvolatile random access memory (SRAM) and a manufacturing method thereof.

[0002]

2. Description of the Related Art A technique for forming a memory cell using a flip-flop circuit using a PMOS type thin film transistor (TFT) made of polycrystalline silicon (poly-Si) as a load resistance element has been developed for the purpose of highly integrating SRAM. Has been done. A typical item of preferable characteristics as the load MOS-TFT is that the leak current when the TFT is off is small,
A low resistance value can be obtained in a stable and small variation at the time of ON. However, it cannot be denied that the realization thereof is difficult due to the use of the poly-Si thin film. Improvement of these characteristics is one of the important technical issues for increasing the density, increasing the capacity, and increasing the speed of the semiconductor solid-state memory device.

The first problem of the poly-Si TFT is the off-leakage current. Since the poly-Si thin film includes an interface (grain boundary) between crystal grains having a high defect level density, it is not easy to keep the leak current at the time of OFF low. Generally, there is a tendency to advance the thinning of the channel part with the aim of suppressing the absolute value, but if it is left as it is, the resistance of the entire element will increase,
A sufficient on-current cannot be obtained. Therefore, by thickening or multilayering only the source / drain parts,
There has been proposed a method for reducing the increase in resistance to some extent (see, for example, JP-A-6-37283). However, this method complicates the TFT structure and, at the same time, causes the expansion of the memory cell size. Therefore, it is desirable to have a drastic solution to reduce the leakage current density itself in the channel portion.

The second problem is the temperature stability of the resistance value. In poly-Si, the trapping of charges by grain boundaries causes damage and the activation energy is large, so that the temperature dependence of the resistance value is not small. This problem is exacerbated as the memory cells become more highly integrated. As a solution, a method of implanting carbon or the like into a thin film has been proposed (see, for example, JP-A-2-58260), but such introduction of impurities is not preferable from the viewpoint of the above-mentioned leak current.

According to the consideration of the present inventors, both of the above two problems are caused by the existence of grain boundaries and, at the same time, depend on their spatial density. That is, if the crystal grain size is enlarged and the grain boundary density is reduced, the influence of the problem is alleviated. But,
Since the polycrystalline film is formed in the process of spontaneous nucleation and its growth at random positions, if the frequency of nucleation is suppressed with respect to the growth rate in order to increase the grain size, a large distribution of grain sizes is obtained. Occurs, and as a result, the spatial distribution of the grain boundary density becomes remarkable. Therefore, if the average crystal grain size is simply increased, the variation in the TFT characteristics is rather increased. Then, as a logical conclusion from the above consideration, it is ideally desirable to use a thin film having no grain boundary.

[0006]

SUMMARY OF THE INVENTION The present invention provides a thin film transistor having a small off-leakage current, a low resistance value when turned on, and a small variation, a high-density, large-capacity, high-speed semiconductor memory device using the same and a method of manufacturing the same. The purpose is to provide.

[0007]

In order to achieve the above object, the thin film transistor of the present invention is formed of polycrystalline silicon, but at least its active element has a single solid phase grown continuous crystal structure. It is characterized by being present inside the crystal grains. The active element is, for example, a MOS
It is a channel in a transistor. Further, in the semiconductor memory device of the present invention, the active elements of at least a part of the thin film transistors forming the memory cell are present inside a single crystal grain having a continuous solid phase grown crystal structure. Characterize. Such a single crystal grain can be formed, for example, by solid phase growth using a single crystal nucleus generated in an amorphous film as a seed. In a preferred embodiment of the present invention, the memory cell includes a flip-flop circuit having a load PMOS transistor, a driving NMOS transistor and a transfer NMOS transistor, and is activated inside a single crystal grain having the continuous crystal structure. The thin film transistor that must have the element is the load PM among the above transistors.
It is an OS transistor. The active element is then the channel of the load PMOS transistor. The load PMOS transistor is stacked in an upper layer of the driving NMOS transistor or the transfer NMOS transistor, and the NMOS transistor provided in a lower layer of the load PMOS transistor is a bulk transistor formed in a single crystal silicon substrate. is there. N for driving
When a MOS transistor is provided below the load PMOS transistor, the drain of the driving NMOS transistor also serves as the source of the transfer NMOS transistor.

In the method of manufacturing a semiconductor memory device of the present invention, amorphous silicon (a-Si) is used in solid phase crystallization.
As a method for selectively generating crystal nuclei at a desired position of the film and solid-phase growing the crystal nuclei, a part of the a-Si film is locally ion-implanted in the solid-phase crystallization of the a-Si film. And then heat treatment to selectively generate crystal nuclei at a desired position of the a-Si film and perform solid phase growth of the crystal nuclei.
Alternatively, in solid phase crystallization of the a-Si film, by locally applying an energy ray to a part of the a-Si film, a
A method of selectively generating a crystal film at a desired position of the Si film and solid-phase growing the crystal film can be applied.

[0009]

In the present invention, at least the active element of the thin film transistor is present inside a single crystal grain having a continuous solid phase grown crystal structure. As a result, in the thin film transistor of the present invention, the active element is formed in the ideal state described above, the influence of the crystal grain boundary is eliminated, the off leak current is small, the on resistance is a low resistance value, and it is stable and has a small variation. . Then, by using this as a load resistance element, a semiconductor memory device such as SRAM can be increased in density, capacity and speed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is an equivalent circuit diagram showing a configuration of one memory cell element in an SRAM according to an embodiment of the present invention. In the figure, the flip-flop circuit is composed of driving NMOS transistors 101 and 102 and load resistance PMOS transistors 103 and 104, and forms one memory cell together with the data transfer NMOS transistors 105 and 106. ing. NMOS transistor 101,
The source portions of 102 are both connected to the ground line 107, and PM
The source portions of the OS transistors 103 and 104 are both connected to the power supply line 108. The gate electrodes of the NMOS transistors 105 and 106 are both connected to the word line 109, and the source or drain of either one of them is connected to the bit lines 110 and 111. Of the six transistors, the NMOS transistors 101, 102,
105 and 106 may be, for example, bulk MOSs whose active regions are formed in a silicon single crystal wafer, or TFTs made of a poly-Si thin film. on the other hand,
The PMOS transistors 103 and 104 are TFTs stacked on the upper layers of the NMOS transistors 101 and 102 with an interlayer insulating film interposed therebetween.

As shown in FIG. 1, the equivalent circuit is the same as a normal SRAM memory cell. The SRAM according to the present embodiment is characterized in that at least the channel regions of the load resistance PMOS transistors 103 and 104 are contained in a single crystal grain having a continuous crystal structure and do not include a crystal grain boundary. Due to this feature, the off-leakage current is small in the PMOS transistors 103 and 104,
It is possible to use a TFT that has a low resistance value when it is turned on, is stable, and has little variation in all memory cells.

In order to form a TFT channel region inside a single crystal grain, a crystal grain of a required size must be arranged in the space occupied by the TFT channel region. This is possible, for example, by artificially generating crystal nuclei at a desired spatial position of the a-Si film and selectively performing solid phase growth. As a method of controlling the generation position of crystal nuclei, for example, a method of performing silicon ion implantation prior to solid phase growth (for example, H. Kumomi et a.
l. , Mat. Res. Soc. Symp.
Proc. Vol. 202, 645 (1991)
(Refer to) and the like, but the invention is not limited thereto.

FIG. 2 is a plan view of the formed memory cell. Here, the last two digits of the number assigned to each part are shown in Fig. 1.
The element corresponding to the last two digits of the number assigned to the equivalent circuit diagram of FIG. 2 corresponds to or constitutes the component shown in the equivalent circuit diagram of FIG. In addition, the part of the alphabet added to the end of the number is MO
It shows that it is a component of the S-transistor, and s, c,
d and g represent a source, a channel, a drain and a gate, respectively. Further, the part indicated by the chain double-dashed line indicates that it is an element of the element formed in the single crystal silicon, and the part is sequentially laminated in the order of the one-dot chain line, the chain line, and the solid line. It means that.

In FIG. 2, the driving NMOS transistor 101 of FIG. 1 has a source 201s and a drain 201d formed in single crystal silicon, and a gate electrode 201g formed of poly-Si on the upper layer of single crystal silicon.
It consists of Similarly, the driving NMOS transistor 102 is a driving NMO with respect to the center of the memory cell.
The source 202s is located at a position symmetrical with respect to the S transistor 101.
It is composed of the following parts. The drain 201d of the driving NMOS transistor 101 also serves as the source 205s of the transfer NMOS transistor 105. The transfer NMOS transistor 105 includes a source 205s and a drain 205d formed in single crystal silicon.
And a gate electrode 205g formed of poly-Si on the single crystal silicon layer. Similarly, the transfer NMOS transistor 106 is composed of a portion below the drain 206d and the gate electrode 206g at a position symmetrical to the transfer NMOS transistor 105 with respect to the center of the memory cell. All of the above are the constituent elements of the bulk MOS transistor and form the first layer of the laminated element group.

Although not shown in the figure, a poly-layer which serves as a ground line is formed on the first layer of the laminated element group via an insulating film.
A Si film is provided. However, this poly-Si
The film is omitted at the position where the upper layer and the first layer are connected, such as the plugs 213 and 214. And the ground wire p
The olly-Si film is used for the driving NMOS transistor 101.
And the sources 201s and 202s of the wirings 102 and 102, the connection plug 207, and the plugs at positions corresponding to the connection plugs 207 in point symmetry.

An insulating layer is provided again on the ground line poly-Si film. This insulating layer is the driving NM
Gate electrodes 201 of the OS transistors 101 and 102
g, 202g and openings for exposing part of the surfaces of the drains 201d, 202d. While filling these openings, polycrystalline silicon (poly-Si) islands 203
g, 204g are provided. Therefore, poly
-Si island 203g is a driving NMOS transistor 10
1 is connected to the gate electrode 201g and the source 206s of the transfer NMOS transistor 106, while pol
The y-Si island 204g is a driving NMOS transistor 1
The gate electrode 202g of No. 02 and the source 205s of the transfer NMOS transistor 105 are electrically connected.

An insulating layer is provided on the poly-Si islands 203g and 204g. This insulating layer is a region 212
Also, an opening is made in a region corresponding to the point-symmetrical position. A P-type poly-Si wire 208 is arranged on the upper layer. However, the region 204c and the region which is dual thereto are a single crystal grain having an intrinsic or low concentration n-type and a continuous crystal structure, and do not include a crystal grain boundary therein. Region 204 continuous with poly-Si line 208
The load resistance PMOS transistor 104 is formed by using c as a channel, both sides of the channel as sources and drains, and the underlying poly-Si island 204g as a gate electrode.
The dual PMOS transistor 103 is similarly configured. The source of the load resistance PMOS transistor 104 is directly connected to the power supply line 208, and the drain thereof is connected to the lower poly-Si island in the region 212, that is, the gate electrode 203g of the load resistance PMOS transistor 103. P for dual load resistance
The same applies to the source and drain of the MOS transistor 103.

These power supply line 208 and PM for load resistance
An insulating film is provided again on the OS transistors 103 and 104, and the word line 209 and the bit lines 210 and 211 are wired thereon with a metal material. The word line 209 is transferred N by the plug 214.
Gate electrodes 205 of the MOS transistors 105 and 106
It is connected to g and 206g. Bit lines 210 and 21
1 is connected to the drains 205d and 206d of the transfer NMOS transistors 105 and 106 by the plug 213 and its dual element, respectively. The memory cell shown in FIG. 1 is configured with the above spatial arrangement.

The manufacturing process of the memory cell shown in FIG. 2 will be described below with reference to FIG. Here, the group of sectional views in FIG. 3 is taken along the transverse line 200 in FIG. Further, an element in which the last two digits of the number given to each part correspond to the last two digits of the numbers given in FIGS. 1 and 2 corresponds to the component shown therein, or It composes parts.

First, an N well layer and a P well layer 300 were sequentially laminated on a (100) oriented p-type silicon single crystal wafer by a CVD epitaxial method. Next, the silicon surface is oxidized by about 100 nm to form a gate insulating film, and then the gate electrodes 302g, 30 made of poly-Si are formed.
6 g was formed. Next, by ion implantation and activation of phosphorus, n ⁺ regions 302s, 302d (306s), 306 are formed.
d was formed. Here, n ⁺ regions 302s and 302
source and drain part composed of d and gate electrode 302
The driving NMOS transistor 102 (30
2) was formed. Also, n ⁺ regions 306s and 30
Source and drain portions composed of 6d and gate electrode 30
The transfer NMOS transistor 106 (3
06) was formed. (FIG. 3 (a)). Next, an insulating film 315 made of a SiO ₂ film is deposited by the CVD method, and an n-type poly-Si film 307 is further deposited.
The ly-Si film 307 was provided with openings for exposing the surfaces of the gate electrode 302g and the drain 302d. Next, an insulating film was deposited again, and openings for exposing the surfaces of the gate electrode 302g and the drain 302d were also provided (FIG. 3A).

Next, while introducing phosphorus, n-type poly-
A Si film is deposited and patterned to form a poly-S.
The i regions 304g and 303g are provided. These correspond to the gate electrodes 204g and 203g of the load resistance PMOS transistors 104 and 103, respectively.
The gate electrode 304g is electrically connected to the gate electrode 302g of the driving bulk NMOS transistor 302, and the gate electrode 303g is electrically connected to the drain portion 302d. After that, a gate oxide film 316 was deposited by the CVD method, and an opening was provided on the gate electrode 303g (FIG. 3B).

Next, an a-Si film 317 having a thickness of 25 nm is deposited by an LPCVD method using disilane gas, a mask material 318 is provided, and then boron ions 319 accelerated to 20 keV are added at 5 × 10 ¹⁴ cm ^−2. (FIG. 3 (c)).

Then, when this was heat-treated at 600 ° C. in a nitrogen atmosphere, a single crystal nucleus 320 was preferentially generated in the region masked by the mask material 318 and solid phase growth was performed (FIG. 3 (d)).

As a result, at least the masked area became a single crystal nucleus 304c having a continuous crystal structure, and the other areas became a polycrystalline film 321 having random grain boundary positions. Therefore, this crystallized film is used as
After patterning into the shape shown in FIG.
Was deposited. As a result, the gate electrode 304g made of poly-Si and the gate oxide film 3 made of a SiO ₂ film are formed.
16, the load resistance PMOS transistor 104 having the channel 304c formed of a single crystal grain and the p ⁺ poly-Si regions 321 and 326 as the source and drain portions was formed (FIG. 3E).

Finally, although not shown in the cross section of FIG. 3, openings are provided in the regions of the plugs 207, 213 and 214, and a plug metal made of aluminum and silicon is embedded, and further the word line 309 and the bit lines 210 and 211 are filled. After performing the wiring of, the passivation layer 323 was deposited.

Through the above steps, the load resistance PMOS
The SRAM type semiconductor memory device shown in FIG. 2 in which the channel portion of the transistor exists inside a single crystal grain having a continuous crystal structure was formed.

[0027] The second embodiment of the second embodiment the present invention will be described with reference to FIG. The structure of the SRAM memory cell according to the second embodiment is the same as that of the first embodiment. Only the method of disposing a single crystal grain 304c at a predetermined position of the a-Si film 317 is different.

In the first embodiment, the same steps were performed until the step of depositing the gate oxide film 316 shown in FIG. 3B and forming the opening on the gate electrode 303g.

Then, an a-Si film 317 having a thickness of 40 nm is deposited by the LPCVD method using silane gas, and silicon ions 324 are accelerated with an energy of 35 keV and 1 × 10 ^{14.
Implanted at} a dose of cm ^-2 (Fig. 4). After that, the process returns to the same step as in the first embodiment, and after the dose mask material 318 is provided, the boron ions 319 accelerated to 30 keV are subjected to 5 ×.
Implantation was performed at a dose of 10 ¹⁴ cm ^-2 (FIG. 3C). Hereinafter, the same SR can be obtained by tracing the steps of the first embodiment.
An AM type semiconductor memory device is formed.

[0030] The third embodiment of the third embodiment the present invention will be described with reference to FIG. The structure of the SRAM memory cell according to the third embodiment is the same as that of the first embodiment. Only the method of disposing a single crystal grain 304c at a predetermined position of the a-Si film 317 is different.

In the first embodiment, the same steps were performed until the step of depositing the gate oxide film 316 shown in FIG. 3B and forming the opening on the gate electrode 303g.

Next, an a-Si film 317 having a thickness of 30 nm is deposited by the LPCVD method using disilane gas, and then,
A SiO ₂ film 318 having a thickness of 500 nm is deposited by the CVD method,
An opening was provided in part. When a xenon lamp having a power density of 10 Wcm ⁻² was irradiated from above the substrate while keeping the entire substrate at 500 ° C., a single crystal nucleus 320 was preferentially generated in the opening of the SiO ₂ film 318, and a solid phase was formed. It has grown (Fig. 5). As a result, the opening was occupied by a single crystal grain having a continuous crystal structure and became a random polycrystal in the other portion. So, after this,
A similar SRAM type semiconductor memory device was formed by tracing the steps after the patterning of the first embodiment described using (e).

As described above, in the solid phase crystallization, at least the channel is formed by the technique of selectively generating crystal nuclei at a desired position of the amorphous silicon (a-Si) film and solid phase growing the crystal nuclei. By disposing the portion inside a single crystal flow having a continuous crystal structure, the influence of the crystal grain boundary is eliminated, and a small off-leakage current, a low resistance value at the time of ON, and a stable and small variation are provided. be able to. Then, by using this as a load resistance element, a high-density, large-capacity, high-speed SRAM can be provided.

In the solid phase crystallization of the a-Si film,
A specific method of selectively generating crystal nuclei at a desired position of the a-Si film and performing solid phase growth by a step of performing heat treatment after locally performing ion implantation on a part of the a-Si film is described. PMOS-TF, which provides a low off-leakage current, has a low resistance value when on, and is stable and has little variation.
By using T as a load resistance element, a high-density, large-capacity, high-speed SRAM can be provided.

Alternatively, in the solid-phase crystallization of the a-Si film, energy nuclei are locally applied to a part of the a-Si film to selectively generate crystal nuclei at a desired position of the a-Si film. By providing a specific method for solid-phase growth of this, and by using a PMOS-TFT with a small off-leakage current, a low resistance value when ON, and a stable variation with a load resistance element, high density and large capacity can be achieved. -A high-speed SRAM can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an element configuration of a semiconductor memory device according to an embodiment of the present invention.

2 is a plan view showing the structure of one memory cell in the device of FIG. 1. FIG.

3 (a) to 3 (e) are cross-sectional views of a cross section taken along a transverse line 200 in FIG. 2 above the P well in each step for manufacturing the device of FIG.

FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the second embodiment of the present invention, which is above the P well in the cross section along the transverse line 200 in FIG.

FIG. 5 is a cross-sectional view showing a part of the manufacturing process of the third embodiment of the present invention, which is above the P well in the cross section taken along the transverse line 200 in FIG. 2;

[Explanation of symbols]

101, 102: driving NMOS transistors, 10
3, 104: PMOS transistor for load resistance, 10
5, 106: transfer NMOS transistor, 107: ground line, 108: power line, 109: word line, 110, 1
11: bit line, 204c, 304c: channel.

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[Procedure amendment]

[Submission date] November 14, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

FIG.

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8244 27/11 9056-4M H01L 29/78 613 B

Claims (12)

[Claims] A thin film transistor formed of polycrystalline silicon, wherein at least its active element comprises:
A thin film transistor characterized by being present inside a single crystal grain having a continuous crystal structure grown by solid phase growth. 2. The semiconductor memory device according to claim 1, wherein the thin film transistor is a MOS transistor, and the active element is a channel of the MOS transistor. A semiconductor memory device having a thin film transistor in a memory cell, wherein at least some of the active elements of the thin film transistor are present inside a single crystal grain having a continuous solid phase grown crystal structure. A semiconductor memory device characterized by: 4. The semiconductor memory according to claim 3, wherein the single crystal grain is formed by solid phase growth using a single crystal nucleus generated in an amorphous film as a seed. apparatus. 05. The memory cell comprises a load PMOS transistor, a driving NMOS transistor and a transfer NM.
4. A flip-flop circuit having an OS transistor, wherein the thin film transistor having an active element inside a single crystal grain having a continuous crystal structure is the load PMOS transistor. Alternatively, the semiconductor memory device according to item 4. 6. The semiconductor memory device according to claim 5, wherein the active element is a channel of the load PMOS transistor. 7. The semiconductor memory device according to claim 5, wherein the load PMOS transistor is stacked on an upper layer of the driving NMOS transistor or the transfer NMOS transistor. 8. The driving NMOS transistor or the transfer NMOS transistor provided on the upper layer of the load PMOS transistor is a bulk transistor formed in a single crystal silicon substrate. Semiconductor memory device. 9. The load PMOS transistor is provided on an upper layer of the driving NMOS transistor,
9. The semiconductor memory device according to claim 7, wherein the drain of the driving NMOS transistor also serves as the source of the transfer NMOS transistor. 10. A step of forming a P well layer on a surface of single crystal silicon, a step of forming an NMOS transistor pair sharing a source of one transistor and a drain of another transistor, and depositing a first insulating layer. A step of depositing a polycrystalline silicon layer as a ground electrode, a step of depositing a second insulating layer, a gate electrode of the NMOS transistor pair and the NM
A step of providing an opening exposing the surface of the n + region shared by the OS transistor pair, a step of depositing a polycrystalline silicon film filling the opening, a step of separating the polycrystalline silicon film into islands, A step of depositing an insulating film, and an n shared by the NMOS transistor pair is formed on the insulating film.
A step of forming an opening exposing the surface of the polycrystalline silicon island which is electrically connected to the + region; a step of depositing an amorphous silicon film; and a mask material directly above the polycrystalline silicon island electrically connected to the gate electrode of the NMOS transistor. A step of providing, a step of implanting ions, a step of removing the mask material, a step of heat-treating the amorphous silicon film at a temperature equal to or lower than a melting point to crystallize, and a step of linearly separating the crystallized film And a step of providing a wiring plug for electrically connecting one unshared source region of the NMOS transistor pair buried in a lower layer and a polycrystalline silicon layer as a ground electrode, to a gate electrode not electrically connected to the crystallization film of the NMOS transistor pair. A step of providing a conductive wiring plug and a metal wiring; and a step of electrically connecting the polycrystalline silicon layer serving as the ground electrode of the NMOS transistor pair. 10. The method according to claim 3, further comprising: a step of providing a wiring plug and a metal wiring that are electrically connected to the in, and a step of depositing a fourth insulating layer, and these steps are sequentially performed. Manufacturing method of semiconductor memory device. 11. A step of performing ion implantation different from the above-mentioned ion implantation is performed before the step of providing the mask material directly on the polycrystalline silicon island which is electrically connected to the gate electrode of the NMOS transistor. Item 11. The manufacturing method according to Item 11. 12. A step of forming a P well layer on a surface of single crystal silicon, a step of forming an NMOS transistor pair sharing a source of one transistor and a drain of the other transistor, and depositing a first insulating layer. A step of depositing a polycrystalline silicon layer as a ground electrode, a step of depositing a second insulating layer, a gate electrode of the NMOS transistor pair and the NM
A step of providing an opening exposing the surface of the n + region shared by the OS transistor pair, a step of depositing a polycrystalline silicon film filling the opening, a step of separating the polycrystalline silicon film into islands, A step of depositing an insulating film, and an n shared by the NMOS transistor pair is formed on the insulating film.
A step of forming an opening exposing the surface of the polycrystalline silicon island which is electrically connected to the + region; a step of depositing an amorphous silicon film; and a mask material directly above the polycrystalline silicon island electrically connected to the gate electrode of the NMOS transistor. A step of providing, a step of irradiating an energy ray to crystallize the amorphous silicon film, a step of removing the mask material, a step of linearly separating the crystallized film, and the NMOS embedded in a lower layer. Providing a wiring plug for conducting one unshared source region of the transistor pair and a polycrystalline silicon layer as a ground electrode, and providing a wiring plug and a metal wiring for conducting to the gate electrode not conducting to the crystallization film of the NMOS transistor pair. A process, and a wiring plug for electrically connecting the polycrystalline silicon layer, which is the ground electrode of the NMOS transistor pair, to the drain that does not electrically connect A step of performing genus wire, comprising the step of depositing a fourth insulating layer, and wherein the successively performing these steps, the method of manufacturing the semiconductor memory device according to any one of claims 3-9.