JPH0846148A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent short circuit between stack electrodes arranged on the opposite sides of a suspended part due to the residue being left in a recess between lower layer word lines after formation of the stack electrode through etching. CONSTITUTION:The clearance 38 at a suspended part provided for an electrode layer facing the contact holes at the suspended part is widened so that a recess 24 between lower layer word lines 1 is exposed to the clearance 38 at the suspended part. Since the etching residue after formation of a stack electrode is removed when the facing electrode layer 3 is overetched, short circuit is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor device having a multilayer wiring structure, and more particularly to a wiring structure suitable for application to a DRAM.

[0002]

2. Description of the Related Art In a miniaturized design such as a 4M DRAM, if a word line is formed of polysilicon, its specific resistance is large, so that the characteristic does not appear. A so-called hanging portion that connects the word layer and the lower word layer is provided to prevent the voltage drop of the word line. Such DRAM
The structure of the memory cell disposition portion will be described with reference to the drawings. FIG. 4 is a plan view of that portion. However, some patterns are omitted to make the points easy to understand.
The memory cell is a MOS using the lower word line 1 as a gate electrode.
It is composed of a transistor (not shown) and a capacitor connected to it. The capacitor is formed in most of the memory cell arrangement portion through the stack electrode 2 and a thin dielectric layer (not shown) above it. Counter electrode layer 3 which is Although a large number of memory cells are arranged in a matrix, the bit line contact holes 4 connecting the bit lines (not shown) arranged in a direction orthogonal to the lower word line 1 and the MOS transistors are made small. Since there is a limit to the number, they are arranged in a staggered pattern as shown in the figure to increase the number of arrangements per unit area.

By the way, since the lower word line 1 is composed of a heat resistant material such as polysilicon, if the resistance is large and only the lower word line is present, the voltage will not be uniform depending on the location due to the voltage drop. Therefore, another word line (not shown) is provided in the upper layer by Al or the like, and the hanging portions 5 are provided at appropriate pitches of the memory cells. In this region, the upper and lower word lines are connected through the hanging portion contact holes 6. To do. Therefore, although the counter electrode layer 3 is provided in almost the entire area, the bit line contact hole 4 and the hanging portion contact hole 6 are provided so as to penetrate the counter electrode 3, so that the bit line contact escape 7 and the hanging portion contact escape. 8 and 8 are formed. The relief 8 of the hanging portion contact is formed as a series of holes by assembling several adjacent hanging portion contact holes. In addition, escape 8 of adjacent hanging part contact
Since it is a portion where the counter electrode layer 3 is connected and the whole surface is kept at the reference potential, it is not preferable to make the clearance 8 of the hanging portion contact too large. Next, the structure of the memory cell arrangement portion will be described in detail by using the manufacturing method. 5A to 5C are cross-sectional views showing the portion along the line AA in FIG. 4 in the order of steps, showing the first half of the steps. FIG. 6 is a cross-sectional view showing the latter half of the process.
FIG. 7 is a cross-sectional view showing a step along the line BB in FIG. 4 in the order of steps, showing the first half of the steps. FIG. 8 is a sectional view showing the latter half of the process. In the manufacturing process, steps for forming elements and wirings arranged outside this region are omitted.

(1) A P well 11 is formed on a silicon substrate, and a field oxide film 13 for element isolation is formed on the surface except the MOS transistor forming region 12. Next, a gate oxide film 14 is formed in the MOS transistor formation region 12, polysilicon into which an impurity such as P is introduced is formed thereon, and patterning is performed to form the lower word line 1. Then, As or the like is ion-implanted using the field oxide film 13 and the lower word line 1 as a mask, and heat treatment is performed to form a source / drain (hereinafter referred to as SD). S. D is the capacitance side S.D. provided in each MOS transistor.
D15 and the bit line side S.D. There is D16. Next, a first interlayer insulating layer 17 made of SiO2 or the like is formed by CVD, and the first interlayer insulating layer 17 and the gate oxide film 14 are formed by photoresist and etching.
Through the S. A capacitive contact hole 18 exposing the surface of D is formed (see FIGS. 5a and 7a above).

(2) Next, a stack layer 2a made of polysilicon is formed by CVD. Then, impurities such as phosphorus are introduced to reduce the specific resistance, and the S. Improves electrical connection with D15. Impurities may be introduced during growth by CVD (see FIGS. 5b and 7b above).

(3) Next, the stack layer 2a is patterned by dry etching using a photoresist as a mask to form the stack electrode 2. The underlying layer of the stack layer 2a has irregularities, and if patterning is performed by dry etching having strong anisotropy, etching sidewalls and the like tend to be insufficiently etched. So that it does not exist (Figure 5c above,
See Figure 7c). (4) Next, a thin dielectric layer 19 made of silicon nitride or the like is formed by CVD or the like (see FIGS. 5d and 7d). (5) A counter electrode layer 3 made of polysilicon is formed thereon, and a photoresist is formed. The mask is patterned by dry etching. The counter electrode layer 3 is left almost all over the memory cell disposition region, and has a bit line contact relief 7 as shown in FIGS. 4 and 6e and a hanging portion contact relief 8 as shown in FIGS. 4 and 8e. Are etched away. At this time, since the underlying dielectric layer 19 is also very thin, it is removed during overetching (see FIGS. 6e and 8e above). (6) Next, CVD is performed to form SiO2 and BPSG thereon, and a planarization process is performed to form the second interlayer insulating layer 20. Then, by using the photoresist as a mask, the second interlayer insulating layer 20, the first interlayer insulating layer 17 and the gate oxide film 14 are penetrated by etching, and the S. A bit line contact hole 4 exposing the surface of D is formed. After that, for example, a tungsten silicide layer is formed by sputtering, and etching is performed using the photoresist as a mask, and the S. A bit line 21 connected to D16 and arranged in a direction orthogonal to the lower word line 1 is formed. (Above Fig. 6f,
See Figure 8f).

(7) Next, a third interlayer insulating layer 22 is formed by CVD or the like, and the third interlayer insulating layer 22, the second interlayer insulating layer 20, and the second interlayer insulating layer 20 and the second interlayer insulating layer 20 are formed in the hanging portion 5 by etching using a photoresist as a mask. 1. A hanging contact hole 6 that penetrates the first interlayer insulating layer 17 and exposes the surface of the lower word line 1 is formed, and a metal layer having a small specific resistance such as Al is formed on the hanging contact hole 6 by sputtering or the like. The upper word line 23 is formed by etching. Upper word line 23
Are provided corresponding to the respective lower layer word lines 1 and are respectively vertically connected to each other in the hanging portions 5 through the hanging portion contact holes 6 (see FIGS. 6g and 8g above).

[0008]

In the conventional DRAM described above, in the step of etching the stack layer 2a shown in FIGS. 4c and 6c to form the stack electrode 2, the etching residue 2b shown in FIG. Two
4b tends to occur. Therefore, it may occur depending on the process variation even though a considerable overetch is performed. It is difficult to limit the cause to one, but
One reason is that the underlying layer of the stack layer 2a has an uneven shape. That is, since the first interlayer insulating layer 17 is formed on the lower layer word line 1, the portion where the lower layer word line 1 is not present is a recess. Next, the cause of the possibility that etching residue tends to occur in the concave portion when the base is uneven is estimated. a) When a positive photoresist is applied, the recesses 24a, 2
4b and the like are thicker than other convex portions and flat portions, and are apt to be under-exposed or under-developed, and the photoresist remains on the surface during etching and is not etched. b) Since the etching anisotropy becomes strong, the etching of the sidewall of the recess does not proceed even if it is overetched. Etc. are possible.

Moreover, in the hanging portion 5, the stack layer 2a
While the whole is etched, the other part is designed to leave a considerable area as the stack electrode 2. As is well known, if there is a large difference in the area to be etched per unit area in one wafer, the etching rate of the area having a large area to be etched becomes slow. Therefore, the recess 24 in the hanging portion 5
Etching residue 2b tends to occur on a and 24b. When the etching residue 2b of the stack layer 2a as shown in FIG. 7c occurs in the concave portion 24a shown in FIG. 4, it remains to the end as shown in FIG. 8g and both sides of the hanging portion 5 shown by reference numerals 2c and 2d in FIG. The stack electrode of will be short-circuited. Therefore, if sufficient over-etching is performed to prevent this, the stack electrode 2 becomes smaller by that amount, and the capacitance becomes smaller, which is not preferable. Therefore, an object of the present invention is to provide a structure in which a short circuit defect does not occur even if extreme overetching is not performed.

[0010]

In a semiconductor device of the present invention, a plurality of lower wirings arranged close to each other and substantially parallel to each other, a first interlayer insulating layer covering the wirings, and partially formed on an upper layer thereof. A first conductive pattern formed on the first conductive pattern and a thin dielectric layer formed on the first conductive pattern, and the second conductive pattern is formed on a wide area and is made of the same material as or similar to the first conductive pattern. Conductive pattern and the second covering it
And an upper layer wiring formed on the upper layer wiring, which is connected to the lower layer wiring, and a large number of connection points between the upper layer wiring and the lower layer wiring, and on which the first conductive pattern is not arranged. In a semiconductor device having a wiring connection portion and a clearance for the connection point provided in the second conductive pattern, the clearance is widened, and the clearance between the first conductive patterns arranged on both sides of the connection portion is increased. Is arranged so that all the recesses connected by the recesses formed between the lower layer wirings are exposed to the escape somewhere. More specifically, that is, as a preferable example, the above semiconductor device is a memory cell arrangement portion of a DRAM, and the lower layer wiring, the first conductive pattern, and the second conductive pattern upper layer wiring are respectively a lower layer word line, a stack electrode, The counter electrode and the upper layer word line can be used, in which case the upper and lower wiring connection portions are so-called hanging portions of the word line.

[0011]

According to the above construction, the first and second wirings are connected to the upper and lower wiring connecting portions.
Since the conductive pattern of No. 2 is not arranged, in the etching step of forming the first conductive pattern, this portion has a low etching rate and is likely to have an etching residue in the concave portion.
If the shape of the relief of the connection point of the upper and lower wirings provided in the conductive pattern is enlarged and etching residue occurs, a short circuit failure occurs, that is, the first wirings arranged on both sides of the upper and lower wiring connection portions.
Since the recess connecting between the conductive patterns is exposed to escape somewhere, when the second conductive pattern is etched, the etching residue is also etched together with the thin dielectric layer thereabove by normal overetching. Therefore, it does not cause a short circuit. Therefore, it is not necessary to perform extreme overetching when etching the first conductive pattern.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to the DRAM described above. FIG. 1 is a plan view of a main part thereof, and the same parts as those in FIG. However, the lower layer wiring of the present invention, the first conductive pattern,
The reliefs for the second conductive pattern, the upper layer wiring, the upper and lower wiring connection portions, and the connection points are provided for the lower layer word line 1, the stack electrode 2, the counter electrode 3, the hanging portion 5, and the hanging portion contact 38 of this embodiment, respectively. Is equivalent to The difference between the conventional example shown in FIG. 4 and the present example is that the relief 38 of the hanging portion contact is widened so that the lower word lines 1, 1 in the hanging portion 5 are formed.
It is configured to be exposed over the entire width from the clearance 38 of the hanging portion contact at at least one place for each of the recesses 24 formed therebetween. Next, the manufacturing method will be used to explain the configuration. Since the cross-sectional views of the process along the line AA in FIG. 1 are the same as the conventional ones, the description will be given with reference to FIGS. 5A to 5D and FIGS. 7A to 7D are the same as the conventional ones in the cross-sectional views of the process along the line BB in FIG. However, conventional FIG. 8e
Since steps shown in FIGS. 2 to g are different in this embodiment, they will be described with reference to FIGS. Since the process up to the steps shown in FIGS. 5d and 7d is the same as the conventional one, the description of the manufacturing method and structure is omitted. However, as shown in FIG. 7c, the etching residue 2b tends to occur in the recess 24a. As shown in FIG. 1, the stack electrodes 2c and 2d arranged on both sides of the hanging portion 5 are short-circuited by the etching residue (reference numeral 2b in FIG. 6c) remaining in the recess 24a. A thin dielectric layer 19 made of silicon nitride or the like is formed thereon (see FIGS. 5d and 7d).

(1) Next, polysilicon is formed on the entire surface,
Etching is performed using a photoresist as a mask to form the bit line contact relief 7 and the hanging portion contact relief 38. The feature of this embodiment lies in the shape of the relief 38 of the hanging portion contact. The recesses are widened beyond the required dimensions so that all recesses 24 are exposed to the recesses 38 of this suspension contact somewhere at least at one location, as shown in FIG. By doing so, the thin dielectric layer 19 is also etched by the overetching process at the time of etching the counter electrode layer 3 and the etching residue 2b of the stack layer remaining in the recess 24a is also etched, and the short circuit between the stack electrodes 2c and 2d. Disappears (above Fig. 6e,
See Figure 2e).

(2) Next, CVD is performed to form SiO 2 and BPSG thereon, and a planarization process is performed to form a second interlayer insulating layer 20. Then, the photoresist is used as a mask for etching to penetrate through the second interlayer insulating layer 20, the first interlayer insulating layer 17 and the gate oxide film 14, and the bit line side S
・ Bit line contact hole 1 that exposes the surface of D16
4, a tungsten silicide film is formed by sputtering, etching is performed by using a photoresist as a mask, and the bit line 21 is formed in a direction orthogonal to the word line 1 by connecting to the bit line side S / D16. 6f, see FIG. 2f). (3) Next, a third insulating layer 22 is formed by CVD or the like, and etching is performed in the hanging portion 5 using an auto resist as a mask to etch the third interlayer insulating layer 22, the second interlayer insulating layer 20, and the first interlayer. The hanging portion contact hole 6 that exposes the surface of the lower word line 1 is formed through the insulating layer 17, a metal layer having a small resistance value such as Al is formed by sputtering, and etching is performed using a photoresist as a mask. The upper-layer word line 23 forming the above is connected to the lower-layer word line 1 in the hanging portion contact hole 6 to make its voltage distribution uniform. (See FIGS. 6g and 2g below) Thereafter, although not shown, passivation or the like is performed to complete the DRAM chip. According to the present embodiment, when the stack electrode 2 is formed by etching, an etching residue is likely to occur in the recessed portion of the base of the hanging portion 5, but the counter electrode layer is removed by the etching process of the subsequent process, and short-circuit defects are reduced. .

[0015]

[Embodiment 2] In the first embodiment described above, the relief of the suspension portion contact provided in the counter electrode layer is formed by collectively forming several suspension portion contact holes, but as shown in FIG. The recess 48 of the hanging part contact hole may correspond to one hanging part contact hole 6 so that only the nearest recess 24 is exposed. In this case, the stack electrodes 2, which are arranged on both sides of the suspension 5,
If there is a recess that does not connect the two, it may be excluded. In each of the above embodiments, the stack electrode 2 and the counter electrode layer 3 are made of polysilicon, but different materials such as silicide may be used. The same material is preferable, but different materials may be used as long as they have similar etching characteristics. Further, although the present invention is applied to the word line suspension portion of the DRAM in the above embodiment, it can be applied to other semiconductor devices having a similar structure.

[0016]

As described above, according to the present invention, the relief provided in the second conductive pattern with respect to the connection point of the upper and lower wirings is widened and is not generated due to the concave portion based on the lower wiring. Since the etching residue of the first conductive pattern is exposed so as to escape, the second conductive pattern is etched by the over-etching process during the etching.
Short-circuit defects of the conductive pattern of are reduced.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a drawing showing a cross section of the main part in the order of steps.

FIG. 3 is a plan view of another embodiment of the present invention.

FIG. 4 is a plan view of a conventional DRAM

FIG. 5 is a sectional view of the first half process showing a part of the process order.

FIG. 6 is a sectional view showing a subsequent half process.

FIG. 7 is a cross-sectional view of the first half process showing another part of FIG. 4 in process order.

FIG. 8 is a sectional view showing the subsequent half-steps.

[Explanation of symbols]

1 Lower layer word line (lower layer wiring) 2, 2c, 2d Stack electrode (first conductive pattern) 3 Counter electrode layer (second conductive pattern) 5 Hanging part (upper and lower wire connection part) 6 Hanging part contact hole (connection point) ) 17 first interlayer insulating layer 19 thin dielectric layer 20 second interlayer insulating layer 23 upper layer word line (upper layer wiring) 24, 24a, 24b recess 38, 48 escape of hanging part contact (escape to connection point)

Claims (3)

[Claims] 1. A plurality of lower layer wirings arranged close to each other and substantially parallel to each other, a first interlayer insulating layer covering the wirings, a first conductive pattern partially formed in an upper layer thereof, and a first conductive pattern formed thereon. Is formed through a thin dielectric layer and is made of the same material as the first conductive pattern or a material having similar etching characteristics,
A second conductive pattern formed in a wide area, a second interlayer insulating layer covering the second conductive pattern, an upper wiring formed on the second conductive insulating layer, which is connected to the lower wiring, and an upper wiring and a lower wiring. In a semiconductor device having a large number of connection points with and a top-and-bottom wiring connection portion where the first conductive pattern is not arranged, and a clearance with respect to the connection point provided in the second conductive pattern, All the recesses that are widened and connected by the recesses formed between the first conductive patterns arranged on both sides of the connection portion between the wirings of the lower layer are arranged to be exposed to the escape somewhere. A semiconductor device characterized by: 2. A plurality of lower layer word lines arranged in close proximity and substantially parallel to each other, a plurality of stack electrodes formed on the upper layer of the first insulating layer, and a thin dielectric layer formed on the upper layer of the stack electrode, and widely arranged. A counter electrode layer which is continuously provided and is made of the same material as the stack electrode or a material having a similar etching characteristic, and an upper layer word line which is provided on the opposite electrode layer through a second interlayer insulating layer and is connected to the lower layer word line. In the semiconductor device having a plurality of connection points of the upper-layer word line and the lower-layer word and a hanging portion having no stack electrode arrangement and a clearance for the connection point provided on the counter electrode, the clearance is widened. In addition, all the recesses connecting the stack electrodes arranged on both sides of the hanging part with the recesses formed between the lower layer word lines are arranged to be exposed to the escape somewhere. Semiconductor device. 3. The semiconductor device according to claim 2, wherein both the stack electrode and the counter electrode layer are made of polysilicon.