JPH0844980A - Fire alarming device - Google Patents

Abstract

PURPOSE:To preserve gathered data if a sub-CPU which gathers data from analog sensors gets out of order and to reduce watched area. CONSTITUTION:A receiver 1 has multi-CPU consisting of an M(main-CPU unit 100 and S(sub)-CPU units 101-10n provided by sensor lines L1-Ln. If one of the S-CPU units 101-10n gets out of order, the gathered data stored in the memory part 35 of the faulty S-CPU unit are saved in the memory part 25 of the M-CPU unit 100. The data saved in the memory part 25 are transferred to the memory 35 of the sub-CPU unit which is repaired or a replacing sub-CPU unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fire alarm device for detecting a fire by collecting smoke concentration data and temperature data detected by analog smoke detectors and heat detectors, and more particularly to smoke concentration data and temperature. The present invention relates to backup of a memory that stores data.

[0002]

2. Description of the Related Art Generally, in this type of fire alarm device, smoke concentrations and temperatures sequentially detected by smoke detectors and heat detectors are collected and stored in a memory, and a fire is detected based on the time-series data. Can be detected early. A receiver or a repeater to which this type of sensor is connected is a multi-CPU composed of a main CPU and a sub CPU provided for each sensor line.
The sub CPU collects data and stores it in the memory.

These collected data are individual data peculiar to analog sensors, for example, (1) dirt correction data (2) sensor type data (smoke sensor or heat sensor, etc.) (3) pre-alarm, fire, This is the alarm level for smoke prevention and smoke emission. (1) What is the dirt correction data? Once a week to once a month, a dirt correction coefficient is calculated and stored from the output value during normal monitoring and the output value during a fire test in order to correct the dirt on the sensor. Moreover, this data varies depending on the surveillance area such as a building.

[0004]

However, in the conventional fire alarm device, since the collected data in the memory disappears when the sub CPU fails, it takes 1 week to 1 month to collect the data again. There is a problem that it must be. Further, when the defective sub CPU is repaired or replaced, the type data for each analog sensor and the set value of the alarming sensitivity must be downloaded from the main CPU to the sub CPU. Since it is necessary to reset the entire system including the system once and restart the system, there is a problem that all the monitoring areas are in a non-warning state during this work. Of course, even if a fire occurs in a non-warned state, it is not possible to give an alarm, so a supervisor must monitor the entire monitoring area during the work of repairing or replacing the sub CPU. Reliability is reduced in the case of a building or in the case of multiple buildings.

In view of the above-mentioned conventional problems, the present invention can save the collected data when the sub CPU collecting the data from the analog sensor fails, and can reduce the unguarded area. It is an object to provide a fire alarm device.

[0006]

To achieve the above object, the present invention collects and stores data detected by an analog sensor provided for each sensor line and connected to the sensor line. One or more sub-Cs with memory
In a fire alarm device having a PU and one main CPU for performing fire alarm control by managing one or a plurality of sub CPUs, the collected data stored in the memory of the sub CPU when the sub CPU fails It is characterized by comprising a storage means and a transfer means for transferring the collected data to the memory of the sub CPU which has been repaired or replaced.

The present invention is also characterized in that the storage means is provided in the main CPU. The present invention is also characterized in that the main CPU and the plurality of sub CPUs are provided in the receiver or the repeater.

[0008]

According to the present invention, the collected data stored in the memory of the sub CPU when the sub CPU provided for each sensor line fails is stored in the storage means and saved, and repaired or replaced. Since it is transferred to the memory, the collected data can be saved if the sub CPU collecting the data from the analog sensor fails. Further, since the unguarded area is only the area monitored by the failed sub CPU, the unguarded area can be reduced.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram schematically showing an entire embodiment of a fire alarm device according to the present invention, and FIG. 2 is a block diagram showing the receiver of FIG. 1 in detail. In the example shown in FIGS. 1 and 2, the receiver 1 is an M (main) -CPU unit 100 and an S (sub) -CP provided for each of the sensor lines L1 to Ln.
It is composed of a multi-CPU composed of U units 101 to 10n. The receiver 1 also has a display unit 2 for displaying a fire and the like, and an acoustic alarm unit 3 for issuing an alarm with a bell or the like.
And the S-CPU unit 1 as will be described later with the recovery operation and the like.
An operation unit 4 is provided for backing up the memory when 01 to 10n fails.

Each of the sensor lines L1 to Ln has an analog sensor 5 for detecting smoke density and temperature, a relay 6 for driving an alarm bell 7, and a relay 8 for driving a damper 9. And a repeater 10 for sending an alarm signal of the on-off type sensor 11 to the receiver 1 and the like are connected. M
-As shown in detail in FIG.
M-CPU 21 for controlling the entire system, display unit 2,
I / O unit 2 for connecting the audible alarm unit 3 and the operation unit 4
2, a program memory 23, a serial I / O unit 24 for connecting a plurality of S-CPU units 101 to 10n via transmission lines L11 to L1n, smoke density data collected from the analog sensor 5, A memory unit 25 for storing temperature data is provided, and the members 21 to 25 are connected via a bus B.

The M-CPU unit 100 also receives smoke density data and temperature data from the analog sensor 5 as S-C.
The data lines L2 from the PU units 101 to 10n, respectively.
A switch unit SM and a bus buffer unit 26 for collecting via the 1 to L2n and storing in the memory unit 25 are provided. Further, the operation unit 4 includes S-CPU units 101 to 101.
In order to perform backup work of the memory 25 when 10n fails, a 3-digit number display 41 and a numeric keypad 42
A maintenance mode switch 43, a data memory read switch 43, and a data memory write switch 45 are provided.

Each of the S-CPU units 101 to 10n has an I for connecting the S-CPU 31 and each of the sensor lines L1 to Ln via a transmission interface section 37.
From the analog sensor 5 of each of the sensor lines L1 to Ln, the I / O unit 32, the program memory 33, the serial I / O unit 34 for connecting the serial I / O unit 24 of the M-CPU unit 100. A memory unit 35 for storing the collected smoke density data and temperature data is provided, and the members 31 to 36 are connected via a bus B.

Each of the S-CPU units 101 to 10n also includes switch units S1 to Sn and a bus for transferring the data stored in the memory unit 35 to the M-CPU unit 100 via the data lines L21 to L2n. A buffer unit 36 is provided, and the switch units S1 to Sn include the memory unit 35.
Can be connected to the data bus B or the bus buffer unit 36.

In such a system, for example, as shown in FIG. 3, the receiver 1 collects terminal information from each of the analog sensor 5 and the relay 10 to which the on / off type sensor 11 is connected by a polling method. In order to control the relays 6 and 8 to which the alarm bell 7 and the damper 9 are respectively connected, the analog sensor 5, the relays 6, 8 and 10 are set with individual unique addresses A1 and A2. To be done.

S-CPU units 101-on the receiver 1 side
The frame format from 10n to the analog sensor 5, the repeaters 6, 8 and 10 is added to the front of each of these 8-bit command field, address field and checksum field as shown in FIG. It is composed of a total of 33 bits including a start bit, a parity bit added later, and a stop bit.

Therefore, the S-CPU units 101 to 10n on the receiver 1 side set a calling command and a set address for each analog sensor 5 and repeaters 6, 8 and 10 in the command field and the address field, respectively. By sending to the sensor lines L1 to Ln, the analog sensor 5 and the repeaters 6, 8 and 10 can be called.

On the other hand, from the analog sensor 5, the relays 6, 8, and 10 to the S-CPU unit 10 on the receiver 1 side.
The frame format for 1 to 10n is, for example, as shown in FIG. 5, an 8-bit transmission data field and a checksum field, a start bit added before these fields and a parity bit and a stop bit added after these fields. The checksum data has a total of 22 bits, and the checksum data is a value obtained by adding the transmission data and the address of the transmission source.

Therefore, the analog sensor 5, the repeaters 6, 8 and 10 are the S-CPU unit 10 on the receiver 1 side.
In response to a call from 1 to 10n, its own address is sent to the sensor lines L1 to Ln together with data, and the S-CPU units 101 to 10n on the receiver 1 side transmit by subtracting the data from the checksum. It is possible to extract the addresses of the analog sensor 5 and the relays 6, 8, and 10 that have been selected.

Further, the S-CPU units 101 to 10n
Stores the collected data in the memory unit 35 for each address as (1) stain correction data. Further, the memory unit 35 stores (2) sensor type data (smoke sensor or heat sensor, etc.), (3) pre-alarm, fire, smoke proof and smoke prevention level from the M-CPU unit 100. It In such a configuration, for example, the S-CPU unit 10
When 1 fails, when the maintenance mode switch 43 of the operation unit 4 sets the maintenance mode as shown in FIG. 6 (step S1), the M-CPU unit 100 stops its operation as a normal fire alarm system. Then, the memory unit 3 on the S-CPU unit 101 to 10n side
The mode is changed to the mode in which the collected data is read from 5 to be in the ready state, and the switch section SM is turned on to connect the memory section 25 and the bus buffer section 25 (step S
2).

Then, using the ten-key pad 42 of the operation unit 4,
For example, the number "10" of the failed S-CPU unit 101
When "1" is input (step S3), this number "101"
Is displayed on the numerical display 41 (step S4), and then the data read switch 44 is turned on (step S5), the read command is sent from the M-CPU 21 to the serial I / O unit 24, the transmission line L11, and the S-CPU unit 101. S-CPU3 via the serial I / O unit 34 of
1 (step S6).

Next, in the S-CPU unit 101, the switch section S1 is switched from the bus B side to the bus buffer 36 side, the collected data in the memory section 35 is read, and the switch S1, the bus buffer 36, the data lines L21, M- are read. C
The data is transferred to the memory unit 25 via the bus buffer 26 and the switch unit SM on the PU unit 100 side and saved (step S7).

Then, after such processing, the faulty S
-The board on which the CPU unit 101 is mounted is removed and repaired or replaced (step S8). In addition,
When this board is removed, the power supplied to the S-CPU unit 101 is cut off and the data in the memory section 35 is erased. Next, when the number "101" of the repaired or replaced S-CPU unit 101 is input by the ten keys 42 (step S9), this number "101" is displayed by the numeral display 41 (step S10), and then the data writing switch. When 45 is turned on (step S11), the write command is MC
PU21 to serial I / O unit 24, transmission lines L11, S
-Transmitted to the S-CPU 31 via the serial I / O unit 34 of the CPU unit 101 (step S12).

Next, in the S-CPU unit 101, the switch section S1 is switched from the bus B side to the bus buffer 36 side, and the data saved in the memory section 25 on the M-CPU unit 100 side is switched to the switch section SM and the bus buffer 2.
6, data line L21, bus buffer 36, switch S1
Is transferred to and returned to the memory unit 35. Further, when this data transfer is completed, the switch section S1 returns to the bus B side.

Therefore, according to the above embodiment, the SC
When the PU units 101 to 10n fail, the collected data in the memory unit 35 is saved in the memory unit 25 on the M-CPU unit 100 side, so that the collected data can be saved. Further, during the repair or replacement work of the S-CPU units 101 to 10n, the sub-area monitored by the faulty S-CPU unit is only in the non-warning state.
Unguarded areas can be reduced.

In the above embodiment, the receiver 1 is MC
PU unit 100 and S-CPU units 101-10
Although the description has been given of the case of the multi-CPU consisting of n, instead of the relay board (relay) 10 as shown in FIG.
The present invention can also be applied to the case where is composed of multiple CPUs. It should be noted that this configuration can be applied to a system in which each of the plurality of relay boards 10 manages one building and the receiver 1 manages all the guard areas when the guard area is composed of a plurality of buildings, for example. .

[0026]

As described above, the present invention has a memory provided for each sensor line and having a memory for collecting and storing data detected by an analog sensor connected to the sensor line. Fire alarm control by managing multiple sub CPUs and one or more sub CPUs 1
In a fire alarm device having one main CPU, storage means for storing the collected data stored in the memory of the sub CPU when the sub CPU fails, and transfer for transferring the collected data to the memory of the repaired or replaced sub CPU Since the means is provided, it is possible to save the collected data when the sub CPU that collects the data from the analog sensor fails, and the unguarded area is only the area monitored by the failed sub CPU. The guard area can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing an entire embodiment of a fire alarm device according to the present invention.

FIG. 2 is a block diagram showing the receiver of FIG. 1 in detail.

FIG. 3 is a timing chart showing a data transmission sequence of the receiver, the analog sensor, and the repeater of FIGS. 1 and 2.

4 is an explanatory diagram showing a format transmitted by the receiver of FIG.

5 is an explanatory diagram showing a format returned by the analog sensor and the relay of FIG.

FIG. 6 is a flowchart for explaining the operation when the sub CPU fails.

FIG. 7 is a block diagram showing a second embodiment.

[Explanation of symbols]

 1: Receiver 2: Display part 3: Acoustic alarm part 4: Operation part 5: Analog sensor 6, 8, 10: Repeater (relay panel) 7: Bell 9: Damper 10: On-off sensor 21: M (main ) -CPU 22, 32: I / O section 23, 33: Program memory 24.34: Serial I / O section 25, 35: Memory section 26, 36: Bus buffer section 37: Transmission interface section 41: Numeric display 42 : Numeric keypad 43: Maintenance mode switch 44: Data memory read switch 45: Data memory write switch SM, S1 to Sn: Switch section 100: M (main) -CPU unit 101 to 10n: S (sub) -CPU unit L1 to Ln : Sensor line L11 to L1n: Transmission line L21 to L2n: Data line B: Bus

Claims (3)

[Claims] 1. One or a plurality of sub CPUs each having a memory for collecting and storing data detected by an analog sensor connected to each sensor line, the sub CPU Alternatively, in a fire alarm device having one main CPU that performs fire alarm control by managing a plurality of sub CPUs, a storage unit that stores collected data stored in a memory of the sub CPU when the sub CPU fails. And a transfer means for transferring the collected data to the memory of the repaired or replaced sub CPU, the fire alarm device. 2. The fire alarm device according to claim 1, wherein the storage means is provided in the main CPU. 3. The fire alarm device according to claim 1, wherein the main CPU and the plurality of sub CPUs are provided in a receiver or a repeater.