JP3236735B2 - Fire alarm - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fire alarm device for detecting a fire by collecting smoke density data and temperature data detected by an analog type smoke sensor and heat sensor, and more particularly to a smoke alarm device and a smoke alarm system. The present invention relates to backup of a memory for storing data.

[0002]

2. Description of the Related Art In general, a fire alarm system of this type collects smoke density and temperature sequentially detected by a smoke sensor and a heat sensor, stores the collected smoke concentration and temperature in a memory, and fires the fire based on the time-series data. Can be detected early. A receiver or a repeater to which this type of sensor is connected is a multi-CPU including a main CPU and a sub CPU provided for each sensor line.
The sub CPU collects data and stores it in the memory.

[0003] These collected data are individual data peculiar to an analog sensor. For example, (1) dirt correction data (2) sensor type data (smoke sensor or heat sensor, etc.) (3) pre-alarm, fire, This is the alarm level for smoke control. (1) The dirt correction data is calculated and stored once a week or once a month from the output value during normal monitoring and the output value during a fire test in order to correct dirt on the sensor. This data varies depending on the monitored area such as a building.

[0004]

However, in the conventional fire alarm system, if the sub CPU breaks down, the collected data in the memory disappears. Therefore, it takes one week to one month to collect the data again. There is a problem that must be. Further, when the failed sub CPU is repaired or replaced, the type data for each analog sensor and the set value of the alarm sensitivity must be downloaded from the main CPU to the sub CPU. Since the entire system including the system has to be reset once and restarted, there is a problem that all the monitoring areas are in an unwatched state during this operation. Of course, even if a fire occurs in an unwatched state, it is not possible to give an alarm. Therefore, during repair and replacement work of the sub CPU, the watcher must monitor the entire monitored area. The reliability is reduced in the case of a building or a building including a plurality of buildings.

In view of the above-mentioned conventional problems, the present invention can save collected data when a sub CPU that collects data from an analog sensor fails, and can reduce an unguarded area. It is intended to provide a fire alarm device.

[0006]

In order to achieve the above object, the present invention is provided for collecting and storing data provided for each sensor line and detected by an analog sensor connected to the sensor line. One or more sub-Cs having
In a fire alarm device having a PU and one main CPU that performs fire alarm control by managing one or a plurality of sub CPUs, when the sub CPU fails, the collected data stored in the memory of the sub CPU is stored. It is characterized by comprising a storage means and a transfer means for transferring the collected data to the memory of the repaired or replaced sub CPU.

The present invention is also characterized in that the storage means is provided in the main CPU. The present invention is also characterized in that a main CPU and a plurality of sub CPUs are provided in a receiver or a repeater.

[0008]

According to the present invention, when a sub-CPU provided for each sensor line fails, the collected data stored in the memory of the sub-CPU is stored in the storage means, saved, and the sub-CPU repaired or replaced is replaced. Since the data is transferred to the memory, the collected data can be stored when the sub CPU that collects data from the analog sensor fails. Further, since the unwatched area is only the area monitored by the failed sub CPU, the unwatched area can be reduced.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing an entire fire alarm device according to the present invention, and FIG. 2 is a block diagram showing the receiver of FIG. 1 in detail. In the example shown in FIGS. 1 and 2, the receiver 1 has an M (main) -CPU unit 100 and an S (sub) -CP provided for each of the sensor lines L1 to Ln.
It is composed of a multi CPU composed of U units 101 to 10n. The receiver 1 also has a display unit 2 for displaying a fire or the like, and an audible alarm unit 3 for giving an alarm with a bell or the like.
And S-CPU unit 1 as will be described later.
An operation unit 4 is provided for performing a memory backup operation when 01 to 10n fails.

Each of the sensor lines L1 to Ln has an analog sensor 5 for detecting smoke density and temperature, a relay 6 for driving an alarm bell 7, and a relay 8 for driving a damper 9. And a repeater 10 for transmitting an alarm signal of the on / off type sensor 11 to the receiver 1 are connected. M
-The CPU unit 100 includes, as shown in detail in FIG.
An M-CPU 21 for controlling the entire system, a display unit 2,
I / O unit 2 for connecting sound alarm unit 3 and operation unit 4
2, a program memory 23, a serial I / O unit 24 for connecting the plurality of S-CPU units 101 to 10n via transmission lines L11 to L1n, and smoke density data collected from the analog sensor 5. A memory unit 25 for storing temperature data is provided, and the members 21 to 25 are connected via a bus B.

The M-CPU unit 100 also stores the smoke density data and temperature data from the analog sensor 5 in the S-C
Data lines L2 from PU units 101 to 10n respectively
A switch unit SM and a bus buffer unit 26 are provided for collecting the data via 1 to L2n and storing the data in the memory unit 25. Furthermore, the S-CPU units 101 to
In order to back up the memory 25 in the event that 10n fails, a three-digit numeric display 41 and a ten-key
, A maintenance mode switch 43, a data memory read switch 43, and a data memory write switch 45.

Each of the S-CPU units 101 to 10n has an I-CPU 31 for connecting the sensor lines L1 to Ln via a transmission interface unit 37.
From the I / O unit 32, the program memory 33, the serial I / O unit 34 for connecting the serial I / O unit 24 of the M-CPU unit 100, and the analog sensors 5 of the sensor lines L1 to Ln. A memory unit 35 for storing collected smoke density data and temperature data is provided, and the members 31 to 36 are connected via a bus B.

Each of the S-CPU units 101 to 10n also has a switch unit S1 to Sn and a bus for transferring data stored in the memory unit 35 to the M-CPU unit 100 via data lines L21 to L2n. A buffer unit 36 is provided, and the switch units S1 to Sn are connected to the memory unit 35.
Can be connected to the data bus B or the bus buffer unit 36.

In such a system, for example, as shown in FIG. 3, the receiver 1 collects terminal information by polling from each of the analog sensor 5 and the repeater 10 to which the on / off type sensor 11 is connected. In order to control the repeaters 6 and 8 to which the alarm bell 7 and the damper 9 are connected, respectively, the analog sensors 5 and the repeaters 6, 8, and 10 are set with individual unique addresses A1, A2. Is done.

The S-CPU units 101 to 101 on the receiver 1 side
The frame format from 10n to the analog sensor 5, the repeaters 6, 8, and 10, for example, as shown in FIG. 4, a command field, an address field and a checksum field of 8 bits each, and are added before these fields. It is composed of a total of 33 bits including a start bit, a parity bit added later, and a stop bit.

Therefore, the S-CPU units 101 to 10n of the receiver 1 set the calling command and the set address for each analog sensor 5, the repeaters 6, 8, and 10 in the command field and the address field, respectively. By sending the signals to the sensor lines L1 to Ln, it is possible to call each analog sensor 5, and each of the repeaters 6, 8, and 10.

On the other hand, the analog sensor 5 and the repeaters 6, 8, and 10 send the S-CPU unit 10 on the receiver 1 side.
The frame format for 1 to 10n includes, for example, a transmission data field and a checksum field each having 8 bits, a start bit added before these fields, a parity bit added after these fields, and a stop bit as shown in FIG. The checksum data is composed of a total of 22 bits, and the checksum data is a value obtained by adding the transmission data and the address of the transmission source.

Therefore, each of the analog sensors 5 and the repeaters 6, 8, and 10 are connected to the S-CPU unit 10 on the receiver 1 side.
In response to the call from 1 to 10n, its own address is sent to the sensor lines L1 to Ln together with the data, and the S-CPU units 101 to 10n of the receiver 1 transmit by subtracting the data from the checksum. The addresses of the analog sensor 5 and the repeaters 6, 8, and 10 can be extracted.

The S-CPU units 101 to 10n
Stores the collected data in the memory unit 35 for each address as (1) stain correction data. The memory unit 35 stores (2) sensor type data (smoke sensor or heat sensor, etc.) from the M-CPU unit 100, and (3) alarm levels such as pre-alarm, fire, smoke prevention and the like. You. In such a configuration, for example, the S-CPU unit 10
If the maintenance mode switch 1 is set to the maintenance mode by the maintenance mode switch 43 of the operation unit 4 as shown in FIG. 6 (step S1), the M-CPU unit 100 stops operating as a normal fire alarm system. And the memory unit 3 on the side of the S-CPU units 101 to 10n.
5, the mode is changed to a mode in which collected data is read out, and a ready state is established. At the same time, the switch unit SM is turned on and the memory unit 25 and the bus buffer unit 25 are connected (Step S).
2).

Next, the ten keys 42 of the operation unit 4
For example, the number “10” of the failed S-CPU unit 101
When "1" is input (step S3), this number "101" is entered.
Is displayed on the numeric display 41 (step S4), and when the data read switch 44 is turned on (step S5), a read command is sent from the M-CPU 21 to the serial I / O unit 24, the transmission line L11, and the S-CPU unit 101. S-CPU 3 via the serial I / O unit 34
1 (step S6).

Next, in the S-CPU unit 101, the switch section S1 switches from the bus B side to the bus buffer 36 side, and the collected data in the memory section 35 is read out, and the switch S1, the bus buffer 36, the data line L21, and the M- C
The data is transferred to the memory unit 25 via the bus buffer 26 and the switch unit SM of the PU unit 100 and is saved (step S7).

After such processing, the failed S
-The board on which the CPU unit 101 is mounted is removed and repaired or replaced (step S8). In addition,
When this board is removed, the power supplied to the S-CPU unit 101 is cut off, so that the data in the memory unit 35 is deleted. Next, when the number "101" of the repaired or replaced S-CPU unit 101 is input by the ten keys 42 (step S9), the number "101" is displayed on the numeric display 41 (step S10), and then the data write switch 45 is turned on (step S11), the write command is
PU21 to serial I / O unit 24, transmission line L11, S
Transmitted to the S-CPU 31 via the serial I / O unit 34 of the CPU unit 101 (step S12).

Next, in the S-CPU unit 101, the switch unit S1 is switched from the bus B side to the bus buffer 36 side, and the data saved in the memory unit 25 of the M-CPU unit 100 is stored in the switch unit SM and the bus buffer 2
6, data line L21, bus buffer 36, switch S1
Is transferred to the memory unit 35 via the controller and returned. When this data transfer is completed, the switch section S1 returns to the bus B side.

Therefore, according to the above embodiment, SC
When the PU units 101 to 10n fail, the collected data of the memory unit 35 is saved in the memory unit 25 of the M-CPU unit 100, so that the collected data can be saved. In addition, during the repair and replacement work of the S-CPU units 101 to 10n, the sub-area monitored by the failed S-CPU unit is only in the unwatched state.
The unguarded area can be reduced.

In the above embodiment, the receiver 1 has the MC
PU unit 100 and S-CPU units 101 to 10
The description has been given of the case where the multi-CPU is composed of multi-CPUs. However, as shown in FIG.
Can also be applied to the case where is configured with multiple CPUs. Note that this configuration can be applied to a system in which, for example, when the guard area is composed of a plurality of buildings, each of the plurality of relay boards 10 manages one building, and the receiver 1 manages all the guard areas. .

[0026]

As described above, the present invention provides one or more memories provided for each sensor line and having a memory for collecting and storing data detected by an analog sensor connected to the sensor line. 1 that performs fire alarm control by managing a plurality of sub CPUs and one or more sub CPUs
In a fire alarm device having two main CPUs, a storage means for storing the collected data stored in the memory of the sub CPU when the sub CPU fails, and a transfer for transferring the collected data to the memory of the repaired or replaced sub CPU. Means, the collected data can be stored when the sub CPU that collects data from the analog sensor fails, and the unmonitored area is the only area monitored by the failed sub CPU, so it is not available. The guard area can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an entire fire alarm device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the receiver of FIG. 1 in detail;

FIG. 3 is a timing chart showing a data transmission sequence of the receiver, the analog sensor, and the repeater of FIGS. 1 and 2;

FIG. 4 is an explanatory diagram showing a format transmitted by the receiver of FIG. 1;

FIG. 5 is an explanatory diagram showing a format returned by the analog sensor and the repeater of FIG. 1;

FIG. 6 is a flowchart for explaining an operation when a sub CPU fails.

FIG. 7 is a block diagram showing a second embodiment.

[Explanation of symbols]

 1: Receiver 2: Display unit 3: Acoustic alarm unit 4: Operation unit 5: Analog detector 6, 8, 10: Repeater (relay panel) 7: Bell 9: Damper 10: On / off detector 21: M (Main) ) -CPU 22, 32: I / O unit 23, 33: Program memory 24.34: Serial I / O unit 25, 35: Memory unit 26, 36: Bus buffer unit 37: Transmission interface unit 41: Numeric display 42 : Ten key 43: maintenance mode switch 44: data memory read switch 45: data memory write switch SM, S1 to Sn: switch unit 100: M (main)-CPU unit 101 to 10 n: S (sub)-CPU unit L1 to Ln : Sensor line L11 to L1n: Transmission line L21 to L2n: Data line B: Bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G08B 17/00 G08B 23/00-31/00

Claims (3)

(57) [Claims] 1. One or more sub-CPUs provided for each sensor line and having a memory for collecting and storing data detected by an analog sensor connected to the sensor line; Alternatively, in a fire alarm device having one main CPU that performs fire alarm control by managing a plurality of sub CPUs, a storage unit that stores collected data stored in a memory of the sub CPU when the sub CPU fails. And a transfer means for transferring the collected data to a repaired or replaced memory of the sub CPU. 2. The fire alarm device according to claim 1, wherein said storage means is provided in said main CPU. 3. The fire alarm device according to claim 1, wherein the main CPU and the plurality of sub CPUs are provided in a receiver or a repeater.