JPH0844660A - Serial bus system - Google Patents

Abstract

PURPOSE:To suppress the increase of cost by reducing the number of parts, reducing the area of a wiring board, miniaturizing and lightening a device and decreasing man-hour for assembly by serially connecting plural pieces of input equipment and plural pieces of output equipment to a control part. CONSTITUTION:As the data input equipment, nXM pieces of sensor units S1-1-SM-n are operated and serially connected (n) by (n), nXm pieces of driver units D1-1-DM-n are operated as the data output equipment and serially connected (n) by (n), and the respective serially connected sensor units S1-1-S1-n and data units D1-1-D1-n or the like are respectively connected to a control part 11 in the shape of a loop. The data of sensors held at respective sensor units S1-1-SM-n are shifted and transferred to the control part 11 synchronously with a clock signal CLK supplied from the control part 11. The data for driver outputted from the control part 11 are successively shifted and supplied to the respective driver units D1-1-DM-n synchronously with the clock signal CLK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system for transmitting data between a plurality of input / output devices and a microcomputer in synchronization with pulse signals, and particularly to input / output devices having equivalent functions. The present invention relates to a serial bus system applied to a device that uses a lot of devices.

[0002]

2. Description of the Related Art For example, a copying machine or a vending machine has a plurality of input / output devices including sensors and motor drivers. When exchanging data between these input / output devices and a microcomputer, parallel data communication is used. That is, as shown in FIG. 14, the microcomputer 91 includes a plurality of data input ports Din, data output port Dout, power port Vcc, has a ground port GND, the sensors 92 _1, 92 ₂ ~92 _n one Data input port Din, power supply port Vcc, ground port G
The drivers 93 ₁ , 93 _{2 to} 93 _n are connected to ND, and are connected to a set of data output port Dout, power supply port Vcc, and ground port GND. The microcomputer 91 arbitrarily designates the data input port Din and the data output port Dout to perform parallel data communication with a sensor or a driver and read data from the sensor.
Writing data to the driver.

[0003]

By the way, in the case of the above-mentioned conventional parallel data communication, the microcomputer 91 is used.
Requires a number of data input ports Din, data output ports Dout, power supply ports Vcc, and ground ports GND corresponding to the number of sensors and drivers. Therefore, when the number of sensors and drivers increases, a huge amount of wirings and connectors are required to connect the sensors and drivers to each port. Copiers and vending machines require large numbers of sensors and drivers. Therefore, the number of parts increases,
Since the area of the wiring board is enlarged, it is difficult to reduce the size and weight of the device, and the number of assembling steps is increased, which makes it difficult to suppress the cost increase.

The present invention is intended to solve the above problems. An object of the present invention is to reduce the number of parts, reduce the area of a wiring board, and reduce the size and weight of the device. An object of the present invention is to provide a serial bus system capable of reducing the number of assembling steps and suppressing the cost increase.

[0005]

SUMMARY OF THE INVENTION According to the present invention, a plurality of input devices for inputting data are connected in series, and the input data is sequentially shifted to each input device according to a clock signal, and the input device is located at one end. The input device group that outputs the shifted data from the above and a plurality of output devices that output the data are connected in series, and the data to be output input to the output device located at one end according to the clock signal An output device group that sequentially shifts to, an input port that supplies the clock signal to the input device group and the output device group, and sequentially inputs data output from the input device located at one end of the input device group, And a control unit having an output port for sequentially supplying the data to be output to an output device located at one end of the output device group.

The input device located at one end of the input device group is connected to the first input port of the control unit, and the input device located at the other end is connected to the second output port of the control unit. . The output device located at one end of the output device group is connected to the first output port of the control unit, and the output device located at the other end is connected to the second input port of the control unit. That is, the input device group and the output device group are connected to the control unit in a loop.

Furthermore, each input device and each output device has a bidirectional buffer capable of bidirectionally transferring data, and the input device group and the output device group are located at one end and the input device and the output device are the control unit. It is connected to the I / O port.

[0008]

That is, in the present invention, the plurality of input devices and the plurality of output devices are serially connected to the control unit. Therefore, the wiring can be reduced as compared with the case where the devices are connected in parallel as in the conventional case, and the size of the device can be reduced.
The weight can be reduced.

The control unit transmits data to the input device and the output device located at one end of the input device group and the output device group, and the input device and the output located at the other end of the input device group and the output device group. By receiving the transmitted data output from the device in the control unit and comparing the transmitted data with the received data, it is possible to detect the presence / absence of disconnection in the input device group and the output device group.

Furthermore, by providing the input device and the output device with the bidirectional buffer, the wiring can be further reduced and the location of the disconnection of the input device group and the output device group can be detected. That is, first, the bidirectional buffer is set to the receiving state, and the control unit transmits data to the input device and the output device located at one end of the input device group and the output device group
Data is sequentially shifted to the input device and the output device located at the other end. After this, set the bidirectional buffer to the transmission state,
The control unit receives data sequentially output from the input device and the output device located at one end of the input device group and the output device group. When the input device group and the output device group have disconnection, the data is normally transferred up to the point before the disconnection point. Therefore, it is possible to compare the transmission data and the reception data and detect the disconnection points of the input device group and the output device group from the disagreement points of these data.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In the figure, the control unit 11 is composed of, for example, a microcomputer as described later, and is connected to a main body device (not shown) such as a copying machine or a vending machine to which this serial bus system is applied. This control unit 11 has M channel data input ports Din1 and Din.
2 and data output ports Dout1 and Dout2, and outputs a clock signal CLK for M channels, a port for outputting a power supply Vcc, a port for outputting a ground potential GND, and a set signal SET for M channels described later. Has a port for outputting.

N × M sensor units S1-1 to SM
-N operates as a data input device and has a function of detecting and holding required data, for example. These sensor units are connected in series by n units each. That is, n sensor units S1-1 and S1-2 connected in series are connected.
-S1-n, the sensor unit S1-1 is the wiring L1.
Sensor units SM-1, SM-2 to SM connected in series to the data input port Din1
-N, the sensor unit SM-1 is connected to the data input port Din1 via the wiring L1M. In addition, the n sensor units S1− connected in series are connected.
1, S1-2 to S1-n, the sensor unit S1-
n is connected to the data output port Dout1 via a line L21 and is connected in series to the sensor unit SM-
1, SM-2 to SM-n, the sensor unit SM-
n is connected to the data output port Dout1 via the line L2M.

The n × M driver units operate as a data output device and have a function of holding data for driving a motor, for example. Each driver unit is connected in series by n units. That is, n driver units D1-1, D1-2 to D1- connected in series are connected.
Of the n, the driver unit D1-1 is connected to the data output port Dout2 via the line L31, and is connected in series to the driver units DM-1, DM-2 to DM-n.
Among them, the driver unit DM-1 is connected to the data output port Dout2 via the wiring L3M. Also, the n driver units D1− connected in series are connected.
Driver unit D1 among D1, D1-2 to D1-n
-N is the data input port Din2 via the wiring L41
Driver unit DM connected in series and connected in series
-1, DM-2 to DM-n, the driver unit D
M-n is the data input port Din via the wiring L4M
Connected to 2.

Each of the driver units D1-n to DM-
The set signal SET is supplied to n. Furthermore, each of the sensor units S1-1 to SM-
n and each driver unit D1-n to DM-n,
Clock signal line C connected to the port of the control unit 11
LK, the power supply line Vcc, and the ground line GND are connected.

In the above structure, a schematic operation will be described. Each sensor unit holds the detected data in a latch circuit (not shown). The data held in each sensor unit is sequentially shifted to the sensor unit of the next stage in synchronization with the clock signal CLK supplied from the control unit 11, and transferred to the data input port Din1 of the control unit 11. Therefore, the control unit 11 outputs n clock signals to C
N connected in one loop by sending LK
Data can be read from the individual sensor units.

When setting data in n driver units connected in one loop, the control section 11 outputs the data from the data output port Dout2 in synchronization with the clock signal CLK. The data output from the data output port Dout2 is sequentially shifted to each driver unit according to the clock signal CLK. When the data is shifted to the n driver units, the control unit 11 outputs the set signal SET, and each driver unit latches the data according to the set signal SET.

On the other hand, in the case of this embodiment, the disconnection of each loop can be checked. For example, the sensor unit S
When checking the disconnection of the loop including 1-1 to S1-n, the control unit 11 outputs preset check data, for example, AA (H) from the data output port Dout1 in synchronization with the clock signal CLK. This check data is sequentially sent to the sensor units S1-n to S1 via the wiring L21.
It is shifted to -1 and further supplied to the data input port Din1 of the control section 11 via the line L11. Control unit 1
1 compares the check data received at the data input port Din1 with the preset check data, and if they match, it is determined that there is no disconnection. Also, if there is a break in the loop, the check data will not be shifted normally. Therefore, the data received at the data input port Din1 does not match the preset check data. Therefore, the control unit 11 can recognize that there is a disconnection in this loop.

Similarly, it is possible to check the disconnection of the loop including the driver unit. That is, by outputting check data from the data output port Dout2 and comparing the data received at the data input port Din2 with the check data, it is possible to check the presence or absence of disconnection of each loop including the driver unit.

FIG. 2 shows the sensor unit. Since all sensor units have the same configuration,
The sensor unit S1-1 will be described. The sensor unit includes a sensor 21 and a logic unit 22. The sensor 21 and the logic unit 22 have a power supply V
cc and ground potential GND are supplied. Further, the clock signal CLK is supplied to the logic unit 22.
In the logic unit 22, the sequence generator 23
As will be described later, sets the output signal A to the low level when the first clock signal is supplied, and sets the output signal A to the high level when counting the number of sensor units in one loop, that is, n clock signals CLK. Level. This output signal A is supplied to the transfer gates 24 and 25. The input end of the transfer gate 24, that is, the data input end Din of the sensor unit S1-1 is connected to the output end of the subsequent sensor unit S1-2, and the output end is connected to the input end D of the flip-flop circuit 26. There is.
The clock signal input terminal C of this flip-flop circuit 26
The clock signal CLK is supplied to K, and the output end Q is the data output end Dout of the sensor unit S1-1. The output signal of the sensor 21 is supplied to the input end of the transfer gate 25. The output end of the transfer gate 25 is connected to the input end D of the flip-flop circuit 26.

FIG. 3 shows the operation of the sensor unit S1-1. The output signal A of the sequence generator 23 is normally at low level. Therefore, the transfer gate 24 is in the off state and the transfer gate 25 is in the on state.
The output signal of the sensor 21 is supplied to the input terminal D of 6.

In this state, when the clock signal CLK is output from the control unit 11, the flip-flop circuit 2
Reference numeral 6 holds the output signal of the sensor 21 in synchronization with the falling edge of the first clock signal CLK. Therefore, the output signal of the flip-flop circuit 26 becomes the output signal of the sensor 21. The sequence generator 23 sets the output signal A to the high level in synchronization with the rising of the first clock signal CLK. Therefore, the transfer gate 2
4, the transfer gate 25 is turned on, the transfer gate 25 is turned off, and the output signal of the sensor unit S1-2 at the subsequent stage is supplied to the input terminal D of the flip-flop circuit 26. The flip-flop circuit 26 holds the output signal of the sensor unit S1-2 at the subsequent stage in synchronization with the falling edge of the second clock signal CLK. After that, the output signals of the sensor unit S1-2 at the subsequent stage are sequentially held in synchronization with the falling edge of the clock signal. That is, the subsequent sensor unit S1-
The data of 2 to S1-n are sequentially shifted. The sequence generator 23 sets the output signal A to the low level when counting the n clock signals CLK, and the sensor 21
The output signal of can be input.

Each sensor unit in one loop performs the same operation as described above in synchronization with the clock signal CLK. Therefore, when the output signal A of the sequence generator 23 is at a high level, the data of each sensor unit is shifted in synchronization with the clock signal CLK and transferred to the control unit 11.

The disconnection check described above is executed, for example, immediately after the power is turned on. That is, the sequence generator 23 is set so that the output signal A does not become a low level while a predetermined number of clock signals are supplied after the power is turned on, and during this period, each sensor unit is output from the control unit 11. Check data is transferred in synchronization with a clock signal.

FIG. 4 shows the driver unit. Since the driver units have the same configuration, the driver unit D1-1 will be described. This driver unit drives, for example, a four-phase pulse motor, and is mainly composed of a shift register 31, a sequence generator 32, a first latch circuit 33, and a second latch circuit 34. The shift register 31 is composed of a plurality of flip-flop circuits 31a to 31f that shift the signal output from the control unit 11 in synchronization with the clock signal CLK, and the input end of the flip-flop circuit 31a is a data input end Din. The output terminal Q of the flip-flop circuit 31f is the data output terminal DOU.
It is T. The sequence generator 32 latches the latch signal B every time it counts four clock signals CLK.
CQ is output and reset according to the set signal SET. The first latch circuit 33 has four
Each of the flip-flop circuits 31a to 31a, which are composed of a plurality of flip-flop circuits 33a, are provided in response to a latch signal BCQ output from the sequence generator 32.
The output signal of 31d is latched. The second latch circuit 34 is composed of four flip-flop circuits 33a, and latches the signal held in the first latch circuit 33 according to the set signal SET. The signal held in the second latch circuit 34 is supplied to the output stage circuit (not shown), and the output stage circuit drives the motor (not shown).

An overcurrent detector (OCD) 35 and an overheat detector (TS) provided in a pulse motor (not shown)
The output signal of D) 36 is supplied to the flip-flop circuits 31e and 31f through gates 37 and 38. Therefore, the output signals of the OCD 35 and TSD 36 can be transferred to the control unit 11.

FIG. 5 shows the structure of the control unit 11. The microcomputer 41 performs overall control. The microcomputer 41 includes serial input / output control units (SIOC) 42 _{1 to} 42 _M , 43 ₁
~ 43 _M are connected. These serial input / output control units 42 _{1 to} 42 _M and 43 ₁ to 43 _M include a logic circuit having a normal SIO function and a frame control function described later.

The serial input / output control units 42 _{1 to} 42 _M control the sensor unit, and each serial input / output control unit 42 _{1 to} 42 _M respectively receives the clock signal CL.
Outputs K1 to CLKM. Each serial input / output control unit 4
2 ₁ through 42 _M are transmitting buffer T which holds transmission data
Data output port D via xBUF1 to TxBUFM
It is connected to out1 and is connected to the data input port Din1 via reception buffers RxBUF1 to RxBUFM that hold received data. Comparison circuits CMP1 to CMPM are connected to the respective transmission buffers and reception buffers. These comparison circuits CMP1 to CMPM compare the transmission data and the reception data during the disconnection check. Each of the comparison circuits CMP1 to CMPM includes the serial input / output control unit 4
2 _1-42 are connected to _M, each comparison circuit CMP1~
The comparison result output from the CMPM is supplied to the microcomputer 41 via the serial input / output control units 42 _{1 to} 42 _M.

Further, serial input / output control units 43 ₁ to 43
_M controls the driver unit, and each of the serial input / output control units 43 ₁ to 43 _M has clock signals CLK1 to CLKM and set signals SET1 to S, respectively.
Output ETM. Each serial input / output control unit 43 ₁ to 4
3 _M is a transmission buffer TxBUF that holds transmission data
1 to TxBUFM connected to the data output port Dout2, the receiving buffer RxBU for holding the received data
It is connected to the data input port Din2 via F1 to RxBUFM. Comparison circuits CMP1 to CMPM are connected to the respective transmission buffers and reception buffers. These comparison circuits CMP1 to CMPM compare the transmission data and the reception data during the disconnection check. Each comparison circuit CMP
₁ to CMPM are the serial input / output control units 43 ₁ to 4
It is connected to 3 _M and each comparison circuit CMP1 to CMPM
The comparison result output from the serial input / output control unit 43 ₁
˜43 _M to the microcomputer 41.

FIG. 6 shows the operation of the driver unit. As shown in FIG. 6A, this driver unit has a UDM mode (Undefined Mode) in which it is latched in the second latch circuit 34 without confirming the authenticity of the data transferred from the control unit 11 to the driver unit. ,
As shown in FIGS. 6B and 6C, the authenticity of the data transferred from the control unit 11 to the driver unit is confirmed, and if the data is transferred correctly, the data is latched in the second latch circuit 34. DDM mode (Data Defined Mod
e) and.

In the case of the UDM mode shown in FIG. 6A, when the microcomputer 41 receives a data transmission request from the main unit to the driver unit, for example, the transmission buffer TxBU is sent via the serial input / output control unit 43 _1.
Data is set in F1 and transmission of the clock signal is started. The sequence generator for each driver unit
After the clock signals corresponding to the number of stages of the driver units are transmitted, the latch signal BCQ is activated. Therefore, each driver unit simultaneously holds the data in the first latch 33. Immediately after this, the serial input / output control unit 43
₁ outputs the set signal SET for one clock. Therefore, the data held in the first latch 33 is held in the second latch circuit 34. After that, by repeating this operation, the motor (not shown) is driven. The process from the sending of the data to the holding of the data by the second latch circuit 34 is called one frame.

On the other hand, in the DDM mode shown in FIG. 6B, the operation until the latch signal BCQ is activated and the data is held in the first latch 33 is the same as in the UDM mode. After that, the serial input / output control unit 43 ₁ again sends the clock signals for the number of stages of the driver unit, and the sent data is taken into the receiving RxBUF1. The comparison circuit CMP1 compares the data fetched in the reception RxBUF1 with the data set in the transmission buffer TxBUF1. Comparison circuit CMP1
The comparison result output from the serial input / output control unit 43 ₁
Is supplied to the microcomputer 41 via this, and when it is determined from the result of this comparison that the two data match, a set signal SET is sent from the microcomputer 41. The set signal SET is supplied to each driver unit via the serial input / output control unit 43 ₁ , and in each driver unit, the data held in the first latch 33 is held in the second latch circuit 34.

By the above operation, the data can be transmitted from the control unit 11 to each driver unit while checking the disconnection and confirming the data. Note that FIG.
It shows a case where the operation shown in (b) is continuously performed.

According to the first embodiment, the plurality of sensor units and the plurality of driver units are serially connected to the control unit 11. For this reason, the control unit does not need the same number of input / output ports as the number of sensor units and driver units as in the conventional case, and may have the same number of input / output ports as the number of loops. Moreover, the number of power supply ports is not the same as the number of sensor units and driver units. Therefore, wiring can be significantly reduced as compared with the related art, so that the size and weight of the device can be reduced, and the number of manufacturing steps can be reduced, so that the cost can be reduced.

Further, the control unit 11 receives the data transmitted from the control unit 11 to one loop including a plurality of sensor units and driver units, and compares the transmitted data with the received data, thereby disconnecting the loop. You can check the failure location. Therefore, maintenance and inspection can be easily performed in an apparatus using a large number of sensor units and driver units.

Next, a second embodiment of the present invention will be described. In the first embodiment, a plurality of sensor units and driver units are connected to the control unit 11 in a loop. On the other hand, in this embodiment, a plurality of sensor units and driver units are openly connected to the control unit.

FIG. 7 shows a second embodiment.
The control unit 51 is composed of, for example, a microcomputer as will be described later, and is connected to a main body device (not shown) such as a copying machine or a vending machine to which the serial bus system is applied. The control unit 51 includes data input / output ports Sio1 and S for M channels to which the sensor unit is connected.
io2 to SioM, and data input / output ports Dio1 for M channels to which the driver unit is connected,
It has Dio2 to DioM. Further, the control unit 51 outputs the clock signal CLK to the sensor unit, the M channel port to output the power supply Vcc, the M channel port to output the ground potential GND, and the clock signal to the driver unit. Port for M channels that outputs CLK, M that outputs power supply Vcc
It has ports for channels, ports for M channels that outputs the ground potential GND, and ports for M channels that outputs the set signal SET.

N × M sensor units SN1-1 to S
The NM-n operates as a data input device and has, for example, a function of detecting and holding required data and a function of bidirectionally transferring data. These sensor units are n
They are connected in series one by one. That is, n sensor units SN1-1, SN1-2 to SN1 connected in series are connected.
-N, the sensor unit SN1-1 is connected to the data input / output port Sio1 via the wiring L11, and n sensor units SN2-1 and SN2- are connected in series.
Among the units 2 to SN2-n, the sensor unit SN2-1 is connected to the data input / output port Sio2 via the line L12. Further, the sensor units S connected in series
Among the NM-1, SNM-2 to SNM-n, the sensor unit SNM-1 is connected to the data input / output port SioM via the wiring L1M.

The n × M driver units operate as a data output device, and have a function of holding data for driving a motor and a function of bidirectionally transferring data, for example. Each driver unit is connected in series by n units. That is, of the n driver units DR1-1, DR1-2 to DR1-n connected in series,
The driver unit DR1-1 is connected to the data input / output port Dio1 via a line L21, and n driver units DR2-1, DR2-2 to DR2 connected in series are connected.
Of the 2-n, the driver unit DR2-1 has the wiring L2.
2 is connected to the data input / output port Dio2. Further, the driver units DRM connected in series
-1, DRM-2 to DRM-n, the driver unit DRM-1 is connected to the data input / output port DioM via the line L2M.

Each of the driver units DR1-n to DR
The set signal SET is supplied to M-n. Furthermore, each of the sensor units SN1-1 to SNM-n and each of the driver units DR1-n to DR.
A clock signal CLK output from each port of the control unit 51, a power supply Vcc, and a ground GND are supplied to Mn.

Various configurations of each data input / output port of the control unit 51 are conceivable. For example, a transmission data and a reception data are provided separately, and the above-mentioned transmission buffer and reception buffer are connected to this gate, The comparison circuit may be connected to the transmission buffer and the reception buffer. According to such a configuration, the disconnection check can be performed using the output signal of the comparison circuit.

In the above structure, a schematic operation will be described. In the normal mode, the bidirectional buffer of each sensor unit is set to the output state, and the bidirectional buffer of each driver unit is set to the input state. The data of each sensor unit is sequentially transferred to the control unit 51 according to the clock signal output from the control unit 51. Also,
The data output from the control unit 51 is sequentially transferred to each driver unit according to the clock signal.

Further, when performing the disconnection check, first,
Each bidirectional buffer is put in an input state, and the check data output from the control unit 51 is transferred to each sensor unit and driver unit. After the transfer of the check data is completed, the bidirectional buffer is set to the output state, and the check data is transferred from each sensor unit and the driver unit to the control unit 51. The control unit 51 compares the transmitted data with the received data and detects a disconnection point.
That is, even if there is a disconnection point, the control unit 51
To the sensor unit and the driver unit in front of the disconnection point, the check data can be normally transferred. Therefore, the disconnection point can be detected by detecting the abnormal point of the check data from the comparison result.

FIG. 8 shows an example of the sensor unit SN1-1. In this sensor unit SN1-1, the same parts as those of the sensor unit S1-1 are designated by the same reference numerals, and only different parts will be described.

The sensor unit SN1-1 differs from the sensor unit S1-1 in that it has a bidirectional buffer 61 and a direction control section 62. The bidirectional buffer 61 is composed of buffers 63 to 68. The input ends of the buffers 63 and 64 and the output end of the buffer 65 are connected to the data input / output port Sio1 of the control unit 51. The output ends of the buffers 66 and 67, and the buffer 6
The input ends of 8 are connected to the adjacent sensor units SN1-2. The output end of the buffer 63 is a buffer 66.
The input end of the buffer 64 is connected to the input end of the transfer gate 24, the output end of the buffer 68, and the direction controller 62. The input terminal of the buffer 65 is connected to the input terminal of the buffer 67 and the output terminal Q of the flip-flop circuit 26.

The signal SA output from the sequence generator 69 is the buffer 6 of the bidirectional buffer 61.
3, 66, the inverter circuit 73, and the direction control unit 62. The direction control unit 62 determines the normal mode and the disconnection check mode from the clock signal CLK and the data DT supplied from the buffer 63, and controls the data transfer direction. The direction control unit 62 outputs an output signal SB for setting the direction of the bidirectional buffer 61.

The output signal SB is supplied to the inverter circuit 7
It is supplied to one input terminal of the AND circuit 71 via 0 and is supplied to one input terminal of the AND circuit 72. The output signal SA is supplied to the other input ends of the AND circuits 71 and 72 via an inverter circuit 73. The output signal of the AND circuit 71 is the buffer 6
5 and 68, and the output signal of the AND circuit 72 is supplied to the buffers 64 and 67.

In the above structure, the bidirectional buffer 61 has the buffer 6 when the output signal SA of the sequence generator 69 is low level and the output signal SB is high level.
4, 67 become active and enter the input state. Therefore, the data can be transferred from the control unit 51 to the sensor unit side. When the output signal SA is low level and the output signal SB is low level, the buffers 65 and 68 are active and the bidirectional buffer 61 is in the output state. Therefore, the data can be transferred from the sensor unit to the control unit 51 side. When the output signal SA is at high level, the buffers 63 and 66 are active and the bidirectional buffer 61 is in the through state. Therefore, the data sent from the control unit 51 can be transferred to the sensor unit in the subsequent stage. In the case of this through state, data can be collectively transferred to a plurality of sensor units connected in series.

FIG. 9 shows a main part of the sequence generator 69, and shows a configuration for generating the signal SA. The sequence generator 69 includes n stages of flip-flop circuits 69 ₁ to
69 _n and a flip-flop circuit 69 _{n + 1} for discriminating whether the output signal of the counter is high level or low level. That is, the clock signal CLK is supplied to the clock signal input terminal CK of the flip-flop circuit 69 ₁ . The inverted output terminal / Q (indicating an inverted signal) of each flip-flop circuit is connected to each data input terminal D and also to the clock signal input terminal CK of the next-stage flip-flop circuit. Inverting output terminal / Q of the flip-flop circuit 69 ₁ is connected to an input terminal of the NAND circuit 74 along with the inverted output terminal / Q of the flip-flop circuit 69 n _{+ 1,}
The output terminal of the NAND circuit 74 is the flip-flop circuit 6
It is connected to the reset signal input terminal R of 9 _{n + 1} . The signal S is output from the output terminal Q of the flip-flop circuit 69 _{n + 1.}
A is output.

The flip-flop circuits 69 _{1 to} 69 _n forming the counter may be reset by the set signal SET output from the control unit 51, for example. By forcibly resetting the counter in this way, it is possible to prevent malfunction of the counter due to noise and prevent changes in the protocol of communication data.

The resetting means of the counter is not limited to the set signal SET, but for example, the control unit 51 outputs a clear code combining a clock signal and data, and the sequence generator detects the clear code. The counter may be cleared by the detection output signal.

FIG. 10 shows the direction control section 62. In FIG. 10, the output signal SA of the sequence generator 69 is connected to the input terminal of the AND circuit 62a,
And a clock signal CLK. The output signal of the AND circuit 62a is supplied to the clock signal input terminal CK of the flip-flop circuit 62b. The data DT is connected to the data input terminal D of the flip-flop circuit 62b.
Is supplied. The inverting output terminal / Q of the flip-flop circuit 62b is connected to the data input terminal D of the flip-flop circuit 62c and the flip-flop circuit 62d. A clock signal CLK is supplied to a clock signal input terminal CK of the flip-flop circuit 62c,
The signal SB is output from the output terminal Q of the flip-flop circuit 62c.

The clock signal CLK is supplied to the clock signal input terminal CK of the flip-flop circuit 62d, and the output terminal Q of the flip-flop circuit 62d is connected to the data input terminal D of the flip-flop circuit 62e. , OR circuit 62f is connected to one input end. The clock signal CLK is supplied to the clock signal input terminal CK of the flip-flop circuit 62e, and the output terminal Q of the flip-flop circuit 62e is connected to the OR circuit 6.
It is connected to the other input terminal of 2f. This OR circuit 62
The output terminal of f is connected to the clock signal input terminal CK of the flip-flop circuit 62g. The data input terminal D of the flip-flop circuit 62g is grounded, and the clock signal CLK is supplied to the reset terminal PR. The output terminal Q of the flip-flop circuit 62g is connected to the reset terminal PR of the flip-flop circuit 62c.

The operation of the sensor unit SN1-1 shown in FIGS. 8 to 10 in the above structure will be described. FIG. 11 shows the operation of the sensor unit SN1-1 in the normal mode.

In the sequence generator 69 shown in FIG. 9, n-stage flip-flop circuits 69 _{1 to} 69 _{n are provided.}
Is reset by a power-on reset circuit (not shown) when the device is powered on, and each output terminal / Q is set to low level. In addition, the flip-flop circuit 69 _{n + 1}
Since the output terminal Q of the signal becomes high level, the signal SA becomes high level. When the signal SA is at high level, it indicates that the output terminals / Q of the flip-flop circuits 69 _{1 to} 69 _n are all at low level.

[0055] In this state, is supplied the clock signal CLK to the flip-flop circuit 69 _1, the inverted output terminal / Q of the flip-flop circuit 69 ₁ is at high level, the output signal of the NAND circuit 74 becomes high level, the flip-flop The output terminal Q of the circuit 69 _{n + 1} , that is, the signal SA becomes low level. Sequence generator 69
After that, when the clock signal is sequentially supplied and the inverting output terminal / Q of the flip-flop circuit 69 _n falls, the output terminal Q of the flip-flop circuit 69 _{n + 1} responds to this.
That is, the signal SA changes from low level to high level.

On the other hand, in the direction control unit 62 shown in FIG. 10, the states of the respective flip-flop circuits after power-on reset are as follows. That is, the inverting output terminal / Q of the flip-flop circuit 62b is high level or low level, the output terminal Q of the flip-flop circuits 62c and 62g is high level, and the flip-flop circuits 62d and 62g.
The output terminal Q of e is at low level.

As described above, the flip-flop circuit 62
The output terminal Q of c, that is, the output signal SB is at a high level. However, the output signal SA of the sequence generator 69 is also at high level. Therefore, in the initial state, the bidirectional buffer 61 is in the through state, and the data output from the control unit 51 can be transferred to the sensor unit in the subsequent stage.

In the above state, the high-level data D corresponding to the first clock signal CLK from the control unit 51.
T is output. Then, the output signal SA of the sequence generator 69 becomes low level as described above according to the first clock signal CLK. At this time, in the direction control unit 62, the flip-flop circuit 62b outputs the high-level data DT according to the output signal of the AND circuit 62a.
Is latched, and its inverting output terminal / Q becomes low level.
Therefore, the flip-flop circuit 62c latches a low-level signal in accordance with the clock signal, and its output terminal Q,
That is, the output signal SB becomes low level. Therefore, the bidirectional buffer 61 is in the output state, and the sensor 21
The data taken in by the flip-flop circuit 26 can be output to the control unit 51. In this state, the data taken into the flip-flop circuit 26 of each sensor unit is sequentially shifted in synchronization with the clock signal and transferred to the control unit 51. After that, when the data of all the sensor units connected in series are transferred to the control unit 51, the output signal SA of the sequence generator 69 becomes high level. Therefore, the bidirectional buffer 61 becomes the through state again. At this time, each output signal SB of the direction control unit 62
Remains low.

FIG. 12 shows the operation in the disconnection check mode. The initial state is similar to the normal mode. That is, the output signal SA of the sequence generator 69,
Also, each output signal SB of the direction control unit 62 is at a high level. Therefore, the bidirectional buffer 61 is in the through state.

In this state, the control unit 51 outputs the low level data DT indicating the disconnection check mode in response to the first clock signal. Therefore, even if the output signal SA of the sequence generator 69 becomes low level, the inverted output / Q of the flip-flop circuit 62b maintains the high level, and the flip-flop circuit 62 is kept.
The output signal SB of c remains high level. Therefore, the bidirectional buffer 61 is in the input state and the control unit 51
The check data output from, for example AA (H),
It is transferred to each sensor unit in synchronization with the clock signal.

When the clock signal CLK and the check data are output for the sensor units connected in series, the counter of the sequence generator 69 becomes all "0", and the output signal SA of the sequence generator 69 becomes high level. After that, when the flip-flop circuit 62b latches the high-level data DT according to the next clock signal, the flip-flop circuit 62c latches the low-level signal output from the inverting output terminal / Q of the flip-flop circuit 62b. To do. Therefore, the output signal SB of the flip-flop circuit 62c becomes low level. Therefore, the bidirectional buffer 61 is put in the output state, and the check data transferred to each sensor unit is transferred to the control unit 51 according to the clock signal. The control unit 51 compares the received check data with the transmitted check data, and determines the non-coincidence portion of the check data to determine the disconnection portion.

FIG. 13 shows the driver unit D shown in FIG.
This is an example of R1-1, the same parts as those in FIGS. 4 and 8 are denoted by the same reference numerals, and only different parts will be described. The driver unit DR1-1 is further provided with a bidirectional buffer 61 and a direction control unit 62.
That is, the data input terminal D of the flip-flop circuit 31 a that constitutes the shift register 31 is connected to the output terminals of the buffers 63, 64 and 68 that constitute the bidirectional buffer 61, and the input terminal of the buffer 66. Further, input terminals of buffers 65 and 67 forming the bidirectional buffer 61 are connected to the data output terminal Q of the flip-flop circuit 31f forming the shift register 31.
The output signal SA of the sequence generator 32 is supplied to the buffers 63 and 66 forming the bidirectional buffer 61, and also to the direction control unit 62 and the inverter circuit 73.

In the normal mode, the driver unit DR1-1 is operated by the direction control unit 62 to allow the bidirectional buffer 61 to operate.
Is set to the input state, and the data is sequentially transferred to the shift register 31 via the bidirectional buffer 61.

In addition, at the time of checking disconnection, the bidirectional buffer 6
1 is set to the input state, and the check data output from the control unit 51 is sequentially transferred to the driver unit in the subsequent stage via the shift register 31. When the transfer of the check data is completed, the bidirectional buffer 61 is set to the output state,
The check data is synchronized with the clock signal by the control unit 5
Forwarded to 1.

According to the second embodiment, one ends of a plurality of sensor units and driver units connected in series are connected to the control section 51, and not in the loop shape as in the first embodiment. Therefore, it is possible to reduce the wiring for connecting the control unit 51 to the sensor unit and the driver unit, and to further reduce the size of the device as compared with the first embodiment.
The weight can be reduced.

Further, each sensor unit and driver unit has a bidirectional buffer. Therefore, the data output from the control unit 51 can be transferred to each sensor unit and the driver unit, and the data output from each sensor unit and the driver unit can be transferred to the control unit 51.

Further, when the disconnection check is performed, first,
The check data output from the control unit 51 with the bidirectional buffer in the input state is transferred to each sensor unit and the driver unit, and after the transfer of the check data is completed, the bidirectional buffer is set in the output state and the sensor unit and the driver unit output The check data is transferred to the control unit 51, and the control unit 51 compares the transmitted data with the received data. Therefore, by detecting the abnormal portion of the check data from the comparison result, the disconnection portion can be easily detected. Therefore, it is possible to easily inspect and maintain a device using a large number of sensor units and driver units.

The configurations of the sequence generator shown in FIG. 9 and the direction control unit shown in FIG. 10 are examples, and the present invention is not limited to these configurations. Of course, various modifications can be made without departing from the scope of the invention.

[0069]

As described above in detail, according to the present invention, the number of parts can be reduced and the area of the wiring board can be reduced.
It is possible to provide a serial bus system capable of reducing the size and weight of the device, reducing the number of assembling steps, and suppressing soaring costs.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of the sensor unit shown in FIG.

FIG. 3 is a timing chart showing the operation of FIG.

FIG. 4 is a circuit diagram showing an example of a driver unit shown in FIG.

5 is a configuration diagram showing an example of a control unit shown in FIG.

FIG. 6 is a timing chart showing the operation of FIG.

FIG. 7 is a configuration diagram showing a second embodiment of the present invention.

8 is a circuit diagram showing an example of the sensor unit shown in FIG.

9 is a circuit diagram showing a part of FIG. 7. FIG.

FIG. 10 is a circuit diagram showing a part of FIG. 7.

11 is a timing chart showing the operation in the normal mode of FIG.

12 is a timing chart showing the operation of the disconnection check mode of FIG.

13 is a circuit diagram showing an example of a driver unit shown in FIG.

FIG. 14 is a configuration diagram showing a conventional bus system.

[Explanation of symbols]

11 ... Control unit, Din1, Din2 ... Data input port, D
out1, Dout2 ... Data output port, S1-1 to SM-n
... sensor unit, D1-1 to DM-n ... driver unit, 21 ... sensor, 23, 32 ... sequence generator, 24, 25 ... transfer gate, 26 ... flip-flop circuit, 31 ... shift register, 33, 34
... first, second latch circuit, 41 ... microcomputer, 42 ₁ through 42 _M ... serial input-output control unit, TxBU
F1 to TxBUFM ... Transmission buffer, RxBUF1 to
RxBUFM ... Receiving buffer, CMP1-CMPM ...
Comparison circuit.

Front page continuation (72) Inventor Toshiyuki Shinoda 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Co., Ltd.

Claims (11)

[Claims] 1. A plurality of input devices for inputting data are connected in series, the input data is sequentially shifted to each input device according to a clock signal, and the shifted data is output from the input device located at one end. An input device group and a plurality of output devices that output data are connected in series, and an output device group that sequentially shifts the data to be output input to the output device located at one end according to the clock signal to each output device. An input port for supplying the clock signal to the input device group and the output device group and sequentially inputting data output from the input device located at one end of the input device group, and one end of the output device group And a control unit having an output port for sequentially supplying the data to be output to the output device located at. 2. A plurality of input devices for inputting data are connected in series, the input data is sequentially shifted to each input device according to a clock signal, and the shifted data is output from the input device located at one end. In addition, an input device group that sequentially inputs disconnection check data in accordance with a clock signal from an input device located at the other end, and sequentially outputs the disconnection check data from the input device located at one end, and a data Output devices are connected in series, and the data to be output or the data for disconnection check supplied to the output device located at one end according to the clock signal is sequentially shifted to each output device, and the other end is also output. An output device group that sequentially outputs the disconnection check data in accordance with a clock signal from an output device located in the section, and the clock signal is input to the input device group. And an output device group, and a first input port for sequentially inputting data output from the input device located at one end of the input device group or the disconnection check data, and the output device group Has a first output port that sequentially supplies the data to be output or the disconnection check data to an output device located at one end of the input device, and is connected to an input device located at the other end of the input device group. A second output port for supplying the disconnection check data to the input device group,
And a second input port that is connected to an output device located at the other end of the output device group and that receives the disconnection check data output from the output device group. First discriminating means for comparing the outputted disconnection check data with the disconnection check data input from the first input port to perform disconnection check of the input device group; A disconnection check data output from an output port and a disconnection check data input from the second input port are compared, and a disconnection check is performed on the output device group. A serial bus system comprising a control unit. 3. The input device is connected to a flip-flop circuit that holds data in synchronization with a clock signal, a sensor that inputs the data, and a data input terminal of the flip-flop circuit,
A first transfer gate that transfers data output from the sensor to the data input terminal, and is connected to a data input terminal of the flip-flop circuit,
A second transfer gate for transferring the data output from the circuit at the previous stage to the data input terminal; and a control means for controlling conduction of the first and second transfer gates according to the clock signal. The serial bus system according to claim 1 or 2, characterized in that: 4. The output device includes a shift register that shifts data input according to a clock signal, and a first register that holds the data held in the shift register.
Second latch circuit connected to the output circuit and holding the data latched by the first latch circuit, and controlling the latch timing of the second latch circuit according to the clock signal. 3. The serial bus system according to claim 1, further comprising a control means. 5. The control unit includes a first input buffer that holds data input from the first input port, and a first input buffer that holds data to be supplied to the second output port.
Output buffer, the data held in the first input buffer and the first input buffer
A first comparison circuit for comparing the data held in the output buffer, a second input buffer for holding the data input from the second input port, and data to be supplied to the first output port. Second to hold
Output buffer, the data held in the second input buffer, and the second
Second comparison circuit for comparing the data held in the output buffer of the first and second comparison circuits, the presence or absence of disconnection of the input device group is determined from the comparison result of the first comparison circuit, and output from the comparison result of the second comparison circuit. 3. The serial bus system according to claim 2, further comprising: a determination unit that determines whether or not the device group is broken. 6. A bidirectional buffer capable of bidirectionally transferring data, wherein a plurality of input devices for inputting data are connected in series, and data input according to a clock signal is input from an input device located at one end. While sequentially shifting to the input device located at the other end, the data is sequentially shifted from the input device located at the other end to the input device located at one end, and the shifted data is transferred from the input device located at the one end. An output device that has a group of input devices that can output data and a bidirectional buffer that can transfer data in both directions. Multiple output devices that output data are connected in series and are located at one end according to the clock signal. The data to be output that is input to is sequentially shifted to the output device located at the other end, and the data is sequentially transferred from the output device located at the other end to the input / output device located at the one end. An output device group that is capable of shifting and outputting the shifted data from an input / output device located at one end, and supplying the clock signal to the input device group and the output device group, and also at one end of the input device group Firstly, sequentially supplying data to an input device located at one end and sequentially inputting data output from the input device located at one end
Second input that sequentially supplies the data to be output to the input / output port of the output device and the output device located at one end of the output device group, and sequentially inputs the data output from the output device located at the one end. A first discriminating means having an output port for discriminating the presence / absence of disconnection of the input device group by comparing the data outputted from the first input / output port with the inputted data; and the second input / output. A serial bus system, comprising: a controller having a second discriminating means for discriminating the presence / absence of a wire break in the output device group by comparing the data output from the port with the input data. 7. The input device is connected to a flip-flop circuit that holds data in synchronization with a clock signal, a sensor that inputs the data, and a data input terminal of the flip-flop circuit,
A first transfer gate that transfers data output from the sensor to the data input terminal, and is connected to a data input terminal of the flip-flop circuit,
A second transfer gate for transferring the data output from the circuit at the previous stage to the data input terminal; and a timing control means for controlling the conduction timing of the first and second transfer gates according to the clock signal, The bidirectional buffer connected between the input end of the first transfer gate and the data output end of the flip-flop circuit, and the transfer direction of the bidirectional buffer is set according to the clock signal and the data. 7. The serial bus system according to claim 6, further comprising direction control means for controlling the direction. 8. The output device includes a shift register that shifts data input according to a clock signal, and a first register that holds the data held in the shift register.
Second latch circuit connected to the output circuit and holding the data latched by the first latch circuit, and controlling the latch timing of the second latch circuit according to the clock signal. Timing control means, the bidirectional buffer connected between the input end and the output end of the shift register, and direction control means for setting the transfer direction of the bidirectional buffer according to the clock signal and the data. 7. The serial bus system according to claim 6, further comprising: 9. The timing control means is configured by a sequence generator including a counter that counts clock signals and outputs the timing signals, and the counter is cleared before starting counting. Or the serial bus system according to item 9. 10. A plurality of input devices for inputting data are connected in series, the input data is sequentially shifted to each input device according to a clock signal, and the shifted data is output from the input device located at one end. Together with an input device group for sequentially inputting disconnection check data from an input device located at the other end in accordance with a clock signal, and sequentially outputting the disconnection check data from the input device located at one end, An input port that supplies a clock signal to the input device group and sequentially inputs the data output from the input device located at one end of the input device group or the data for checking the disconnection, the other end of the input device group Output port connected to an input device located in the section and supplying the disconnection check data to the input device group, output from the output port Serial wherein the data for the disconnection check input from the input port is compared with the data for the disconnection check, serial bus system, characterized by comprising a control unit for performing disconnection check of the input device group. 11. A bidirectional buffer capable of bidirectionally transferring data, wherein a plurality of input devices for inputting data are connected in series, and data input according to a clock signal is input from an input device located at one end. While sequentially shifting to the input device located at the other end, the data is sequentially shifted from the input device located at the other end to the input device located at the one end,
An input device group capable of outputting the shifted data from an input device located at one end, and supplying the clock signal to the input device group and disconnecting the input device located at one end of the input device group. While sequentially supplying check data, and having an input / output port for sequentially inputting the disconnection check data output from the input device located at one end,
A serial bus system comprising: a control unit that compares the disconnection check data output from the input / output port with the input disconnection check data to determine whether or not the input device group has a disconnection. .