JPH0844575A - Monitor and load control system for cpu - Google Patents

Abstract

PURPOSE:To efficiently detect the load state or the overload state of a CPU with a simple constitution by periodically inputting an external interrupt to the CPU and monitoring the time from the interrupt request to the interrupt acceptance. CONSTITUTION:For example, a CPU 1a accepts plural external interrupts IRQ0a to IRQna through a priority control part 2a in the priority order. An interrupt generation part 3a periodically inputs the external interrupt IRQ0a, whose priority is equal to or lower than priorities of the other external interrupts preferably, to the CPU 1a. A CPU management part 10 monitors the time from this interrupt request IRQ0a to interrupt acceptance IAK0a. If the number or external interrupts ORQ0a. to IRQna is small at this time, the CPU 1 quickly accepts the external interrupt IRQ0a, and it doesn't take time to accept it. If the number of external interrupts IRQ0a to IRQna is large, the CPU 1a slowly accepts the external interrupt IRQna, and it takes time to accept it. Consequently, the load state of the CPU is effectively detected by the simple constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU monitoring and load control system, and more specifically, it detects a load state or an overload state, and consequently a failure, in processing of one or more CPUs that receive a plurality of external interrupts. The present invention relates to a CPU monitoring and load control method for detecting load and controlling load sharing.

For example, in a communication device installed in an exchange, a CPU processes interrupt requests from many communication channels in real time. This type of device is required to have high reliability because it has a great social impact, and there are many cases where a multiprocessor configuration is adopted. In order to smoothly operate such a communication system, it is necessary to effectively detect the load state and the fault state of each CPU and effectively share the load.

[0003]

2. Description of the Related Art Conventionally, the CPU load is measured by the time during which effective processing is executed per unit time.

[0004]

However, this kind of measuring method is generally complicated, and it is difficult to distinguish which processing is effective and which processing is not effective, for example, in a single programming type processor. Further, in a multi-programming system processor in which a plurality of tasks are executed alternately, it is necessary to total the execution time for each task, which may impose an extra load on the processor and reduce the original processing capability.

An object of the present invention is to provide a CPU with a simple structure.
Load condition and overload condition detection, and eventually failure detection,
Another object of the present invention is to provide a CPU monitoring and load control method capable of efficiently controlling load sharing.

[0006]

The above-mentioned problems can be solved by the structure shown in FIG. That is, according to the CPU monitoring method of the present invention (1), in the CPU monitoring method that receives a plurality of external interrupts in priority order, external interrupts are periodically input to the CPU, and interrupts are issued from the interrupt request. The load state of the CPU is detected by monitoring the time until reception.

The CPU monitoring method of the present invention (4) is
A CPU that accepts multiple external interrupts, temporarily pools the interrupt vectors, and executes interrupt processing in priority order.
In this monitoring method, an external interrupt is periodically input to the CPU, and the time from the reception of the interrupt until the execution of the interrupt process is monitored to detect the load state of the CPU.

The CPU load control system of the present invention (9) is provided with a plurality of CPUs having the above-mentioned monitoring function, which share a common load, and whichever of the CPUs has an overload state or a fault state. Remaining CP due to detection
The U is configured to share the load.

[0009]

In the CPU monitoring system of the present invention (1), an example is given.
For example, CPU1_aIs the priority control unit 2 _aMultiple external discounts via
Included IRQ_0a~ IRQ_naAre accepted in order of priority. Interrupt occurrence
Part 3_aIs CPU1_aTo the same degree as other or
External interrupt IRQ with lower priority_0aEnter regularly
I do. Then, the CPU management unit 10 sends the interrupt request IRQ.
_0aReceived from IAK_0aUp to time.

When the external interrupts IRQ _{0a to} IRQ _na are small, the CPU 1 _a accepts the external interrupts IRQ _0a quickly and does not take much time. In addition, external interrupt IRQ _{0a to} IRQ
_{If the number of na} is large, the acceptance of the external interrupt IRQ ₀ by the CPU 1 _a becomes slow and takes time. Therefore, according to the present invention (1), the load state of the CPU can be effectively detected with a simple configuration.

Preferably, the time is a first predetermined time.
The CPU overload state is detected when the value exceeds the limit. Also
Preferably, the second predetermined time is longer than the first predetermined time.
The failure state of the CPU is detected when the time is exceeded.
In the CPU monitoring method of the present invention (4), for example, CP
U1_aIs the priority control unit 2 _aMultiple external interrupt IRQs via
_0a~ IRQ_naAnd wait for the interrupt vector
Pool in a queue and interrupt processing TSK in priority order_0a~ TSK_na
To execute.

In this case, a plurality of external interrupts may be received in the order of priority and the interrupt processing may be executed in the order of reception, or a plurality of external interrupts may be received all at once and the interrupt processing executed in the order of priority. Is also good. The interrupt generating unit 3 _a periodically inputs to the CPU 1 _a an external interrupt IRQ _0a, which preferably has the same or lower priority than the others. Then, the CPU management unit 1
0 monitors the time from the interruption acceptance IAK _0a to the execution of the interruption processing TSK _0a .

[0013] If the external interrupt IRQ _0a ~IRQ _na is small, less queues, interrupt processing TS by CPU1 _a
It does not take long to execute K _0a . External interrupt IR
If there are many Q _{0a to} IRQ _na , there will be more queues and C
It takes a long time to execute the interrupt process TSK _0a by the PU 1 _a . Therefore, according to the present invention (4), the CPU load state can be effectively detected with a simple configuration.

Preferably, the CPU overload state is detected when the time exceeds the third predetermined time. Further, preferably, the failure state of the CPU is detected when the time exceeds a fourth predetermined time which is longer than the third time.
Further, preferably, the predetermined time period is generated by a one-shot multivibrator circuit.

Further, preferably, the time is counted by a counter. In the load control system of the CPU of the present invention (9), comprising a plurality of CPU 1 _a, 1 _b comprising the monitoring function, the load is usually these common 6
For example, _{1 to} 6 _n are divided into 1/2, for example. And CPU
Overloaded with 1 _a (BSY _1a or BSY _2a) or fault condition (ALM _1a or ALM _2a) If the detected CPU
1 _b bears part or all of the load on the CPU 1 _a . Conversely, when the CPU 1 _b detects an overload state (BSY _1b or BSY _2b ) or a fault state (ALM _1b or ALM _2b ), the CPU 1 _a bears part or all of the load of the CPU 1 _b . Therefore, according to the present invention (9), it is possible to efficiently control the load sharing between the CPUs with a simple configuration.

Preferably, the above-mentioned monitoring functions are integrated in one place (for example, the CPU management unit 10), and the monitoring function for each time is constituted by a common RAM counter 10 ₅ .

[0017]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. Figure 2 is a diagram showing a configuration of a first embodiment, CPU, 1 ₁ of 1 multiprogramming system in FIG supervisor, 1 ₂ task 2 interrupt control unit (INTC), 2 ₁ priority control unit (PRT
C), 2 ₂ is a mask circuit (MSK), 3 is an interrupt generator (IG), 3 ₁ is a frequency dividing circuit (1 / M), 3 ₂ is a flip-flop circuit (FF), 4 is from an interrupt request. monitoring unit for monitoring the time to interrupt reception, 4 _1, 4 ₂ one-shot multivibrator circuit (SS), 4 _3, 4 ₄ is a flip-flop circuit (FF), 5 execution interrupt task from interrupt reception monitoring unit for monitoring the time to, 5 _1, 5 ₂ one-shot multivibrator circuit (SS), 5 ₃ to 5 ₅ flip-flop circuit (FF), 6 ₁ ~6 _m serial communication controller (SCC) , CH _{1 to} CH _m are communication channels thereof, 7 is an interrupt bus (IB), 8 is a common bus (C which is a data bus, an address bus, a control bus, etc. of the CPU 1).
B) and 21 are OR gate circuits (O), and SR is a system reset signal.

Supervisor 1₁Is an external interrupt request I
RQ₀~ IRQ_nCommon acceptance processing that accepts
Schedule processing of tasks and processing to execute these
And so on. Task 1₂External interrupt IRQ₀~ IRQ_n
Interrupt task ITSK scheduled by reception of₀
~ ITSK_nEtc. are included. Priority control unit 2₁Is this example
Then interrupt request IRQ₁(BSY₁), IRQ₂(BSY
₂) Is given a high priority. SCC6₁~ S
CC6_mInterrupt request IRQ from₃~ IRQ_nFor
Medium priority or communication channel CH ₁~ CH_m
The priority is given according to the urgency or importance of. Soshi
The interrupt request IRQ from the interrupt generator 3.₀For
Include request IRQ₃~ IRQ_nThe same as or against
Among them, the priority is given to medium or lower. Follow
Interrupt request IRQ₀Is the interrupt request IRQ₃~ IRQ_nWhen
In the relationship of, the order of occurrence is accepted.

The mask circuit 2 ₂ is normally fully opened, and CP
U1 bears the full load of SCC6 _{1 to} SCC6 _m . That is, for example, the SCC 6 ₁ generates an interrupt request signal IRQ ₃ when transmitting / receiving one frame data. When the supervisor 1 ₁ receives the interrupt request IRQ ₃ , the interrupt controller 2
Sends an interrupt acceptance signal IAK ₃ to SCC 6 ₁ .
Thereafter, the supervisor 1 ₁ schedules the interrupt task ITSK ₃ corresponding to the interrupt request (interrupt vector) IRQ _3, which temporarily pooled in order of reception to the run queue of the interrupt task. Then, when the turn comes, the interrupt task IT
Execute SK ₃ . The same applies to SCC6 _{2 to} 6 _m .

Under such a condition, the interrupt generator 3 is regularly
Interrupt request signal IRQ₀To occur. That is, the frequency divider circuit
Three₁Is the master clock signal MCK divided by M,
To generate the interrupt clock signal ICK. FF3₂Is an interrupt
The interrupt request signal I is set by the clock signal ICK
RQ₀= 1 is output. At the same time, this interrupt request signal IR
Q₀Is SS4 of the monitoring unit 4₁, SS4₂Trigger. S
S4₁Timeout time t₁CPU1 is overloaded
It is set to a value that can be determined whether or not Immediately
Chi, supervisor 1₁Is t₁Interrupt request IRQ within₀of
If it is accepted, it is within the range of normal load, and t₁Need to interrupt within
Seeking IRQ₀If it is not accepted, it is overloaded.
Also SS4₂Timeout time t ₂(T₁More fully
Long) can determine whether CPU1 is in a faulty state
Is set to a value. That is, supervisor 1₁Is t₂
Interrupt request IRQ within₀If you accept
, T₂Interrupt request IRQ within₀If you do not accept
It is in a state of disability.

If the supervisor 1 ₁ is not busy,
Accept the interrupt request signal IRQ ₀ within a reasonable time,
The FF3 ₂ is reset by the interrupt acceptance signal IAK ₀ . In this case, the interrupt request signal IRQ ₀ = 0 before SS4 ₁ and SS4 ₂ time out, and therefore FF
4 ₃ and FF4 ₄ are not set. On the other hand, the interrupt acceptance signal IAK ₀ sets the FF ₅ 5 of the monitoring unit 5. The output of FF5 ₅ triggers the SS5 _1, SS5 _2. The time-out time t ₃ of SS5 ₁ is set to a value that can determine whether the CPU 1 is overloaded. That is, the supervisor 1 ₁ receives the interrupt task I within t _3.
If TSK ₀ is executed, it is in the range of normal load, and if the interrupt task ITSK ₀ is not executed within t ₃ , it is in overload. Further, the timeout time t ₄ (sufficiently longer than t ₃ ) of SS5 ₂ is set to a value with which it can be determined whether or not the CPU 1 is in a failure state. That is, supervisor 1
_{If 1} executes the interrupt task ITSK ₀ within t ₄ , it is in the normal range, and if it does not execute the interrupt task ITSK ₀ within t ₄ , it is in a failure state.

If the supervisor 1 ₁ is not busy,
The interrupt task ITSK ₀ is executed within a reasonable time, and F
F5 ₅ is reset by the program reset signal PR ₁ generated when the interrupt task ITSK ₀ is executed. In this case, F before SS5 ₁ and SS5 ₂ time out.
The output Q of F5 ₅ becomes 0, so that FF 5 ₃ and 5 ₄ are not set.

However, when the supervisor 1 ₁ is busy, the interrupt request signal IRQ ₀ cannot be accepted within t ₁ . That is, when the SS4 ₁ times out an interrupt request signal IRQ ₀ = 1, thereby FF4 ₃ is set, the busy signal BSY ₁ = 1. Busy signal B
SY ₁ issues a high priority interrupt request to the CPU ₁ as an interrupt request signal IRQ ₁ . When the supervisor 1 ₁ receives the interrupt request IRQ ₁ , it schedules the interrupt task ITSK ₁ . When this interrupt task ITSK ₁ is put into execution, mask data is set in the mask circuit 2 ₂ in the process to reduce the load. SC
C6 ₁ temporarily masking all or urgency or less important part of the interrupt request to 6 _n, attempt to reduce the load. Then, (When eg supervisor 1 ₁ becomes situations to perform idle task) When the load is reduced to return the mask data is fully opened.

Further, when the supervisor 1 ₁ is busy, the interrupt task ITSK ₀ is not executed within t ₃ . That is, when SS5 ₁ times out, FF5 ₅
Output Q = 1, and thereby FF5 ₃ is set and the busy signal BSY ₂ = 1. Busy signal BSY
₂ issues an interrupt request of high priority to the CPU 1 as an interrupt request signal IRQ ₂ . When the supervisor 1 ₁ receives the interrupt request IRQ ₂ , it schedules the interrupt task ITSK ₂ . When the interrupt task ITSK ₂ is put into execution, mask data is set in the mask circuit 2 ₂ in the process to reduce the load.

The busy signals BSY ₁ and BSY ₂
Are both signals that detect the overload state of the CPU 1,
When the acceptance delay of the interrupt request IRQ ₀ is detected (BSY
₁ ) and the case where the execution delay of the interrupt task ITSK ₀ is detected (BSY ₂ ) differ in the nature (severity) of overload in the CPU 1. Generally, it is more serious when a delay in accepting the interrupt request IRQ ₀ is detected. In this embodiment, the busy signals BSY ₁ and BSY ₂ are used to separately request the interrupt request IR.
Since Q ₁ and IRQ ₂ are performed, measures for reducing the load can also be taken separately. However, if it is not necessary to divide them, the busy signals BSY ₁ and BSY ₂ may be logically ORed, and the interrupt request IRQ ₁ may be applied at the output.

Further, if the CPU 1 has a failure (holt, runaway, infinite loop, etc.), the interrupt request signal IRQ ₀ cannot be accepted within t ₂ . Alternatively, the interrupt task ITSK ₀ is t ₄
Not implemented within. In the case of these FF4 ₄ / F
F5 ₄ is set and alarm signals ALM ₁ / ALM ₂
= 1. When ALM ₁ / ALM ₂ = 1 is satisfied, the OR gate circuit 21 is satisfied, and the operation of the CPU 1 is forcibly stopped. Although not shown, a light emitting diode may be turned on by the output of the OR gate circuit 21 to notify the failure.

Thus, according to the first embodiment, the overload detection, the fault detection, and the load management of the CPU 1 can be efficiently performed with a simple structure including the one-shot multivibrator circuit and the flip-flop circuit. In addition, CPU1
Instead of setting mask data in the mask circuit 2 ₂ , for example, an OR gate circuit 22 is provided and the busy signal BS
The mask data may be directly supplied to the mask circuit 2 ₂ by the generation of Y ₁ / BSY ₂ = 1 to reduce the load.

FIG. 3 is a diagram showing the structure of the second embodiment. The difference from the first embodiment is that the monitoring units 4 and 5 are composed of counters and comparison circuits (or decoders). . That is, 4 is a monitoring unit that monitors the time from interrupt request to interrupt acceptance, 4 ₇ is a counter circuit (CTR), 4 ₈ is a comparison circuit (CMP), and 5 is from interrupt acceptance to execution of an interrupt task. A monitoring unit for monitoring time, 5 ₆ is a flip-flop circuit (FF), 5 ₇ is a counter circuit (CTR), and 5 ₈ is a comparison circuit (CMP).

In the monitoring unit 4, the counter 4 ₇ is enabled by the interrupt request signal IRQ ₀ = 1
The counting of the master clock signal MCK is started. If the supervisor 1 ₁ is not busy, the interrupt request IRQ ₀ is accepted within a reasonable time. That is, the FF3 ₂ is reset by the interrupt acceptance signal IAK ₀ , which causes the counter 4 ₇ to stop counting.

The interrupt acceptance processing of the supervisor 1 ₁ reads the count value of the counter 4 ₇ via the common bus 8 when the interrupt request IRQ ₀ is accepted. The count value is read by, for example, designating the I / O address of the monitoring unit 4 on the address bus, sending a read control signal to the control bus, and reading the count value from the data bus. The value of the read count value is CP
Since each case may take various values depending on the load state of U1, supervisor 1 ₁ can precisely determine the load state of CPU1 based on the regimen value. Therefore, in this embodiment, it is possible to finely control the load reduction.

When the supervisor 1 ₁ is busy, the interrupt request IRQ ₀ cannot be accepted within a reasonable time. As a result, it outputs a busy signal BSY ₁ by detecting the counter value corresponding to the comparison circuit in 4 ₈ time t _1. However, in this second embodiment, since the count value itself is taken into the supervisor 1 ₁ , the supervisor 1 ₁ can independently determine whether it is busy or not. Therefore, in the present embodiment, the portion of the comparison circuit 4 ₈ for detecting the busy signal BSY ₁ is not necessarily required. However, for example, when the OR gate circuit 22 is provided and the mask data of the mask circuit 2 _{2 is} directly controlled by the output of the OR gate circuit 22, the busy signal BSY ₁ is useful.

Further, when the CPU 1 has a failure, the interrupt request IRQ ₀ cannot be accepted until any time. As a result, it outputs an alarm signal ALM ₁ by detecting the counter value corresponding to the comparator circuit 4 ₈ time t _2. The alarm signal ALM ₁ is sent to the CP via the OR gate circuit 21.
The operation of U1 is forcibly stopped. On the other hand, in the monitoring section 5, the FF5 ₆ is set by the interrupt acceptance signal IAK ₀ . The counter 5 ₇ becomes count enable by the output Q = 1 of the FF 5 ₆ and starts counting the master clock signal MCK.

When the CPU 1 is not busy, the interrupt task ITSK ₀ corresponding to the interrupt request IRQ ₀ is put into execution within a reasonable time. This causes the interrupt task ITSK
_{For 0} , first, the count value of the counter 5 ₇ is read through the common bus 8, and thereafter, the program reset signal PR ₃ is generated to reset the FF 5 ₆ and the counter 5 ₇ . The value of the read count supervisor 1 ₁ because each time may take various values depending on the load state of CPU1 can precisely determine the load state of CPU1 based on the regimen value.
Therefore, in this embodiment, it is possible to finely control the load reduction.

If the CPU 1 is busy, the interrupt task ITSK ₀ will not be executed in a reasonable time. As a result, it outputs a busy signal BSY ₂ by detecting the counter value corresponding to the comparison circuit in 5 ₈ hours t _3. However, the usage of the busy signal BSY ₂ may be the same as above.
If the CPU 1 has a failure, the interrupt task ITSK ₀ is not executed until any time. As a result, the comparator circuit 5 ₈ outputs the alarm signal ALM ₂ when it detects the count value corresponding to the time t ₄ . Alarm signal A
The LM ₂ forcibly stops the operation of the CPU 1 via the OR gate circuit 21.

Thus, according to the second embodiment, the configuration using the counter enables the CPU 1 to perform the fine load detection and the load management. FIG. 4 is a diagram showing the configuration of the third embodiment. This third embodiment shows an example of application of the present invention to the multiprocessor system. In Fig, 1 _a, 1 _b is a multiprogramming system CPU, 2 _a, 2 _b is an interrupt control unit _{(INTC), 3 a, 3} b an interrupt generator (IG), 6
_{1 to} 6 _n are serial communication control units (SCC), CH _{1 to} C
H _n is the communication channel, 7 is the interrupt bus (IB),
8 _a, 8 _b is a common bus (C of each CPU1 _a, 1 _b
B), the expansion bus 9 (EB), 10 is CPU 1 _a, 1 _b
CPU management unit that detects the load and fault status of the
1 _a, 11 _b is a bus interface for connection control between the expansion bus 9 and common bus _{8 a, 8 b (BIF)} , 12
Is an arbitration bus (AB) that arbitrates the right to use the expansion bus 1
Reference numeral 3 is a bus arbitration unit (ABT).

The CPU 1 _a, 1 _b is normally are fairly share the full load of the serial communication control unit 6 ₁ to 6 _n. That is,
Interrupt control unit 2 _a accepts the first part of the interrupt request IRQ ₁ ~IRQ _n by setting the mask data from the CPU 1 _a. On the other hand, the interrupt controller 2 _b accepts the second part of the interrupt request IRQ ₁ ~IRQ _n by setting the mask data from the CPU 1 _b.

CPU1_aIs my common bus 8_aAlways
Accessible. On the other hand, CPU1 _aTo expansion bus 9
To access the bus request signal BRQ to the arbitration bus 12_a
Is output. In the bus arbitration unit 13, the expansion bus 9 is the CPU 1_b
CPU1 if not in use (busy)_aBus permit
Signal BAK_aWill be returned. CPU1 that received this_aIs
BIF11_aEnergize the common bus 8_aTo the expansion bus 9
To continue.

[0038] In this state, CPU 1 _a can access any one of the SCC6 ₁ to 6 _n by specifying a device address of SCC6 ₁ to 6 _n, for example, the address bus. Further, by designating a device address assigned to the CPU management unit 10, writing command data (such as program reset) into the CPU management unit 10, and the CPU management unit 10
It is possible to read the count value data and status data (busy, alarm) from. The same applies to the CPU 1 _b .

FIG. 5 is a block diagram of the CPU management section of the third embodiment. In the figure, 10 is the CPU management section 10 ₁ , 10
₂ is a flip-flop circuit (FF), 10 ₃ is a selector (SEL), 10 ₄ is an adder circuit, 10 ₅ is a RAM counter, 10 ₆ is an AND gate circuit (A), 10 ₇ is a counter (CTR), 10 ₈ is Comparator (CMP), 10
₉ is an instruction register (IR), 10 ₁₀ is a decoder (DEC), 10 ₁₁ is a flip-flop (F).
F), 10 _12, 10 ₁₃ are three-state driver circuit (D), 10 ₁₄ a decoder (DEC), 10 ₁₅ ~10 ₁₈
Is a comparator (CMP), 10 ₂₁ to 10 ₂₄ , 10 ₃₁ to
10 ₃₄ is a flip-flop (FF).

The entire content of the RAM counter 10 ₅ is the CPU 1
It has been pre-cleared by a command from the _a / CPU1 _b. FF10 ₁ is an interrupt acceptance signal I from the interrupt control unit 2 _a.
Set by AK _0a , then interrupt task ITS
It is reset by the program reset signal PR _3a generated by the CPU 1 _a during execution of K _0a . FF1
0 ₂ is set by the interrupt acceptance signal IAK _0b from the interrupt control unit 2 _b , and then reset by the program reset signal PR _3b generated by the CPU 1 _b during execution of the interrupt task ITSK _0b .

Counter 10₇Is the master clock signal MC
Cyclic by K (0, 1, 2, 3, in this example
(Like 0, 1, 2, 3, ...)
It Counter 10₇Count output of Q (in this example, 2
Is a selector 10₃Selection input and RAM counter 1
0_FiveIt is added to the address input of. Count output Q =
RAM counter 10 when 0_FiveFrom address 0
Data CD_R0= 0 is read. On the other hand, selector 1
0₃Is the interrupt request signal IRQ at this point_0aSelect and output
There is. Adder circuit 10_FourIs the IRQ_0aIf = 0 then CD _R0
Write count data CD by adding 0 to = 0_W0Form = 0
To achieve. Also IRQ_0aIf = 1 then CD_R0Add 1 to = 0
Calculate and write count data CD_W0= 1 is formed. Immediately
The count data CD_R0Is IRQ_0a+1 if = 1
And IRQ_0aWhen = 0, the value is retained.

Similarly, the count data CD _R1 of the address 1 is 1/0 of the output Q of the FF 10 ₁ and the count data CD _R2 of the address 2 is 1/0 of the interrupt request signal IRQ _0b .
, The count data CD _R3 address 3 1/0 of FF10 ₂ outputs Q, corresponding respectively to be +1, or retains its contents. Interrupt request signal I, for example, the interrupt generation unit 3 _a
When RQ _0a = 1, the count data CD _R0 of the RAM counter 10 ₅ starts counting up. Interrupt request IRQ if supervisor 1 _{1a of} CPU 1 _a is not busy
_0a will be accepted within a reasonable time. That is, the interrupt request signal IRQ _0a = 1 is reset by the interrupt acceptance signal IAK _0a , whereby the count data CD _R0 stops counting up.

[0043] extend the common bus 8 _a interrupt the process of accepting the supervisor 1 _1a is at the time of accepting the interrupt request IRQ _0a bus 9
Connected to the RAM counter 10 ₅ count data CD
_{Read R0} . To read the count data CD _R0 , for example, the device address of the CPU management unit 10 and the R
Specify sub address 0 for AM counter 10 ₅ ,
In addition, the read signal is sent to the control bus.

The device address and the memory of the CPU management unit 10
The pulse signal is decoded by a decoder (not shown).
Generate WRD. As a result, FF10₁₁Is set
Then, the extension signal EXT for using the extension bus 13 is generated.
In addition, IR10 is generated by the pulse signal WRD.₉Sub address
I₂= 0 and command information to the effect of read is set. Ko
Comparator 10₈Is IR10₉Subaddress I of₂= 0
And counter 10₇Is compared with the count value of
And decoder 10_TenEnergize. Decoder 10 _TenIs IR
10₉Directive I₁(= Lead) according to A = B timing
Read gate signal RDG. This
Driver circuit 10₂Is activated, and count data CD_R0
Contents of CPU1_aRead in.

Count data CD read_R0Content of
Is CPU1_aDepending on the load condition of
Supervisor 1_1aIs the count data CD_R0
CPU1 based on the contents of_aThe load condition of the machine
it can. Therefore, if necessary, CPU1_aOriginal load reduction
Can be finely controlled. Count data CD_R0Of
The content is CPU1_aRead the above by reset command from
It is cleared by the same control as in the case. That is, in this case
Count data CD _R0At the timing when is read
Order 10_TenThe gate signal CL is generated from
10_FiveWrite count data to CD_W0Is forced to 0
I do. The above is CPU1_bIs also the same.

On the other hand, CPU1_a, CPU1_bIs crowded
RAM counter 10_FiveEach count up
Mu. Decoder 10₁₄Is counter 10₇Count output Q
Pulse signal φ with different phases according to the value of₀~ Φ₃To
It is outputting. In this state, the comparator 10_FifteenIs RA
M counter 10_FiveEach count data CD_RAnd time t₁
Is compared with a predetermined value corresponding to, and if A> B, then H
Outputs IGH level. Then, the pulse signal φ₀= 1
If A> B is satisfied at the timing of, FF10_{twenty one}Output Q
(Busy signal BSY_1a) = 1. The pulse signal φ
₂If A> B is satisfied at the timing of = 1, FF10_{twenty three}of
Output Q (busy signal BSY_1b) = 1.

Further, the comparator 10 ₁₆ compares each count data CD _R of the RAM counter 10 ₅ with a predetermined value corresponding to the time t ₂ , and outputs a HIGH level when A> B. Then, when A> B is satisfied at the timing of the pulse signal φ ₁ = 1, the output Q (busy signal BSY _2a ) of the FF 10 ₂₂ becomes 1. When A> B is satisfied at the timing of pulse signal φ ₃ = 1, the output Q of FF10 ₂₄
(Busy signal BSY _2b ) = 1.

Further, the comparator 10₁₇Is a RAM count
10_FiveEach count data CD_RAnd time t₃Corresponding to
Is compared with a predetermined value, and if A> B, the HIGH level is
Output bell. Then, the pulse signal φ₀= 1 Taimi
FF10 when Satisfaction A> B₃₁Output Q (Alarm
Signal ALM_1a) = 1. The pulse signal φ₂= 1
If A> B is satisfied at the timing of, FF10₃₃Output Q
(Alarm signal ALM _1b) = 1.

Further, the comparator 10₁₈Is a RAM count
10_FiveEach count data CD_RAnd time t_FourCorresponding to
Is compared with a predetermined value, and if A> B, the HIGH level is
Output bell. Then, the pulse signal φ₁= 1 Taimi
FF10 when Satisfaction A> B₃₃Output Q (Alarm
Signal ALM_1b) = 1. The pulse signal φ₃= 1
If A> B is satisfied at the timing of, FF10₃₄Output Q
(Alarm signal ALM _2b) = 1.

[0050] In this state, CPU1 _a, CPU1 _b is able to read status data (BSY _1a ~ALM _2b) at any time. The reading of the status data is performed by, for example, designating another device address of the CPU management unit 10 on the address bus and sending a read signal to the control bus. In this case, the generation of the gate signal RD immediately activates the driver circuit 10 ₁₃ and the status data is read into the CPU 1 _a or the CPU 1 _b .

[0051] According to the third embodiment, CPU 1 _a, C
PU1 _b can perform mutual load balancing control by monitoring common status data. That is, for example, a CPU
When a failure occurs in 1 _b , the status data is busy signal BSY _1b , BSY _2b = 1 and alarm signal ALM.
_1b and ALM _2b = 1. Alarm signal of the status data CPU 1 _a is read in this case ALM _1b /
Focusing on ALM _2b = 1 and changing so as to bear the full load by itself. That is, the interrupt control unit 2 _a is changed to accept all of the interrupt request IRQ ₁ ~IRQ _n by setting the mask data from the CPU 1 _a. On the other hand, CPU1 _b is A
The operation is stopped when LM _1b / ALM _2b = 1. When _a failure occurs in the CPU 1a, the reverse operation is performed.

Further, for example, the busy signal BSY_1aAnd BS
Y_2a= 0 and the busy signal BSY _1bOr BSY_2b= 1
If it is, for example, CPU1_aIs 2 / of full load
Bear 3 CPU1_bBear the remaining 1/3
It is possible to change to. Also busy signal BSY_1b
And BSY_2b= 0 and the busy signal BSY_1aOr BS
Y_2aIf = 1 then CPU1_bIs full load 2
/ 3, CPU1_aWill bear the remaining 1/3
Can change.

In this case, the CPU 1 _b outputs the program reset signal PR _1b when its own load is reduced (that is, when the internal processing proceeds), and resets the FF10 ₂₃ and FF10 ₂₄ . This reset is performed immediately without outputting the extension signal EXT. Further, the CPU 1 _a outputs the program reset signal PR _1a when its own load is reduced, and resets the FF 10 ₂₁ and FF 10 ₂₂ . In either case, if the busy signal is reset, the load sharing returns to 1/2 of fairness.

The above status data is not shown in the figure.
Encoded by ROM etc. and output from it interrupt control unit 2
_a, 2_bMask circuit 2_2a, 2_2bMask data directly
It may be configured to change to. This way CPU1
_a, CPU1_bEasy synchronization control of load sharing between
become. Alternatively, a CPU dedicated for management in the CPU management unit 10
Equipped with CPU1_a, CPU1 _bLoad balancing control
May be configured to be performed more finely.

Although the CPU 1 is based on the multi-programming system in the above embodiment, the present invention can be applied to a single programming system CPU. Although a plurality of preferred embodiments of the present invention have been described above, it goes without saying that various changes can be made to the configurations, combinations and control procedures without departing from the spirit of the present invention.

[0056]

As described above, since the CPU monitoring and load control system of the present invention has the above-mentioned configuration, it is possible to properly detect the load state and overload state load of the CPU by the simple configuration, and to detect the failure. Also, proper control of load sharing can be performed efficiently.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a configuration of a first embodiment.

FIG. 3 is a diagram showing a configuration of a second embodiment.

FIG. 4 is a diagram showing a configuration of a third embodiment.

FIG. 5 is a block diagram of a CPU management unit according to the third embodiment.

[Explanation of symbols]

1 _a , 1 _b CPU 2 _a , 2 _b Interrupt control unit 3 _a , 3 _b Interrupt generation unit 6 _{1 to} 6 _n I / O control unit 10 CPU management unit

Claims (10)

[Claims] 1. A C which accepts a plurality of external interrupts in priority order
In the PU monitoring method, an external interrupt is periodically input to the CPU, and the time from the interrupt request to the interrupt acceptance is monitored to detect the CPU.
CPU monitoring method characterized by detecting the load state of the CPU. 2. The CPU monitoring method according to claim 1, wherein the CPU overload state is detected when the time exceeds a first predetermined time. 3. The CPU monitoring system according to claim 2, wherein a failure state of the CPU is detected when the time exceeds a second predetermined time which is longer than the first time. 4. A CPU monitoring method for accepting a plurality of external interrupts, temporarily pooling the interrupt vectors, and executing interrupt processing in priority order. C by inputting and monitoring the time from the acceptance of the interrupt to the execution of the interrupt process
A CPU monitoring method characterized by detecting a load state of a PU. 5. The CPU monitoring system according to claim 4, wherein the CPU overload state is detected when the time exceeds a third predetermined time. 6. The CPU monitoring method according to claim 5, wherein a failure state of the CPU is detected when the time exceeds a fourth predetermined time which is longer than the third time. 7. The CPU monitoring method according to claim 2, wherein the predetermined time is generated by a one-shot multivibrator circuit. 8. The CPU monitoring method according to claim 1, wherein the time is counted by a counter. 9. A CP having the monitoring function according to claim 1.
Multiple U are provided, and these share a common load,
A load control system for a CPU, wherein any one of the CPUs is configured to share the load when an overload condition or a fault condition is detected. 10. The CPU load control system according to claim 9, wherein the monitoring functions of claim 1 are combined in one place, and the monitoring function of each time is constituted by a common RAM counter.