CN109918223A - Cpu reset monitoring device - Google Patents
Cpu reset monitoring device Download PDFInfo
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- CN109918223A CN109918223A CN201910369527.4A CN201910369527A CN109918223A CN 109918223 A CN109918223 A CN 109918223A CN 201910369527 A CN201910369527 A CN 201910369527A CN 109918223 A CN109918223 A CN 109918223A
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- 238000012806 monitoring device Methods 0.000 title claims abstract description 22
- 238000011084 recovery Methods 0.000 abstract description 5
- 238000012423 maintenance Methods 0.000 description 8
- 238000012544 monitoring process Methods 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 210000001367 artery Anatomy 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Abstract
The present invention relates to a kind of cpu reset monitoring device, including reset chip, the CPU has external interrupt input terminal and the RESET input；The reset chip includes hand-reset end and reset output terminal；The cpu reset monitoring device further includes reset button and delay circuit, and the reset button is connected to the hand-reset end by the delay circuit all the way, and another way and the external interrupt input terminal are directly connected to the external interrupt input terminal；The reset output terminal of the reset chip is connect with the RESET input of the CPU.The present invention not only can quick position reset type, but also can rapidly find the root of exceptional reset because to solve the system failure, the normal operation of quick recovery system accurately and in time.
Description
Technical field
The present invention relates to electronic information and automatic control technology field, in particular to a kind of cpu reset monitoring device.
Background technique
System reset has two kinds of situations of normal reset and exceptional reset, and exceptional reset is usually surprisingly gone offline by system, is soft
Caused by part exception or hardware anomalies.In the prior art, reset what operation was usually completed by a reset chip auxiliary,
After system resets, soft and hardware critical state information is removed, and current reset schemes can not tell reset circuit, because
And maintenance personnel also can not timely and effectively search guilty culprit, increase the difficulty of system maintenance.
Summary of the invention
Based on this, it is necessary to provide a kind of cpu reset monitoring device, not only be apparent that exceptional reset generates
Root because also can recorde the status information for resetting preceding part software and hardware, facilitating quick repair system failure, greatly reduce
The difficulty of system maintenance, shortens maintenance time, can effectively reduce maintenance cost.
For achieving the above object, the present invention uses following technical scheme.
The present invention provides a kind of cpu reset monitoring device, including reset chip, and the CPU has external interrupt input terminal
And the RESET input；The reset chip includes hand-reset end and reset output terminal；
The cpu reset monitoring device further includes reset button and delay circuit, and the reset button passes through described all the way
Delay circuit is connected to the hand-reset end, and it is defeated that another way with the external interrupt input terminal is directly connected to the external interrupt
Enter end；The reset output terminal of the reset chip is connect with the RESET input of the CPU.
Preferably, the reset chip also has house dog input terminal and house dog output end, and the CPU, which also has, to guard the gate
Dog pulse output end, the watchdog pulse output end are connect with the house dog input terminal, and the house dog output end is all the way
It is connect with the external interrupt input terminal, another way is connect with the input terminal of the delay circuit.
The present invention also provides a kind of cpu reset monitoring device, including delay circuit and reset chip, the CPU has outer
Portion's interrupting input end and the RESET input；The reset chip includes hand-reset end and reset output terminal；
The CPU also has watchdog pulse output end, and the reset chip also has house dog input terminal and house dog
Output end, the watchdog pulse output end are connect with the house dog input terminal；The house dog output end is connected to all the way
The external interrupt input terminal, another way are connect with the input terminal of the delay circuit.
Above scheme through the invention can be according to the soft and hardware state of CPU interrupt routine record after resetting generation
Information, not only can quick position reset type, but also can rapidly be found according to the soft and hardware status information abnormal multiple
The root of position because to solve the system failure, the normal operation of quick recovery system accurately and in time.
Detailed description of the invention
Fig. 1 is the circuit theory schematic diagram of cpu reset monitoring device in the embodiment of the present invention one；
Fig. 2 is the circuit theory schematic diagram of cpu reset monitoring device in the embodiment of the present invention two；
Fig. 3 is the circuit theory schematic diagram of cpu reset monitoring device in the embodiment of the present invention three.
Specific embodiment
With reference to the accompanying drawing and specific embodiment is described further.
Embodiment one:
As shown in Figure 1, the present embodiment provides a kind of cpu reset monitoring device, for carrying out reset control, the CPU to CPU
Reset control device mainly includes reset button, reset chip and delay circuit.Wherein,
Reset button for generating pulse signal manually；
Reset chip carries out auxiliary reset for providing reset signal；
Delay circuit is used to carry out delay disposal to the pulse signal.
The CPU has an external interrupt input terminal INT and the RESET input Reset, and the reset chip has manual
Reset terminal MR and reset output terminal Rst, the reset button pass through delay circuit all the way and are connected to hand-reset end MR, another way
It is directly connected to external interrupt input terminal INT.
This embodiment scheme can realize monitoring and the record of hand-reset, and principle is:
When pressing reset button, reset button generates a pulse signal, which is directly inputted to outside all the way
Interrupting input end INT, triggering CPU generate interruption, and the interrupt routine recording reset types of CPU are hand-reset, meanwhile, above-mentioned arteries and veins
Hand-reset end MR is inputted after rushing the delayed circuit of signal another way, after reset chip receives the pulse signal, passes through reset
Output end Rst generates reset signal, and is input to the RESET input Reset of CPU, realizes the reset of CPU.Prolong due to being provided with
Slow circuit, to before cpu reset, there are the scheduled times, so that the interrupt routine of CPU records soft and hardware status information, or are formed
The reset log.The soft and hardware status information even CPU has resetted, and after CPU is restarted, still can check, in this way
With quick position reset type, and can rapidly be found according to the soft and hardware status information or the reset log abnormal multiple
The root of position because to solve the system failure, the normal operation of quick recovery system accurately and in time.
Embodiment two:
Referring to shown in Fig. 2, the present embodiment provides another cpu reset monitoring device, which is based on real
The cpu reset monitoring device in example one is applied, and using the reset chip with WatchDog Timer WDT, such as 706 type reset coils
Piece.
The reset chip also has house dog input terminal WDI and house dog output end in addition to function had in embodiment one
WDO, meanwhile, CPU is also configured with watchdog pulse output end WDI, the present embodiment by the watchdog pulse output end WDI of CPU with
The house dog input terminal WDI connection of reset chip, and the external interrupt input terminal connection of house dog output end WDO and CPU, together
Sample, the reset output terminal of reset chip are connect with the RESET input of the CPU.
Monitoring and the record of hand-reset not only may be implemented in the cpu reset monitoring device of the present embodiment, can also be achieved certainly
The principle of the dynamic monitoring resetted and record, the monitoring and record that automatically reset is:
WDT (Watch Dog Timer, WatchDog Timer) is a component part of single-chip microcontroller, it is actually one
A counter generally gives mono- number of WDT, and house dog starts to count down after CPU brings into operation.If CPU normal operation, one is crossed
Section time CPU can issue pulse command by watchdog pulse output end WDI and reset by WDT, restart to count down.If
WDT reduces to 0 and does not receive above-mentioned pulse command yet, is considered as CPU and exception occurs, at this time the house dog output end of reset chip
WDO can generate a pulse signal.
In the present embodiment, the external interrupt input terminal INT connection on mono- tunnel door dog output end WDO and CPU, another way and delay
The input terminal of circuit connects.In this way, when CPU occurs abnormal, watchdog pulse output end WDI no signal output, as arrival WDT
Timing cycle when, house dog output end WDO exports a pulse signal, which is input to external interrupt input terminal all the way
INT, triggering CPU generate interruption, and the interrupt routine recording reset types of CPU are software reset.Meanwhile the pulse signal another way
Hand-reset end MR is inputted after delayed circuit, after reset chip receives the pulse signal, is generated by reset output terminal Rst
Reset signal, and it is input to the RESET input Reset of CPU, realize the reset of CPU.Equally, delay circuit is used for as CPU's
Interrupt routine records soft and hardware status information, or reserves time enough to form the reset log.The soft and hardware status information
Even CPU has resetted, and after CPU is restarted, still can check, in this way can quick position reset type, Er Qieke
Rapidly to find the root of exceptional reset according to the soft and hardware status information or the reset log because to solve accurately and in time
The certainly system failure, the normal operation of quick recovery system.
Embodiment three:
Referring to shown in Fig. 3, the present embodiment provides a kind of cpu reset monitoring device again, for carrying out reset control to CPU,
It includes delay circuit and reset chip, which has external interrupt input terminal INT and the RESET input Reset, the reset coil
Piece includes hand-reset end MR and reset output terminal Rst.
In addition, above-mentioned CPU also has watchdog pulse output end WDI, accordingly, reset chip also has house dog input
End WDI and house dog output end WDO, the watchdog pulse output end WDI are connect with the house dog input terminal WDI；It is described
Mono- tunnel house dog output end WDO is connected to the external interrupt input terminal INT, the input terminal company of another way and the delay circuit
It connects.
The cpu reset monitoring device of the present embodiment can realize the monitoring to automatically reset and record, and principle is:
The external interrupt input terminal INT connection on door dog output end WDO mono- tunnel and CPU, the input of another way and delay circuit
End connection.In this way, when CPU occurs abnormal, watchdog pulse output end WDI no signal output, when the timing cycle for reaching WDT
When, house dog output end WDO exports a pulse signal, which is input to external interrupt input terminal INT all the way, triggers
CPU generates interruption, and the interrupt routine recording reset types of CPU are software reset.Meanwhile the delayed electricity of pulse signal another way
Hand-reset end MR is inputted behind road, after reset chip receives the pulse signal, is generated by reset output terminal Rst and is resetted letter
Number, and it is input to the RESET input Reset of CPU, realize the reset of CPU.Equally, the interruption journey that delay circuit is used for as CPU
Sequence records soft and hardware status information, or reserves time enough to form the reset log.The soft and hardware status information is even
CPU has resetted, and after CPU is restarted, still can check.
As it can be seen that present embodiments providing three kinds of different schemes, it can be achieved that hand-reset and/or the monitoring to automatically reset
And record need to only check soft and hardware status information or the reset log before resetting after cpu reset is restarted, it can be accurately
The type of reset is solved, to targetedly debug.
In conclusion above scheme through the invention, after resetting and occurring, can be recorded according to CPU interrupt routine it is soft,
Hardware status information or the reset log, not only can quick position reset type, but also can rapidly find exceptional reset
Root because to solve the system failure, the normal operation of quick recovery system accurately and in time, and reducing system maintenance
Difficulty shortens maintenance time, significantly reduces maintenance cost.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.
Claims (3)
1. a kind of cpu reset monitoring device, including reset chip, the CPU has external interrupt input terminal and the RESET input；
The reset chip includes hand-reset end and reset output terminal；It is characterized by:
The cpu reset monitoring device further includes reset button and delay circuit, and the reset button passes through the delay all the way
Circuit connection is directly connected to the external interrupt and inputs to the hand-reset end, another way and the external interrupt input terminal
End；The reset output terminal of the reset chip is connect with the RESET input of the CPU.
2. cpu reset monitoring device as described in claim 1, it is characterised in that: the reset chip also has house dog defeated
Enter end and house dog output end, the CPU also has watchdog pulse output end, and the watchdog pulse output end is seen with described
Door dog input terminal connection, the house dog output end are connect with the external interrupt input terminal all the way, another way and the delay
The input terminal of circuit connects.
3. a kind of cpu reset monitoring device, including delay circuit and reset chip, the CPU have external interrupt input terminal and
The RESET input；The reset chip includes hand-reset end and reset output terminal；It is characterized by:
The CPU also has watchdog pulse output end, and the reset chip also has house dog input terminal and house dog output
End, the watchdog pulse output end are connect with the house dog input terminal；The house dog output end is connected to described all the way
External interrupt input terminal, another way are connect with the input terminal of the delay circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910369527.4A CN109918223A (en) | 2019-05-06 | 2019-05-06 | Cpu reset monitoring device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910369527.4A CN109918223A (en) | 2019-05-06 | 2019-05-06 | Cpu reset monitoring device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0844575A (en) * | 1994-08-03 | 1996-02-16 | Fujitsu Ltd | Monitor and load control system for cpu |
| CN1109302C (en) * | 1997-10-27 | 2003-05-21 | 摩托罗拉公司 | Circuit and method for retaining data in DRAM in portable electronic device |
| CN1945555A (en) * | 2006-11-01 | 2007-04-11 | 华为技术有限公司 | Method and device for preventing internal storage data from losing |
| US20140304538A1 (en) * | 2013-04-07 | 2014-10-09 | Sony Corporation | Method and device for prolonging sleeping time of cpu |
| CN209625194U (en) * | 2019-05-06 | 2019-11-12 | 深圳市钮为通信技术有限公司 | Cpu reset monitoring device |
-
2019
- 2019-05-06 CN CN201910369527.4A patent/CN109918223A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0844575A (en) * | 1994-08-03 | 1996-02-16 | Fujitsu Ltd | Monitor and load control system for cpu |
| CN1109302C (en) * | 1997-10-27 | 2003-05-21 | 摩托罗拉公司 | Circuit and method for retaining data in DRAM in portable electronic device |
| CN1945555A (en) * | 2006-11-01 | 2007-04-11 | 华为技术有限公司 | Method and device for preventing internal storage data from losing |
| US20140304538A1 (en) * | 2013-04-07 | 2014-10-09 | Sony Corporation | Method and device for prolonging sleeping time of cpu |
| CN209625194U (en) * | 2019-05-06 | 2019-11-12 | 深圳市钮为通信技术有限公司 | Cpu reset monitoring device |
Non-Patent Citations (1)
| Title |
|---|
| 陈晓风: "MCS-51系统外部中断响应频率的测试与研究", 福建师范大学学报(自然科学版), no. 03, pages 25 - 27 * |
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Effective date of registration: 20210224 Address after: 518000 R & D building 2002, block a, building 7, Vanke Cloud City Phase I, Xingke 1st Street, Xili community, Xili street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: SHENZHEN YOUHUA TECHNOLOGY Co.,Ltd. Address before: 518000 room 1203, entrepreneurship Park, Lishan road University Town, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Applicant before: SHENZHEN NIUWEI COMMUNICATION TECHNOLOGY Co.,Ltd. |