JPH084253B2 - Time division multiplex transmission method - Google Patents

Description

The present invention relates to a multiplex transmission method, and more particularly to a time division multiplex transmission method suitable for transmitting a plurality of signals having different source frequencies (that is, different transmission rates). .

[Conventional technology]

In the conventional multiplex transmission method of this type, as described in JP-A-59-110239, analog input signals of a plurality of channels are converted into digital signals, and sequentially shifted clocks generated by one oscillation source are generated. By using the latch, it is converted into serial data, and a synchronization signal or the like is further added to this to form a transmission signal. Since the A / D conversion circuit and the multiplexing circuit operate with one oscillation source, the serial data is always the first signal source output, the second signal source output, ...
... A fixed array such as the nth signal source output, which is composed of a synchronization signal and these signal source outputs
The frame has always been a cycle of the oscillation source frequency.

[Problems to be solved by the invention]

In the above-mentioned prior art, no consideration has been given to the case where the input signal is a digital signal and the case where each signal source operates by its own source.

It is an object of the present invention to provide a time division multiplex transmission method capable of accurately transmitting a plurality of signal source outputs having different oscillation sources to a receiving side.

[Means for solving problems]

The above-mentioned object is to perform time-axis compression of data having different transmission rates from different signal sources according to the transmission rates, respectively, and select the data that have been time-axis compression processed in the order of time-axis compression processing. While the time division multiplex signal is selected and synthesized, the time information indicating the time from the time axis compression process to the selective synthesis is generated for each data in the time division multiplex signal. It is achieved by adding

Further, it is achieved by receiving the time division multiplexed signal, extracting the time information from the received signal, and controlling the timing of the data for the time information according to the time information.

[Action]

For example, when data from a plurality of signal sources with different transmission rates are time-axis compressed and combined to form a time-division multiplexed signal, such as a digital audio playback device such as a CD or DAT, when these signals are transmitted from these signal sources, Since the timing of data is different and the time length per frame is also different, when the time axis compression is performed by the time axis compression circuit, the transmission rate also changes, and the time required for the time axis compression process is different for each data. Different to On the other hand, when synthesizing the time-axis-compressed data to generate a time-division multiplexed signal,
Even if another data (data 2) is time-axis compressed while a certain time-axis compression-processed data (data 1) is selected, the data 2 is stored until data 1 is selected. Must have choice. Therefore, when time-division multiplexed signals are generated by selecting and synthesizing these time-compressed data in the order of their compression processing, the timing of each time-axis-compressed data is shifted by the selected waiting time. .

In such a case, the present invention makes it possible to know the waiting time until selection for time division multiplexing from the time information.

Also, on the receiving side, time information is extracted from the received time division multiplexed signal, and the timing of the data in this time division multiplexed signal is controlled according to this extracted time information. In this way, the original data having no phase shift is restored.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram for explaining the first basic configuration of a transmission circuit in the time division multiplexing transmission method according to the present invention, which has different oscillation sources 11-1, 11-2, ... 11-n. The signal sources 12-1, 12-2, ... 12-n have different transmission rates. The outputs of these signal sources 12-1, 12-2, ... 12-n are respectively compressed by time axis compression circuits 13-1, 13-2 ,. To be done. The synthesizing circuit 261 has its own oscillation source 150, and switches and outputs the input data at a transmission rate based on the frequency of the oscillation source 150. The output serial data is
It is transmitted at a constant transmission rate of the oscillation source 150. Further, the synthesizing circuit 261 detects the transmission rates of the signal sources 12-1, 12-2, ... 12-n, generates a data pattern such that each transmission rate can be restored on the receiving side, and is multiplexed. It has a function of arranging on serial data.

FIG. 2 is a block diagram showing in detail the synthesizing circuit in FIG. 1, and in the synthesizing circuit 261 in FIG. 1, the synchronization signal pattern of each signal source is added to the serial data and the signal source of the transmitting side is added. This is an example of transmitting a transmission rate.

In the figure, 12-1, 12-2, ... 12-n are signal sources having different oscillation sources 11-1, 11-2 ,.
The outputs of the signal sources 12-1, 12-2, ... 12-n are compression circuits 13-1, 13-2 ,.
Is input to and compressed. Compression circuit 13-1, 13-2, ...... 13
The output of −n is the synchronizing signal generation circuit 14 of each signal source.
−1, 14-2, ... 14-n and the output of the switching circuit 260, and an oscillation source 150 different from the oscillation sources 11-1, 11-2 ,. The switching circuit 2 by the control circuit
Reference numeral 60 is for switching the output signal to any data or synchronizing signal.

FIG. 3 is a timing chart for explaining the operation when there are two signal sources in FIG. 2, and A1 and B1 are digital signal outputs of the respective signal sources. These signals A1, B1
Are data detection sync signals a1, b1 and data a2,
It is formed by b2, and the compressed signals of A2 and B2 are input to the switching circuit 6. At the same time, the synchronizing signals A3 and B3 of the respective signal sources are also input to the switching circuit 6. The control circuit 170 operates such that the compressed data of A2 and B2 is output from the earliest fixed one in order to be the switching circuit output, but the sync signal is preferentially output on the serial data. In the serial data C1 output from the switching circuit 260 and its enlarged C2,
C1 receives data a3 and sync signal a4 at the same time,
The sync signal pattern a4 is output, and then a3 is output.
Since the synchronizing signal b4 and the data b3 are input to the switching circuit during the output of a3, the data 3a outputs the third a3n, the a3n + 1 is held in the switching circuit 6, and the synchronizing signal pattern b4 is output first. The data of a3 after a3n + 1 is output after waiting for the output of b4, and the data of b3 is output after the data of a3 is output. In this way, since the synchronization signal pattern is preferentially arranged on the serial data, it is possible to transmit the transmission rate of the signal source almost accurately within 1 word of data and 1 clock of error.

FIG. 4 is a timing chart for explaining the operation when a plurality of synchronizing signals are simultaneously input to the switching circuit. In this case, as shown in the serial data D1 and the enlarged D2, like the data, it is also possible to provide priority levels to the respective synchronization signals A4, B4, C4, and to arrange the synchronization signals, but the more synchronization signals overlap, For those with low priority, there is a large delay, so the cycle changes, making it impossible to accurately convey the transmission rate. Therefore, if the number of signal sources is large, insert another sync signal pattern d5 as shown in D3, and set it as a pattern that allows you to know which signal source sync signal exists at the same time. The transmission rate of the signal source can be stored above. Second
In the embodiment described with reference to FIG. 3 and FIG. 3, the timing is such that the output of the compression circuit is fixed at the same time as the synchronization signal
The synchronization signal is added for the purpose of reproducing the transmission rate on the receiving side. The signal sources 12-1, 12-2, ...
As long as it is formed of 12-n oscillation sources 11-1, 11-2, ... 11-n, it does not depend on the timing at which the compression circuit output is determined.

FIG. 5 is a block diagram showing a second basic configuration of the transmission circuit in the time division multiplex transmission method according to the present invention.
This is an example of dividing 11-1, 11-2, ... 11-n to generate a synchronization signal.

In the figure, 16-1, 16-2, ... 16-n are frequency dividers,
Each output is applied to the control circuit 170. The same reference numerals as those in FIG. 1 correspond to the same functional parts. Here, in addition to a frame synchronization signal for performing time division multiplexing and error correction processing, a synchronization signal for sending a data transmission rate is separately added, and a frequency division signal is separately added. . By increasing the frequency division ratio of the frequency dividers 16-1, 16-2, ... 16-n, it is possible to reduce the period error due to sampling by the clock 150.

FIG. 6 shows the function of the frequency divider in FIG.
11-2, ... 11-n or compression circuit 13-1, 13-2, ... 13-n
Was brought to.

FIG. 7 is a block diagram showing a first basic configuration of a transmission circuit in the time division multiplexing transmission method according to the present invention, in which 180 is a separation circuit, 190 is a signal processing circuit, and 410 is a timing circuit.

In the figure, the transmitted serial data is separated into a synchronizing signal and data by a separating circuit 180. The separated sync signal and data are now one of the transmitter signal sources.
One is selected. The selected sync signal is the timing circuit
The transmission rate signal processing circuit 190 of the signal source on the transmission side by 410
Can be controlled to restore the transmitter signal source output.
In this receiving circuit, when the signal source output compression method on the transmitting side is the same for all signal sources, only one signal processing circuit 190 on the receiving side is required, and the circuit scale is small. Also, by providing a large number of this receiving circuit, it is possible to obtain signals of multiple channels at the same time.

FIG. 8 is a block diagram showing the details of the separation circuit in FIG. 7, and 211 is a clock reproduction circuit, 22-1 to 22-n.
Is a pattern detection circuit, 23-1 to 23-n is a protection circuit, 34-
4 to 34-n are switches, 315 is an OR circuit, and 316 is an AND circuit. Further, FIG. 9 is a timing chart for explaining the operation of FIG.

In FIG. 8, the serial data input to the clock reproduction circuit 21-1 outputs the clock CK and the serial data CI. With respect to the clock CK and the serial data CI, the pattern detection circuits 22-1, 22-2, ... 22-n detect the sync signal patterns corresponding to the respective signal sources, and the protection circuits 23-1, 23
-2, ... 23-n, and outputs a signal that goes low when there is a sync signal and goes high when there is no sync signal. The synchronizing signals thus separated are input to the timing circuit 410 by selecting only the signals to be received by the switches 34-1, 34-2, ... 34-n. On the other hand, the output clock CK of the clock reproduction circuit 211 is the protection circuits 23-1, 23.
-2, ... 23-n outputs (D1 and D2 in FIG. 9) are ANDed by the OR circuit 315 and the AND circuit 316 to obtain a clock when a sync signal is present. By using the signal CK1 which does not exist as the clock of the signal processing circuit 190, the synchronizing signal is separated and the data is reproduced.

FIG. 10 is a block diagram showing the basic configuration of the time division multiplex transmission method according to the present invention using the above transmission circuit and reception circuit in the case where the transmission side signal source is a digital audio reproduction device. CD player, 118 is DAT recorder, 1
19 is a BS tuner, 113-1, 13-2, 13-3 are compression circuits, 14
-1,14-2,14-3 are synchronization signal generators, 150 is an oscillation source, 1
70 is a control circuit, 260 is a switching circuit, 320 is a modulation circuit, and 240 is a light emitting element. Further, 250 is a light receiving element, 265 is a demodulation circuit,
180 is a separation circuit, 190 is a signal processing circuit, 270 is a D / A conversion circuit, 280 is an LPF, 410 is a timing circuit, and 290 is an output terminal.

In the figure, the sampling frequency of each of the digital audio reproducing devices is 44.1 KHz for the CD player 117, 48 KHz for the DAT recorder 119, and 32 KHz for the BS tuner 119, which have different oscillation sources. These signal sources are connected to the time division multiplexer of the present invention by PCM data, modulate the output of the switching circuit 260, and then transmit as optical signals by the light emitting element 240. Even when the number of signal sources increases, the above-mentioned transmission is transmission of a modulated serial signal, so that the light emitting element 1
It is possible to transmit a large number of signals by one, and the energy of the light emitting element that can be used by the number of signal sources is not limited as in the case of transmitting a frequency multiplexed signal. Therefore, the light emitting element allows the service area of the light emitting element. Can be kept to a maximum.
On the receiving side, the signal received by the light emitting element 250 is demodulated by the demodulation circuit 265.
Demodulate to serial data with and select one of the signal sources on the transmitting side according to the synchronization signal obtained from the separation circuit 8 to reproduce it.
An audio output is obtained at the output terminal 290 via the conversion circuit 27 and the LPF 280. By using a plurality of the receiving circuits, it is possible to select a desired signal source depending on a place apart from the transmitting circuit, and many people can obtain audio outputs of different signal sources from one system at the same time.

FIG. 11 is a block diagram showing the basic structure of the time division multiplex transmission method according to the present invention using the above transmission circuit and reception circuit when the transmission side signal source is a digital audio reproduction device. CD, 118 is DAT, 119 is BS tuner,
13-1 to 13-3 are compression circuits, 14-1 to 14-3 are synchronization signal generation circuits, 150 is an oscillation source 170 is a control circuit, 260 is a switching circuit, 340 is a modulation circuit, 400 is a recording medium, and 350 is Demodulation circuit, 1
80 is a separation circuit, 190 is a signal processing circuit, 270 is a D / A conversion circuit, 280 is an LPF, 410 is a timing circuit, and 290 is an output terminal.

In the figure, the multiplexed serial data is recorded on the recording medium 400, and the signal recorded on the recording medium 400 is taken out as an audio output. Since the recording signals are time-division multiplexed, the listener can select and listen to a desired signal by switching the separation circuit 180, and can record a large number of signals on one recording medium.

INDUSTRIAL APPLICABILITY The present invention is a time division multiplexing system and apparatus effective when the oscillation sources owned by the signal sources are different. Therefore, the signal sources do not necessarily have to output digital signals, and even when they are analog signals. It is valid.

FIG. 12 is a block diagram showing a transmission circuit in an embodiment of the time division multiplex transmission method according to the present invention. The same reference numerals as those in FIG. 6 correspond to the same parts, and 810 is an error detection circuit.

The one shown in the figure transmits the transmission rate of the signal source by adding the error data of the period formed by the synchronization pattern and the oscillation source and the repetition period of the synchronization pattern to the compressed data on the serial data. 3 is an example of a transmission side circuit of a time division multiplexing device that performs

The outputs of the signal sources 12-1, 12-2, ... 12-n are compression circuits.
The data is compressed by 13-1, 13-2, ... 13-n, and is input to the switching circuit 260 in order from the one that has been compressed earlier and placed on the serial data. Here, when the compression of the data B1 is completed while the compressed data of the data A1 is input to the switching circuit 260 and is being output as serial data, the control circuit 170 controls the switching circuit 260 until the switching circuit 260 finishes outputting the data. The output circuit of the compression circuit of data B1 is held, and the compression output data of data B1 that was held after that is switched.
260 outputs. Therefore, the repetition cycle on the serial data of the compressed data of the data B1 that is input to the switching circuit 260 later is shifted from the cycle formed by the oscillation source of the signal source, and The transmission rate information is lost. Therefore, compression circuits 13-1, 13-2, ...
The error detection circuit 810 detects the difference between the time when the 13-n outputs the compressed data and the output of the synchronization signal generation circuits 14-1, 14-2, ... 14-n, and outputs the error data to the switching circuit. Circuit configuration. As a result, the data is transmitted with the sync signal pattern and the error data added, and the receiving side corrects the timing by using the error data when reproducing the sync signal, thereby ensuring an accurate transmission rate. Can be played.

FIG. 13 is a timing chart for explaining the operation of FIG. 12, where A2 and B2 in the case where there are two signal sources are the data after compressing the signal source outputs. When the data a having the synchronization signal a _s is determined and the data b having the synchronization signal b _s is determined while being input to the switching circuit 260 (FIG. 12), the data b is output until the data a is output. Wait T. The error detection circuit 810 (FIG. 12) detects the deviation amount T, generates error data, and adds the error data pattern b _m on the serial data E. As the data a, also the error data in which no deviation is added to a _m as an indication of T = 0.

FIG. 14 is a block diagram showing a receiving circuit for the transmitting circuit shown in FIG.
Is a signal processing circuit, 820 is a sync signal pattern detection circuit, 830
Is a transmission rate reproducing circuit, and 410 is a timing circuit.

The clock reproduction circuit 211 which receives the serial data outputs the data and the reproduced clock. Synchronous signal pattern detection circuit 820 with this clock and data as input
Then, the data synchronization signal is reproduced. Since this synchronizing signal has a shift amount generated at the time of multiplexing on the transmitting side, a transmission rate reproducing circuit 830 is provided, an error data pattern is detected from the data output from the clock reproducing circuit 211, and the synchronizing signal pattern The sync signal output from the detection circuit 820 is temporally modified to reproduce the transmission rate of the transmission-side signal source. The timing circuit 410 generates a necessary clock based on the reproduced transmission rate, controls the signal processing circuit 190, expands data, and reproduces the transmission signal source output at the transmission rate of the signal source.

FIG. 15 is a block diagram showing an example of the configuration of the transmission rate reproducing circuit in FIG. 14, in which 291 to 292 are input terminals and 831.
Is an error data detection circuit, 840 is a counter, 850 is a decoder, 860 is a PLL circuit, 293 is a clock input terminal, and 294 is an output terminal. 16 is a timing chart of the transmission rate reproduction circuit of FIG.

15, a counter 840 is provided with a sync signal S ₁ (see FIG. 16) reproduced by a sync signal pattern detection circuit 820 (FIG. 14).
(Fig.) Is input from the input terminal 291. Sync signal S ₁ (16th
In the figure, there is a shift of T ₁ , T ₂ , ... T _n that occurs when multiplexing is performed on the transmission side. In order to correct the synchronization signal S ₁ , error data is detected from the data input to the input terminal 292 in FIG. 15 by the error data detection circuit 831 and T ₁ , T ₂ , ...
... The deviation amount of T _n (Fig. 16) is loaded as the offset amount of the counter 840. The counter 840 is a clock reproduction circuit 2
A value obtained by subtracting the amount of deviation from the period T (Fig. 16) indicating the transmission rate of the transmission side signal source from the time when the pulse of the synchronization signal S ₁ is input by the clock output from Fig. 11 (Fig. 14). A pulse is generated by counting only, and an accurate synchronization signal like S ₀ can be obtained through the PLL circuit 860, and the transmission rate of the transmission side signal source is reproduced.

In the above embodiments, since the data pattern on the multiplexed serial data exists discretely on the time axis, if a signal that is easy to reproduce by a clock is put in the portion where the data pattern does not exist, the reception is possible. It is possible to prevent malfunction in the clock reproduction circuit 211 (FIG. 1) on the side. If error data causes a data error on the transmission path, the cycle information will not be accurately transmitted.
The error detection circuit in the figure is further provided with an additional function of an error correction code to enhance the correction capability, and the error data is not sent only once as shown in FIG. 13, but the control circuit in FIG. It is conceivable that the error data is sent out a plurality of times by 170, and by providing such processing, it is possible to receive it more accurately.

FIG. 17 is a block diagram showing a transmitting circuit in a modification of the time division multiplexing transmission method according to the present invention, which is 87-1 to 87-n.
Is a counter, and the same reference numerals as those in the above-mentioned embodiment are parts having the same functions.

In this embodiment, by changing the temporal compression rate of a plurality of signal sources for each signal and for each frame, a transmission circuit for transmitting at a constant transmission rate of a time-division multiplexed transmission signal is provided. Here is an example. In this embodiment, the transmission rate of each signal source can be reproduced on the receiving side by adding a data pattern indicating each compression rate to the transmission data pattern.

FIG. 18 is a timing chart for explaining the operation of FIG.

The operation of the transmission circuit of FIG. 17 will be described with reference to the timing chart of FIG.

When the output of the signal line 12-1 A1, an output B1 of the signal source 12-2 in FIG. 18, during data A1 is time T _0, composed of several bits data a _1, a ₂ , ...... a n-number of _n as it is present, b ₁ is data in the data B1 is time _{T 0, b 2, ...... b} m
Of m exist. This data is respectively compressed by the compression circuit 13
It is compressed by 1,132, ... 13n (Fig. 17), but if the compression rate is, for example, one data, the ratio corresponding to one clock of the clock F _ck generated by the oscillation source 150 of the control circuit 170 compression ratio on the axis roasted by a signal source, a _1, a ₂ of A1,
The data a, which is the compressed a _n , is F _ck , n clock, b _{1 of} B2,
The data b compressed b ₂ , ... b _n becomes the data of the time length of F _ck , m clock and becomes the transmission signal with the constant transmission rate using the clock F _{ck. In} this case, the converted serial data is 1
It is completed at frame T ₀ . When these signals are serial data, the synchronization signals g ₁ , g ₂ , ...
G _n is added, but T ₀ that indicates the compression rate together with the synchronization signal
The signals g _m1 , g _m2 , ... G _mn indicating the number of data in the frame are added, and the frame synchronization signal g ₀ is also added.

In the compression circuits 13-1, 13-2, ... 13-n in FIG. 17, the compression rate on the time axis changes depending on the transmission rate as described above. Since the number varies depending on the signal source and also varies depending on the cycle, the number of data within a fixed time is counted by counters 87-1, 87-2, ...
87-n is counted and this output is input to the switching circuit 260 as compression rate data. The switching circuit 260 receives the synchronizing signals of the synchronizing signal generating circuits 14-1, 14-2, ... 14-n outputs and the compression circuits 13-1, 13-2 ,.
These signals are switched and output by 0, and the serial data G shown in FIG. 18 is output.

FIG. 19 is a block diagram of a receiving circuit for receiving the data transmitted by the transmitting circuit of FIG. 17, in which 211 is a clock reproducing circuit, 191 is a signal processing circuit, 880 is a synchronous signal detecting circuit, and 861 is a phase comparison circuit. , 862 is VOC, 863 is a frequency divider.

In the figure, the transmission serial data is input to the clock reproduction circuit 211, reproduces the clock, and outputs this clock and the data. A sync signal detection circuit 880 detects a frame sync signal or a sync signal for each data from this data and the clock, and detects the sync signal for each phase comparator 861 and VCO8.
The timing is input by inputting it to the PLL circuit composed of the frequency divider 62 and the frequency divider 863, but if the frequency division ratio of the frequency divider 863 is determined by the compression rate data detected by the signal processing circuit 191, one data is obtained. Therefore, the transmission rate of the signal source on the transmission side can be obtained, and the signal can be reproduced at the transmission rate on the transmission side.

In the serial data G of FIG. 18, the data is arranged continuously in the same figure, but in the case of the present embodiment, the number of data compressed according to the cycle is not always constant, and it is compressed. The data length is also not constant. Therefore, if the frame period T ₀ is to be obtained by the sync signal pattern added to each data, a shift occurs due to the period. In this case, a correct value can be obtained by obtaining T _{0 according} to the frame synchronization signal. When the number of signal sources is limited to the maximum K, the period T ₀ is divided into channels in time, and when the signals are arranged at predetermined positions in the frame, the synchronization signal of each data Can also obtain the period T ₀ .

〔The invention's effect〕

As described above, according to the present invention, data of different signal sources of oscillation sources can be transmitted to the receiving side, and the output of the transmitting side signal source can be transmitted to the receiving side to generate time-division multiplexed signals. Even if the data timing fluctuates, it is possible to reproduce at the timing of the transmission-side signal source, and no malfunction occurs. Further, since the transmission rate of the serial data to be transmitted is always constant, the configuration such as clock reproduction rotation on the receiving side can be facilitated. A division multiplexing method can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first basic configuration of a transmission circuit in the time division multiplex transmission method according to the present invention, and FIG. 2 is a configuration diagram showing in detail the synthesizing circuit in FIG. 1, FIG. 3 and FIG. Four
FIG. 5 is a timing diagram of the transmission circuit of FIG. 2, FIG. 5 and FIG.
FIG. 7 is a block diagram showing the second basic configuration of the transmission circuit in the time division multiplex transmission method according to the present invention, and FIG. 7 is a block diagram showing the first basic configuration of the transmission circuit in the time division multiplex transmission method according to the present invention. Fig. 8 and Fig. 8 are block diagrams showing the details of the separation circuit of Fig. 7, Fig. 9 is a timing diagram of Fig. 8, and Figs. 10 and 11 are cases where the transmitting side signal source is a digital audio regenerator. 12 and 13 are block diagrams showing the basic configuration of the time division multiplex transmission method according to the present invention using the transmitting circuit shown in FIGS. 1, 5, and 6 and the receiving circuit shown in FIG.
FIG. 13 is a block diagram showing a transmitting circuit in an embodiment of a time division multiplex transmission method according to the present invention, FIG. 13 is a timing diagram of FIG. 12, and FIG. 14 is a block of a receiving circuit for receiving the output of FIG. FIG. 15 is a block diagram showing an example of the configuration of the transmission rate reproducing circuit of FIG. 14, FIG. 16 is a timing diagram of the receiving circuit of FIG. 15, and FIG. 17 is a time division multiplex transmission method according to the present invention. FIG. 18 is a block diagram showing a transmitting circuit in a modified example, FIG. 18 is a timing diagram of FIG. 17, and FIG. 19 is a block diagram of a receiving circuit for receiving the output of the transmitting circuit of FIG. 11-1, 11-2, 11-n ... Oscillation source, 261, ... Combining circuit, 12
-1,12-2,12-n ... Signal source, 13-1,13-2,13-n ...
Compression circuit, 170 ... Control circuit, 14-1, 14-2, 14-n ...
Synchronous signal generation circuit, 260 ... switching circuit, 180 ... separation circuit, 190 ... signal processing circuit, 410 ... timing circuit.

(72) Hiromichi Tanaka, Inventor Hiromichi Tanaka, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Home Appliances Research Laboratory, Hitachi, Ltd. (56) References JP 62-7237 (JP, A)

Claims (2)

[Claims] 1. A time-division multiplex transmission method for multiplexing and transmitting and reproducing data having different transmission rates from a plurality of signal sources having different oscillation source frequencies, the data from each of the signal sources Each is time-axis compressed according to its transmission rate, and the time-axis compressed data is selected and combined in the order in which the time-axis compression processing is performed while waiting for the selection end of the data that has been time-axis compression processed first. To generate a time-division multiplexed signal, and for each time-axis-compressed data in the time-division multiplexed signal, calculate the time from the end of the time-axis compression processing of the data to the selective combination. A time division multiplex transmission method, characterized in that the time information shown is added and the time division multiplex signal added with the time information is used as a transmission signal. 2. A time division multiplex transmission method for multiplexing and transmitting and reproducing data having different transmission rates from a plurality of signal sources having different oscillation source frequencies, the data from each of the signal sources Each is time-axis compressed according to its transmission rate, and the time-axis compressed data is selected and combined in the order in which the time-axis compression processing is performed while waiting for the selection end of the data that has been time-axis compression processed first. To generate a time-division multiplexed signal, and for each time-axis-compressed data in the time-division-multiplexed signal, the time from the end of the time-axis compression processing of the data until the selective combining is performed. The time information represented is added, the time division multiplexed signal to which the time information is added is used as a transmission signal, the time information is extracted from the received transmission signal, and the timing of the data with respect to the extracted time information The The issued and controlled in accordance with the time information, division multiplex transmission method when the timing of the data and returning to the timing before the selection combining.