JPH0837631A - Drive circuit for display device - Google Patents

Abstract

PURPOSE:To give no adverse influence to a display device even when a different system is applied to a drive circuit by discriminating the polarity inverted signals of the same cycle which are inverted in a prescribed cycle in the cyclic periods of vertical synchronizing signals of both NTSC and PAL standard systems and then applying these polarity inverted signals to the display device. CONSTITUTION:An AND gate 15 takes an AND between a control signal P11 and a pulse P11 which is obtained by inverting a vertical synchronizing signal PV and outputs a pulse P16. A latch circuit 5 outputs a pulse P17 which is synchronized with the phase of a clock pulse CKH by the timing of the pulse P16 to an OR gate circuit 6. Meanwhile a self-reset pulse P5 of a counter 3 is supplied to the other side of the circuit 6. Thus the circuit 6 outputs the reset pulses P12 of the counter 3 and supplies to the counter 3 and a divider 7. The pulse P12 resets the counter 3. The divider 7 outputs a pulse P8 which is obtained by applying 1/2 division to the pulse P12, and the pulse P8 serves as the polarity inverted signal, etc., of a display device 10 that requires the AC drive.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a matrix type display device such as a liquid crystal display device which needs to be driven by alternating current.

[0002]

2. Description of the Related Art A conventional drive circuit for a display device will be described below with reference to the drawings. The block diagram is shown in FIG. FIG. 4 shows drive waveforms when a PAL system composite video signal is applied to this drive circuit corresponding to the NTSC system, and FIG. 5 shows drive waveforms when an NTSC system composite video signal is supplied.

First, the case where a composite video signal of the NTSC system is given will be described. In FIG. 3, the PLL
A (Phase Locked Loop) oscillator 1 takes in a horizontal synchronizing signal PH obtained from a composite synchronizing signal of NTSC system via a terminal 11, generates an oscillation pulse PLL having a frequency corresponding to the horizontal synchronizing signal PH, and gives it to a horizontal counter 2.

The horizontal counter 2 generates a driving pulse P1 in the horizontal direction based on the oscillation pulse PLL and displays it on the display device 10.
Clock pulse C shown in FIG.
KH is generated and supplied to the vertical counter 3, the latch circuit 4, the latch circuit 5, and the PLL oscillator 1. At this time, the periods of the drive pulse P1 and the clock pulse CKH match the period (1H) of the horizontal synchronizing signal PH included in the NTSC composite synchronizing signal.

The vertical counter 3 has a clock pulse CKH.
Is used as a clock to generate a drive pulse P3 in the vertical direction and apply it to the display device 10. Further, the vertical counter 3 is shown in FIG.
Counting of the number of pulse periods of the clock pulse CKH is started from the time when it is reset by the pulse P7 shown in (). That is, it is counted once in one line period (1H).

When the predetermined number of times N is counted, a pulse P4 is generated and supplied to the latch circuit 4, for example, the pulse P4d of FIG. At this time, as the value of N,
The period for counting N times is set to be slightly longer than one field period (262.5 line period) of the NTSC system, but here the value of N is 284 for simplicity.

The latch circuit 4 synchronizes with the phase of the clock pulse CKH when the pulse P4 rises.
A pulse P5 is generated like the pulse P5d of (U) and is applied to one input terminal of the gate circuit 6.

The latch circuit 5 shown in FIG. 5 has a period of 262.5 line period obtained from the composite synchronizing signal of the NTSC system.
The vertical synchronizing signal PV shown in (E) is taken in from the terminal 12. When the vertical synchronizing signal PV rises, the pulse P6 shown in FIG. 5 (E) is generated in synchronization with the phase of the clock pulse CKH and is applied to the other input terminal of the gate circuit 6. Therefore, the pulse P6 is generated every one field period (262.5 line period) of the NTSC system. The pulse PVd shown in FIG. 5E shows a state in which noise is mixed in, and therefore the pulse P6d does not rise.

The gate circuit 6 takes the logical sum of the pulses P5 and P6 to generate a pulse P7 shown in FIG. 5 (or) and supplies it to the vertical counter 3 and the frequency divider 7.

Since the vertical cycle of the NTSC system is 262.5 line periods, the vertical synchronizing signal PV and the pulse P6 are generated and the pulse P7 rises at time u2 in FIGS. When the pulse P7 rises at time u2, the number of counts by the vertical counter 3 is still 262, so as shown in FIG.
Is not generated yet, the vertical counter 3 is reset in response to the rising edge of the pulse P7 and restarts counting from 0. Therefore, as at times u1, u2, and u3, the pulse P
As long as 7 rises correctly, the pulses P4 and P5 will not be generated.

Even if the pulse P7 does not rise because the noise is not mixed into the pulse PVd and the pulse P6d does not occur at time u4, the vertical counter 3 continues counting, and the count number reaches 284. At this time (time u4 ′), the vertical counter 3 generates the pulse P4 almost without the time u4, so that the pulse P5 is generated and the pulse P7 rises. At this time, the vertical counter 3 resets itself by the rising pulse P7.

The frequency divider 7 displays a pulse P8 obtained by dividing the reset signal P7 by 1/2 as shown in FIG.
Give to 0. In this way, the pulse P8 reverses its polarity every one field period (262.5H) of the NTSC system, and thus is generally used when reversing the field polarity when the liquid crystal display is AC-driven.

On the other hand, a case where the PAL system composite video signal is applied to the drive circuit of FIG. 3 will be described with reference to FIG. In FIG. 3, a PLL oscillator 1 receives a horizontal synchronizing signal PH obtained from a PAL-type composite synchronizing signal as an input terminal 1.
An oscillation pulse PLL that is oscillated at a frequency corresponding to the horizontal synchronization signal PH is generated in synchronization with the pulse CKH that is fetched via 1 and fed back, and is given to the horizontal counter 2.

The horizontal counter 2 generates a driving pulse P1 in the horizontal direction based on the oscillation pulse PLL and displays it on the display device 10.
Clock pulse C shown in FIG.
KH is generated and supplied to the vertical counter 3, the latch circuit 4, the latch circuit 5, and the PLL oscillator 1. At this time, the periods of the drive pulse P1 and the clock pulse CKH match the period of the horizontal synchronization signal PH included in the PAL-system composite synchronization signal, which is the period of the horizontal synchronization signal PH included in the NTSC-system composite synchronization signal. Equal to (1H).

The vertical counter 3 has a clock pulse CKH.
Is used as a clock to generate a drive pulse P3 in the vertical direction and apply it to the display device 10. Further, the vertical counter 3 starts the clock pulse C from the time when it is reset by the pulse P7.
The number of KH pulse periods is counted, and a pulse P4 shown in FIG. 4B is generated and supplied to the latch circuit 4 each time a predetermined 284 times are counted.

The latch circuit 4 synchronizes with the phase of the clock pulse CKH when the pulse P4 rises.
A pulse P5 shown in (v) is generated and applied to one input terminal of the gate circuit 6.

The latch circuit 5 shown in FIG. 4 has a period of 312.5 line periods obtained from the PAL system composite synchronizing signal.
The vertical synchronizing signal PV shown in (E) is taken in via the input terminal 12. When the vertical synchronizing signal PV rises, it is synchronized with the phase of the clock pulse CKH to generate the pulse P6 shown in FIG. 4 (E), which is applied to the other input terminal of the gate circuit 6.

The gate circuit 6 takes the logical sum of the pulses P5 and P6 to generate the pulse P7 shown in FIG. 4 (or) and supplies it to the vertical counter 3 and the frequency divider 7.

Since the vertical period of the PAL method is 312.5 line periods, the time U is set as shown in FIGS.
From 1 to time U2, the pulses P4 and P5 are not generated.
As shown in FIG. 4B, when the number of counts by the vertical counter 3 reaches 284 at time U2, the pulse P
4, P5 are generated, the pulse P7 rises, the vertical counter 3 is reset, and the count is restarted from 0.

At time U3 after a while, the number of re-counts by the vertical counter 3 has not reached 284, but since the vertical synchronizing signal PV and the pulse P6 are generated,
The pulse P7 rises, the vertical counter 3 is reset, and counting is restarted from 0. Since this is repeated after that,
The pulse P7 will occur at times U1, U2, U3, U4, U5.

The frequency divider 7 displays a pulse P8 obtained by dividing the reset signal P7 by 1/2 as shown in FIG.
Give to 0. As described above, the polarity of the pulse P8 used for AC driving the liquid crystal display is not inverted every one field period (312.5H) of the PAL system, and most of the pulse P8 is at "Low" level. Therefore, the time for applying one polarity to the liquid crystal electrode becomes long, and a DC voltage is applied to the liquid crystal when the time average is taken.

[0022]

As described above, the NTSC
When the PAL system composite video signal is supplied to the drive circuit for processing the system system composite video signal, the pulse for AC driving does not invert its polarity in substantially the same cycle, and a DC component is generated. At this time, since the number of scanning lines in the PAL system (312.5 lines in one field) is larger than the number of scanning lines in the NTSC system (262.5 lines in one field), the image displayed on the display device is vertically transformed and displayed. . In particular, when driving a display device that needs to be driven by an alternating current, such as a liquid crystal display device in which a problem such as burn-in occurs when it is driven by direct current, a deformed image is burned into a display element that constitutes a screen such as a liquid crystal, and is displayed. It caused the deterioration of quality.

In order to solve such a problem, the present invention provides a display device capable of AC driving the display device even when a PAL-system composite synchronizing signal is given to the drive circuit of the display device for NTSC system. It is an object of the present invention to provide a driving circuit of the.

[0024]

In order to achieve the above object, a drive circuit of a display device according to the present invention is a drive circuit of a display device for performing display in synchronization with horizontal and vertical sync signals of a standard video signal. A first control signal generating means for generating a first control signal at a timing of passing a vertical synchronization signal of a predetermined standard video signal; a vertical synchronization signal of an input video signal; and the first control signal. The first gate means for outputting a logical product and the count value of the horizontal synchronizing signal of the input video signal are larger than the predetermined vertical cycle of the standard video signal and smaller than the vertical cycle of other standard video signals in advance. A second control signal generating means for generating a second control signal when the predetermined value is reached, and a second logical output of the output of the first gate means and the second control signal. Gate means, and And resetting means for resetting the second control signal generating means by the output of the second gate means,
A frequency dividing means for dividing the output of the second gate means and for deriving an inverted signal for AC driving the display device.

Further, the first control signal generating means counts the horizontal pulses, and the value thereof is later than the generation time of the vertical synchronizing signal of the predetermined standard video signal and the vertical synchronizing signal of another standard video signal. A discrimination counter that generates an output when a predetermined value corresponding to an earlier time point is reached, a first latch circuit that latches an output from the discrimination counter and generates a pulse, and an input video signal Of the vertical synchronizing signal and the output of the first latch circuit, and the gate circuit for resetting the discrimination counter by the logical sum output and the output of the discrimination counter are received and set in advance. It is characterized in that it is configured with a second latch circuit that passes the vertical synchronizing signal of the standard video signal but blocks the vertical synchronizing signal of the other standard video signal and generates the first control signal at the timing. To.

Furthermore, the display device is a liquid crystal display device.

[0027]

According to this structure, when the predetermined standard video signal is the NTSC system, the NTSC is also used for the input terminal.
When the video signal of the system is supplied, the first control signal generating means gives the first control signal P ₁₀ at the timing of passing the vertical synchronizing signal of the NTSC video signal to the first gate means. A signal based on the vertical synchronizing signal given to the first gate means is passed and this signal is given to the second gate means.

On the other hand, the count value of the horizontal synchronizing signal of the input NTSC video signal from the second control signal generating means is the vertical period (262.5H) of the NTSC video signal.
A second control signal is generated when it reaches a predetermined value which is larger and smaller than the vertical period (312.5H) of another standard system, for example, PAL system, and this is supplied to the second gate means.

Since the second gate means takes the logical sum of both the signals inputted and resets the second control signal by this logical sum, the normal operation from the second gate means is NTSC. A signal corresponding to the vertical synchronizing signal of the video signal of the system is generated, and a signal corresponding to the second control signal is generated only when the vertical synchronizing signal is not normally input due to noise or the like.

Therefore, the output of the second gate means becomes a signal having a slightly longer cycle than the vertical cycle only when the vertical sync signal cannot be detected, but normally it has the same cycle as the vertical sync signal of the NTSC system, and is approximately the same. The signal of the interval. In this way, the generated output of the second gate means is divided by 1/2 by the frequency dividing means, so that inverted signals at substantially equal intervals are derived from the frequency dividing means, and the display device is AC driven. It becomes a polarity inversion signal for

When a video signal of a standard system other than a predetermined standard system (for example, NTSC system), for example, a PAL system is input, the first gate means passes the vertical synchronizing signal (262.5H) of NTSC system. Since the gate is opened at the timing, the PAL vertical sync signal (31
2.5H) cannot be passed, and the output of the first gate means normally becomes high level and is given to one input terminal of the second gate means.

At the other input terminal of the second gate means,
A video signal (PAL input from the second control signal generating means)
The horizontal synchronization signal count value of the standard method is longer than the vertical cycle (262.5H) of the video signal of the predetermined standard method (NTSC method in this case), and the other standard method, for example, PA.
When a predetermined value (284H in the embodiment) shorter than the vertical period (312.5H) of the L system video signal is reached,
A second control signal is provided that produces a pulse.

Since the second gate means outputs the logical sum of the input signals, the above-mentioned predetermined value (284 in the embodiment) is used.
The second control signal, which emits a pulse every H), is passed, the second control signal generating means is reset by this, and the second control signal is guided to the frequency dividing means to divide the frequency by 1/2.
Since the second control signal is a signal having an equal pulse interval, the frequency-divided output divided by 1/2 by the frequency dividing means becomes a polarity inversion signal for AC driving the display device which inverts at equal intervals.

As described above, the polarity inversion signal which is inverted at equal intervals regardless of whether the input video signal is a predetermined standard system (for example, NTSC system) or another standard system (for example, PAL system). Can be derived, and becomes a convenient polarity inversion signal when the display device needs AC driving like a liquid crystal display device.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A drive circuit of a display device embodying the present invention will be described with reference to the drawings. The block diagram is shown in FIG. In FIG. 1, the same parts as those shown and described in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In addition, FIG. 2A shows a drive waveform when an NTSC composite video signal is applied to this drive circuit compatible with the NTSC system.
Fig. 2 shows the drive waveform when a composite video signal of the H.264 system is applied.
It shows in (b).

First, the case where a composite video signal of the NTSC system is given will be described. In FIG. 1, when the horizontal synchronizing signal PH obtained from the NTSC composite synchronizing signal is supplied from the input terminal 11, the PLL oscillator 1 oscillates at an oscillation pulse PL oscillated at a frequency corresponding to the horizontal synchronizing signal.
L is generated and given to the horizontal counter 2.

The horizontal counter 2 generates a horizontal drive pulse P1 based on the oscillation pulse PLL to display the display device 10.
To generate a clock pulse CKH and PL
It is supplied to the L oscillator 1, the vertical counter 3, the discrimination counter 13, the flip-flop 17, and the latch circuits 4, 5, 16. At this time, drive pulse P1 and clock pulse CKH
The period of 1 corresponds to the period (1H) of the horizontal synchronizing signal PH included in the NTSC composite synchronizing signal.

The vertical counter 3 has a clock pulse CKH.
Is used as a clock to generate a drive pulse P3 in the vertical direction and apply it to the display device 10. Further, the vertical counter 3 starts counting the number of pulse periods of the clock pulse CKH from the time when it is reset by the reset pulse P12 from the gate circuit 6. That is, 1 in 1 line period (1H)
You will count it. If a predetermined number of times (284 times in this embodiment) is counted, for example, as shown in FIG.
The pulse P ₄ at the time t2 of (or) is generated and supplied to the latch circuit 4.

The latch circuit 4 synchronizes with the phase of the clock pulse CKH when the pulse P4 rises.
A self-reset pulse P ₅ for the vertical counter 3 as shown in (g) is generated and applied to one input terminal of the OR gate circuit 6.

The discrimination counter 13 generates an output P13 with a predetermined count number and supplies it to the latch circuit 16. In this case, the predetermined count number is a count number corresponding to a time later than the generation time of the vertical synchronization signal of the NTSC system and earlier than the generation time of the vertical synchronization signal of the PAL system, and is selected to be 284 counts, for example. . The latch circuit 16 generates a pulse P14 for self-resetting the discrimination counter 13 itself synchronized with the phase of the clock pulse CKH at the timing of the output P13, and supplies the pulse P14 to one input terminal of the OR gate circuit 18.

When the vertical synchronizing signal PV shown in FIG. 2A obtained from the composite video signal of the NTSC system is supplied to the flip-flop 17 from the input terminal 12, the vertical synchronizing signal P is generated.
V is delayed by the flip-flop 17 and becomes a pulse P15 of FIG. 2B which is phase-synchronized with the clock pulse CKH, which is one field (26) of the composite synchronization signal from the signal source.
The signal is generated every 2.5 H). This pulse P15
Is supplied to the other input terminal of the OR gate 18.

Therefore, the OR gate 18 outputs the logical sum of the pulse P14 which is the self-reset signal of the discrimination counter 13 obtained from the latch circuit 16 and the pulse P15 which is obtained by delaying the vertical synchronizing signal from the flip-flop 17, and this. Reset signal CREA of the discrimination counter 13
Is supplied to the reset terminal of the discrimination counter 13. In the case of NTSC reception, when the vertical synchronizing signal is normally input, the pulse P15 based on the vertical synchronizing signal resets the discrimination counter 13 and the latch circuit 16 does not output the pulse P14. When it is not input, an output pulse P14 of the latch circuit 16 is generated, and the pulse P14 resets the discrimination counter 13.

In the case of PAL reception, the reset signal is reset twice by the vertical synchronizing signal and the pulse P14 when the vertical synchronizing signal is normally input, and reset by the pulse P14 when the vertical synchronizing signal is not input.

The latch circuit 14 outputs a discrimination pulse P10 for passing a pulse P11 obtained by inverting the vertical synchronizing signal PV of FIG. 2A supplied from the input terminal 12 based on the output of the discrimination counter 13. The timing of the discrimination pulse P10 of FIG. 2 (c) derived from the latch circuit 14, which is a circuit for generation, is created by the discrimination counter 13 and set to a predetermined value.

The discrimination pulse P10 allows only a desired vertical synchronizing signal (in this case, the NTSC vertical synchronizing signal) to pass, and allows the vertical synchronizing signal PV to slightly shift due to noise. In order to enable the above, the rising edge is set to be slightly earlier than the vertical synchronizing signal, and for example, it is set to the high level between the count number of the vertical counter of 255H and 265H.

The AND gate circuit 15 outputs the pulse P10.
And P11 are ANDed, and the pulse P16 of FIG.
In order to pass the inverted pulse P11 of the vertical synchronizing signal PV generated during the period of the determination pulse P10 and not to pass any signal such as an undesired vertical synchronizing signal generated during the other period. To do.

Therefore, when the composite video signal of the NTSC system is given, as shown in FIG. 2A, the inverted signal of the vertical synchronizing signal PV generated during the period of the determination pulse P10 is the pulse P16 (e). Is taken out as. Figure 2
The pulse P16 is not derived unless the vertical synchronizing signal PV is input due to the noise N generated at time t1 in (a).

On the other hand, when the PAL system composite video signal is applied, the vertical synchronizing signal PV is not generated during the period of the pulse P10 as shown in FIG.
The output of P is high level pulse P as shown in FIG.
It becomes 16.

The latch circuit 5 is the AND gate circuit 1 described above.
2 synchronized with the phase of the clock pulse CKH at the timing of the pulse P16 of FIG.
The pulse P17 shown in FIG.
Supply to one of the input terminals. The other input terminal of the OR gate circuit 6 is supplied with the self-reset pulse P5 of the vertical counter 3 shown in FIG.

Therefore, the OR gate circuit 6 uses both the pulses P
5 and P17 are ORed to output the reset pulse P12 of the vertical counter 3 shown in FIG. 2C, which is supplied to the reset terminal of the vertical counter 3 and the CK terminal of the frequency divider 7. As a result, the vertical counter 3 receives the self-reset signal P5 in FIG. 2 (ki) as well as the pulse P17 in FIG. 2 (o) which is a vertical reset signal by the composite synchronizing signal from the signal source. Will be reset.

Noise N is generated in the vertical synchronizing signal PV from the signal source of FIG. 2A at time t1 and the vertical synchronizing signal P is generated.
When V is not detected, the reset signal of the vertical counter 3 based on the vertical synchronizing signal PV from the latch circuit 5 is also shown in FIG.
Like the pulse P17 of (o), the pulse is missing at the time t1, but the reset pulse P4 from the vertical counter 3 shown in FIG. It occurs at time t2 when 284 pieces are counted.

As a result, at the timing of the pulse P4, the self-reset pulse P5 of FIG. 2 (K) synchronized with the clock pulse CKH is generated, taken out from the OR gate circuit 6 as the reset pulse P12, and the vertical counter 3 is reset. It is supplied to the frequency divider 7.

That is, the self-reset pulse P5 is necessary for resetting the vertical counter 3 when the vertical synchronizing signal PV is missing due to noise as shown at time t1 in FIG. Therefore, if the normal NTSC signal is input, the self-reset pulse P5 is not generated, and the vertical counter 3 is reset by the pulse P17 of FIG. 2 (e) generated based on the vertical synchronizing signal PV. In the above noise state, the vertical counter 3 is not reset, so that the vertical driving signal malfunctions.

Therefore, if the period of the self-reset pulse P5 is too long, the period during which malfunction occurs and the period during which the display device is affected are long. For this reason, the period of the self-reset pulse P5 is not very long, and as a result, it is longer than one field (262.5 horizontal periods) of the NTSC signal and shorter than one field (312.5 horizontal periods) of the PAL signal. In the present embodiment, the self-reset pulse P5 is generated when the count number of the vertical counter is 284, so that the vertical counter 3 is self-reset.

As described above, the vertical counter 3 includes the pulse P17 of FIG. 2 (e) based on the vertical synchronizing signal PV and the self-reset pulse P5 of the vertical counter 3 of FIG. It is reset by P12.
In this case, the pulse P11 based on the vertical synchronizing signal PV that has not entered the period in which the pulse P10 of FIG. 2 (c) occurs cannot pass through the AND gate circuit 15, and the self-reset pulse P5 is input to reset the vertical counter 3. The reset does not take twice.

In the division cycle 7, the reset pulse P12 is divided by 1/2 to output a pulse P8 shown in FIG. This pulse P8 is, as shown at time t1 in FIG.
When the noise N occurs and the vertical synchronizing signal PV cannot be detected, the pulse width of that portion becomes slightly longer, but as a whole it becomes a signal that is inverted for each field of the composite synchronizing signal, and is AC driven like a liquid crystal display or the like. Can be used for reversing the field polarity of the display device 10 that requires.

Next, a case will be described in which a PAL system composite video signal is applied to the above drive circuit compatible with the NTSC system. In FIG. 1, the PLL oscillator 1 is a PAL
An oscillation pulse PLL oscillated at a frequency corresponding to a horizontal synchronizing signal PH obtained from the composite synchronizing signal of the system is generated and given to the horizontal counter 2.

The horizontal counter 2 generates a driving pulse P1 in the horizontal direction based on the oscillation pulse PLL and displays it on the display device 10.
To generate a clock pulse CKH and
It is supplied to the oscillator 1, the vertical counter 3, the discrimination counter 13, the flip-flop circuit 17, and the latch circuits 4, 5, and 16. At this time, drive pulse P1 and clock pulse CK
The period of H coincides with the period of the horizontal synchronizing signal PH included in the PAL-system composite synchronizing signal, which is equal to the period (1 of the horizontal synchronizing signal PH included in the NTSC-system composite synchronizing signal.
H).

The vertical counter 3 has a clock pulse CKH.
Is used as a clock to generate a drive pulse P3 in the vertical direction and apply it to the display device 10. Further, the vertical counter 3 counts the number of pulse periods of the clock pulse CKH from the time when it is reset by the reset pulse P12 from the OR gate circuit 6, and every time it counts a predetermined 284 times,
The pulse P4 shown in FIG. 2 is generated and supplied to the latch circuit 4.

The latch circuit 4 synchronizes with the phase of the clock pulse CKH when the pulse P4 rises.
A self-reset pulse P5 shown in (a) is generated and applied to one input terminal of the OR gate circuit 6.

The discrimination counter 13 has a predetermined 284
An output P13 is generated by the number of times counted and supplied to the latch circuit 16. The latch circuit 16 has a pulse P1 for resetting the discrimination counter 13 itself synchronized with the phase of the clock pulse CKH at the timing of the output P13.
4 is generated and supplied to one input terminal of the OR gate circuit 18.

When the vertical synchronizing signal PV of FIG. 2 obtained from the PAL-system composite synchronizing signal is supplied to the flip-flop 17 from the input terminal 12, the vertical synchronizing signal PV is delayed by the flip-flop 17 and a clock pulse is generated. CK
The pulse P15 shown in FIG. 2 (a) that is phase-locked to H becomes the field P (31) of the composite sync signal from the signal source.
The signal is generated every 2.5 H).

This pulse P15 is supplied to the other input terminal of the OR gate circuit 18. Therefore, the OR gate circuit 18 outputs the pulse P14 which is the self-reset signal of the discrimination counter 13 obtained from the latch circuit 16 and the pulse P15 which is obtained by delaying the vertical synchronizing signal from the flip-flop 17, and these pulses P1
By 4 and P15, the discrimination counter 13 is continuously reset twice.

The latch circuit 14 generates a determination pulse P10 for passing a pulse P11 which is the inverted vertical synchronization signal PV of FIG. The timing of the discrimination pulse P10 derived from the latch circuit 14 shown in FIG. 2C is created by the discrimination counter 13 and set to a predetermined value.

The pulse P10 for discrimination is designed to pass only the desired vertical synchronizing signal (NTSC vertical synchronizing signal in the case of a drive circuit corresponding to the NTSC system), and the vertical synchronizing signal due to noise. In order to allow the PV to pass even if it is slightly deviated, it rises slightly earlier than the vertical synchronizing signal, and is set to a high level, for example, from 255H to 265H of the count number of the vertical counter.

The AND gate circuit 15 outputs the pulse P10.
And P11 are ANDed, and the pulse P16 of FIG. The inverted pulse P11 of the vertical synchronizing signal PV generated during the period of the determination pulse P10 is passed, and any signal such as an undesired vertical synchronizing signal generated during other periods is not passed. Therefore, when the PAL system composite video signal is given, as shown in FIG.
During the period of the determination pulse P10, the inverted signal of the vertical synchronizing signal PV is hardly generated, and the pulse P16 of FIG. 2 () is at the high level over most of the period.

The latch circuit 5 is the AND gate circuit 1 described above.
2 synchronized with the phase of the clock pulse CKH at the timing of the pulse P16 of FIG.
The pulse P17 shown in FIG.
Supply to one of the input terminals. As described above, the self-reset pulse P5 of the vertical counter 3 shown in FIG. 2A is supplied to the other input terminal of the OR gate circuit 6.

Therefore, the OR gate circuit 6 takes the logical sum of both the pulses P5 and P17 and outputs the reset pulse P12 of the vertical counter 3 shown in FIG. It is supplied to the CK terminal of the container 7. That is, one terminal of the OR gate circuit 6 has
2 except that the vertical synchronizing signal PV and the pulse P10 of FIG.
Since the pulse P17 of (se) is supplied, the self-reset pulse P5 of FIG.
The reset pulse P12 shown in FIG. 2C is generated every 284H from the OR gate circuit 6 at all times.
Is generated and the vertical counter 3 is reset.

The frequency divider 7 sets the reset pulse P12 to 1
The pulse P8 of FIG. This pulse P8 becomes a signal that is inverted every 255H, and the display device 10 that needs AC driving like a liquid crystal display.
Can be used as a signal for reversing the polarity of the above.

[0070]

As described above, according to the present invention, when a video signal of a predetermined standard system (for example, NTSC system) is input, the period of the vertical synchronizing signal is used, and a signal other than the predetermined standard system is used. When a video signal of a standard system (for example, PAL system) is input, a polarity reversal signal having the same cycle, which is reversed at a predetermined cycle between the cycles of the vertical synchronization signals of both standard methods, is input from the input signal inside the drive circuit. It can be automatically discriminated, output and given to the display device.

Therefore, when a signal of a system different from that of the drive circuit is input to the drive circuit of the display device (for example,
Even when a PAL system signal is input to the drive circuit for NTSC), unexpected image printing or display requiring AC drive such as liquid crystal display device because polarity reversal is not normally performed It is possible to prevent a problem that a DC voltage is applied to the device and the display device is adversely affected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a drive circuit of a display device that is an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the drive circuit of the display device according to the embodiment of the present invention.

FIG. 3 is a block diagram of a drive circuit of a conventional display device.

FIG. 4 is a diagram showing drive waveforms when an NTSC composite video signal is applied to a drive circuit of a conventional display device.

FIG. 5 is a diagram showing drive waveforms when a PAL-type composite video signal is applied to a drive circuit of a conventional display device.

[Explanation of symbols]

 2 horizontal counter 3 vertical counter 4 latch circuit 6 OR gate circuit 7 frequency divider 10 display device 13 discrimination counter 14 latch circuit 15 AND gate circuit 16 latch circuit 17 flip-flop 18 OR gate circuit PH horizontal sync signal PV vertical sync signal P4 pulse P5 Self reset pulse P10 pulse P11 pulse P12 reset pulse P17 pulse 1H One line period

Claims (3)

[Claims] 1. A drive circuit of a display device for displaying in synchronism with horizontal and vertical synchronizing signals of a standard video signal, wherein a first control signal of a timing at which a predetermined vertical synchronizing signal of the standard video signal is passed. First control signal generating means for generating, first gate means for outputting a logical product of the vertical synchronizing signal of the input video signal and the first control signal, and counting of the horizontal synchronizing signal of the input video signal. Second control signal generating means for generating a second control signal when the value reaches a predetermined value that is larger than the vertical cycle of the predetermined standard video signal and smaller than the vertical cycle of another standard video signal. And second gate means for outputting the logical sum of the output of the first gate means and the second control signal, and the output of the second gate means for the second control signal generating means. Reset to reset And DOO means, the output of the second gate means divides, a driver circuit of a display device, characterized by comprising a frequency dividing means for deriving an inversion signal for AC driving the display device. 2. The first control signal generating means counts horizontal pulses, the value of which is later than the generation time of the vertical synchronizing signal of the predetermined standard video signal and the vertical synchronizing signal of another standard video signal. A discrimination counter that generates an output when a predetermined value corresponding to an earlier time point is reached, a first latch circuit that latches an output from the discrimination counter and generates a pulse, and an input video signal Of the vertical synchronizing signal and the output of the first latch circuit, and the gate circuit for resetting the discrimination counter by the logical sum output and the output of the discrimination counter are received and set in advance. It is characterized by being configured with a second latch circuit which passes a vertical synchronizing signal of a standard video signal but generates a first control signal of a timing at which a vertical synchronizing signal of another standard video signal is blocked. Driving circuit according to claim 1,. 3. The drive circuit for a display device according to claim 1, wherein the display device is a liquid crystal display device.