JPH0837206A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPH0837206A
JPH0837206A JP6170617A JP17061794A JPH0837206A JP H0837206 A JPH0837206 A JP H0837206A JP 6170617 A JP6170617 A JP 6170617A JP 17061794 A JP17061794 A JP 17061794A JP H0837206 A JPH0837206 A JP H0837206A
Authority
JP
Japan
Prior art keywords
semiconductor device
bumps
manufacturing
bump
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6170617A
Other languages
Japanese (ja)
Other versions
JP2540787B2 (en
Inventor
Naoharu Senba
直治 仙波
Atsushi Nishizawa
厚 西沢
Nobuaki Takahashi
信明 高橋
Teruo Kusaka
輝雄 日下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6170617A priority Critical patent/JP2540787B2/en
Publication of JPH0837206A publication Critical patent/JPH0837206A/en
Application granted granted Critical
Publication of JP2540787B2 publication Critical patent/JP2540787B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • H01L2924/3841Solder bridging
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance reliability in bump connection by reducing variation of the size of bumps in a mounting method of a flip-chip method. CONSTITUTION:A conductive adhesive sheet 1 having B stage characteristics is punched in a solid in a solid state of a low temperature to form a small piece, which is placed on terminals 7 of a heated circuit board 6 and softened and connected to the terminal 7 by generated adhesion to form a bump 8. Next, the electrode pads of a semiconductor chip 11 are positioned on the bumps 8 and placed to heat at 120 to 200 deg.C so that they are connected to each other from a liquefied state to a thermset state, whereby the sizes of the bumps are made uniform to prevent short-circuit between terminals and connection failure between the bumps and electrode pads.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体チップの実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor chip mounting method.

【0002】[0002]

【従来の技術】半導体チップの実装方法の一つとしてバ
ンプを用いたフリップチップ法がある。
2. Description of the Related Art A flip chip method using bumps is one of the methods for mounting semiconductor chips.

【0003】図4は従来の半導体装置の製造方法の第1
の例を説明するための模式的断面図である。
FIG. 4 shows a first method of manufacturing a conventional semiconductor device.
3 is a schematic cross-sectional view for explaining an example of FIG.

【0004】図4に示すように、半導体チップ11に形
成したパッド電極12の上に、めっきや蒸着等により半
田バンプ15を形成し、回路基板6に形成した端子7に
半田バンプ15を位置合わせして半導体チップ11を載
置し、半田バンプ15をリフローして端子7に接合す
る。なお、半導体チップ11および回路基板6の表面に
はポリイミド膜16を設けて保護している。
As shown in FIG. 4, solder bumps 15 are formed on the pad electrodes 12 formed on the semiconductor chip 11 by plating or vapor deposition, and the solder bumps 15 are aligned with the terminals 7 formed on the circuit board 6. Then, the semiconductor chip 11 is mounted and the solder bumps 15 are reflowed to be bonded to the terminals 7. A polyimide film 16 is provided on the surfaces of the semiconductor chip 11 and the circuit board 6 for protection.

【0005】図5は従来の半導体装置の製造方法の第2
の例を説明するための模式的断面図である。
FIG. 5 shows a second method of manufacturing a conventional semiconductor device.
3 is a schematic cross-sectional view for explaining an example of FIG.

【0006】図5に示すように、半田バンプ15の中に
Cuボール17を入れた以外は第1の例と同様の構成を
有しており、半田バンプ15をリフローして端子7に接
合する際にCuボール17をスペーサとして半導体チッ
プ11と回路基板6との間隔を設定できるという利点が
ある。
As shown in FIG. 5, the structure is the same as that of the first example except that the Cu balls 17 are put in the solder bumps 15. The solder bumps 15 are reflowed and bonded to the terminals 7. At this time, there is an advantage that the distance between the semiconductor chip 11 and the circuit board 6 can be set by using the Cu balls 17 as spacers.

【0007】[0007]

【発明が解決しようとする課題】この従来の半導体装置
の製造方法は、半田バンプがめっきや蒸着、スパッタ法
等により形成されるため、そのめっき条件のばらつきや
マスクの開口部の寸法あるいは膜厚のばらつき等の影響
により、大きさの不揃いを生じて図6に示すように半田
バンプ15の過剰な半田が流れ出し、最近の微細化が進
んでいるデバイスでは特にバンプ間の距離も小さくなっ
ているので端子間相互の短絡を生じたり、またバンプの
高さが不揃いになって一部の電極パッドと接続不良を発
生するという問題があった。
In this conventional method for manufacturing a semiconductor device, since the solder bumps are formed by plating, vapor deposition, sputtering, etc., variations in the plating conditions and the size or film thickness of the opening of the mask. 6A and 6B, due to the influence of variations in the size of the solder bumps, excess solder of the solder bumps 15 flows out as shown in FIG. 6, and the distance between the bumps is particularly small in devices that have been miniaturized recently. Therefore, there has been a problem that short-circuiting between terminals occurs, or bump heights become uneven, causing a connection failure with some electrode pads.

【0008】本発明の目的はバンプの寸法を一定にして
端子間の短絡や接続不良等の発生を防止する半導体装置
の製造方法を提供することにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device in which the size of bumps is kept constant to prevent the occurrence of short circuits between terminals and defective connections.

【0009】[0009]

【課題を解決するための手段】本発明の第1の半導体装
置の製造方法は、Bステージ特性を有する導電性樹脂を
シート状に形成した導電性粘着シートを低温の固体状態
で選択的に切断して小片を形成する工程と、前記小片が
軟化して粘着性を呈する温度に加熱した回路基板の端子
上に前記小片を接着してバンプを形成する工程と、前記
バンプ上に半導体チップの電極パッドを位置合わせして
載置し前記バンプを加熱して硬化させ前記バンプを介し
て前記回路基板の端子と前記半導体チップの電極パッド
とを電気的に接続する工程とを含んで構成される。
According to a first method for manufacturing a semiconductor device of the present invention, a conductive adhesive sheet having a conductive resin having B-stage characteristics formed in a sheet shape is selectively cut in a solid state at a low temperature. And forming a small piece, a step of forming the bump by bonding the small piece onto a terminal of the circuit board heated to a temperature at which the small piece is softened and exhibits adhesiveness, and an electrode of a semiconductor chip on the bump. The step of aligning and placing pads, heating and curing the bumps, and electrically connecting the terminals of the circuit board and the electrode pads of the semiconductor chip via the bumps is included.

【0010】本発明の第2の半導体装置の製造方法は、
金属シートの両面に半田膜又は金属膜を形成した積層金
属シートを選択的に切断して小片を形成する工程と、前
記小片を回路基板の端子上に載置してリフローしバンプ
を形成する工程と、前記バンプ上に半導体チップの電極
パッドを位置合わせして載置し前記バンプを加熱リフロ
ーして接合し前記バンプを介して前記回路基板の端子と
前記半導体チップの電極パッドとを電気的に接続する工
程とを含んで構成される。
A second method of manufacturing a semiconductor device according to the present invention is
A step of selectively cutting a laminated metal sheet having a solder film or a metal film formed on both sides of a metal sheet to form a small piece; and a step of placing the small piece on a terminal of a circuit board and reflowing to form a bump And the electrode pads of the semiconductor chip are aligned and placed on the bumps, the bumps are heated and reflowed to be joined, and the terminals of the circuit board and the electrode pads of the semiconductor chip are electrically connected via the bumps. And a step of connecting.

【0011】[0011]

【実施例】次に、本発明について図面を参照して説明す
る。
Next, the present invention will be described with reference to the drawings.

【0012】図1(a)〜(d)は本発明の第1の実施
例を説明するための工程順に示した模式的断面図であ
る。
FIGS. 1A to 1D are schematic sectional views showing the steps in order to explain the first embodiment of the present invention.

【0013】まず、図1(a)に示すように、Bステー
ジ特性を有するエポキシ等の樹脂にAg等の金属微粒子
を混入して厚さ10〜50μmのシート状あるいはテー
プ状に形成した導電性粘着シート1を低温の固体状態に
保持してダイス2とポンチ3を有する打抜機のダイス2
に装着して固定する。
First, as shown in FIG. 1A, a conductive material formed into a sheet or tape having a thickness of 10 to 50 μm by mixing fine particles of metal such as Ag into a resin such as epoxy having a B-stage characteristic. A die 2 of a punching machine which holds the adhesive sheet 1 in a low temperature solid state and has a die 2 and a punch 3.
Attach it to and fix it.

【0014】ここで、Bステージ特性とは、常温以下で
固体状態を示し、常温を超えて40〜80℃程度では粘
着性を示し、100〜200℃で液状化し加熱時間の経
過とともに熱硬化する特性である。
Here, the B stage characteristic means a solid state at room temperature or lower, a tackiness at a temperature of 40 to 80 ° C. above room temperature, liquefaction at 100 to 200 ° C., and thermosetting with heating time. It is a characteristic.

【0015】次に、図1(b)に示すように、ポンチ3
を駆動してダイス2に装着された導電性粘着シート1か
ら小片4を打抜き、ステージ5の上に装着して40〜5
0℃に加熱した回路基板6の端子7に小片4を位置合わ
せし、小片4を小さな荷重(0.1〜5g程度)で端子
7に圧着し、回路基板6の加熱で粘着性を生じた小片4
を端子7に接着固定してバンプ8を形成する。
Next, as shown in FIG. 1B, the punch 3
Is driven to punch a small piece 4 from the conductive pressure sensitive adhesive sheet 1 mounted on the die 2, and is mounted on the stage 5 for 40 to 5
The small piece 4 was aligned with the terminal 7 of the circuit board 6 heated to 0 ° C., and the small piece 4 was pressure-bonded to the terminal 7 with a small load (about 0.1 to 5 g), and the circuit board 6 was heated to produce tackiness. Small piece 4
Are bonded and fixed to the terminals 7 to form bumps 8.

【0016】次に、図1(c)に示すように、半導体チ
ップ11のパッド電極12に形成したボールバンプ13
を回路基板6に形成したバンプ8に対向するように位置
合わせする。
Next, as shown in FIG. 1C, the ball bumps 13 formed on the pad electrodes 12 of the semiconductor chip 11 are formed.
Are aligned so as to face the bumps 8 formed on the circuit board 6.

【0017】次に、図1(d)に示すように、ステージ
5の加熱で軟化されたバンプ8に半導体チップ11のボ
ールバンプ13を圧着した後バンプ8を更に120〜2
00℃まで加熱して液状化から熱硬化まで変化させボー
ルバンプ13とバンプ8を接合する。このように、導電
性樹脂を用いて接合することにより、金属バンプ同志を
接合する場合のフラックスを必要とせず、また、接合材
の量を制御できるため、接合材の流れ出しによる短絡事
故を防止できる。
Next, as shown in FIG. 1D, the ball bumps 13 of the semiconductor chip 11 are pressure-bonded to the bumps 8 softened by the heating of the stage 5 and then the bumps 8 to 120-2.
The ball bumps 13 and the bumps 8 are joined by heating to 00 ° C. and changing from liquefaction to thermosetting. In this way, by using the conductive resin, it is possible to prevent a short-circuit accident due to the flow-out of the bonding material because the flux for bonding the metal bumps is not required and the amount of the bonding material can be controlled. .

【0018】図2は本発明の第2の実施例を説明するた
めの模式的断面図である。
FIG. 2 is a schematic sectional view for explaining the second embodiment of the present invention.

【0019】図2に示すように、カット台14とダイス
2により装着されたテープ状の導電性粘着シート1を低
温の固体状態で真空チャック機能を有するポンチ3aに
より順次カットして小片4を形成すると同時にポンチ3
aに吸着させて保持する。
As shown in FIG. 2, the tape-shaped conductive adhesive sheet 1 mounted by the cutting table 14 and the die 2 is sequentially cut in the solid state at low temperature by the punch 3a having the vacuum chuck function to form the small pieces 4. Punch 3 at the same time
It is adsorbed to a and held.

【0020】以後、このポンチ3aをステージ上で加熱
した回路基板上まで移送し、第1の実施例と同様に回路
基板の端子に小片4を圧着して粘性を生じさせ接着して
バンプを形成する。
Thereafter, the punch 3a is transferred to the circuit board heated on the stage, and the small pieces 4 are pressure-bonded to the terminals of the circuit board to generate viscosity and adhere to form bumps as in the first embodiment. To do.

【0021】この第2の実施例では、打抜き法に比べて
導電性粘着シート1を無駄なく使用でき、コスト低減が
得られる。
In the second embodiment, the electroconductive pressure-sensitive adhesive sheet 1 can be used without waste and the cost can be reduced as compared with the punching method.

【0022】図3(a),(b)は本発明の第3の実施
例を説明するための工程順に示した模式的断面図であ
る。
3 (a) and 3 (b) are schematic sectional views showing the steps in order to explain the third embodiment of the present invention.

【0023】図3(a)に示すように、Au,Cu,A
l等からなる厚さ10〜100μmの金属シート9の両
面にBステージ特性を有する導電性樹脂膜10を10〜
50μmの厚さに形成した積層構造からなる導電性粘着
シートをポンチ3で打抜き小片を形成し、ステージ5の
上に装着して40〜50℃に加熱した回路基板6の端子
7に粘着させバンプ8aを形成する。
As shown in FIG. 3A, Au, Cu, A
10 to 10 μm in thickness of the metal sheet 9 having a thickness of 10 to 100 μm and the conductive resin films 10 having the B-stage characteristics on both sides.
A conductive adhesive sheet having a laminated structure formed to a thickness of 50 μm is punched with a punch 3 to form a small piece, which is mounted on a stage 5 and adhered to a terminal 7 of a circuit board 6 heated to 40 to 50 ° C. 8a is formed.

【0024】次に、図3(b)に示すように、半導体チ
ップ11のパッド電極12とバンプ8aを位置合わせし
て圧着し、バンプ8aを120〜200℃まで加熱して
硬化し、パット電極12とバンプ8aを接合する。
Next, as shown in FIG. 3B, the pad electrodes 12 of the semiconductor chip 11 and the bumps 8a are aligned and pressure-bonded, and the bumps 8a are heated to 120 to 200 ° C. to be hardened, and the pad electrode is then applied. 12 and the bump 8a are joined.

【0025】この実施例では、金属シート9を介在させ
ることにより、半導体チップ11と回路基板6との間隔
を広げることができ、半導体チップ11と回路基板6と
の熱膨張率の相違によって生ずる熱ストレスに対する耐
久性を向上させることができる利点がある。
In this embodiment, the space between the semiconductor chip 11 and the circuit board 6 can be widened by interposing the metal sheet 9, and the heat generated by the difference in the coefficient of thermal expansion between the semiconductor chip 11 and the circuit board 6 can be increased. There is an advantage that durability against stress can be improved.

【0026】なお、第1乃至第3の実施例で説明したB
ステージ特性を有する導電性樹脂に混入する導電性材料
としてはAgの代りにCu,Au,半田等の微粒子又は
微粒状のプラスチック粒の表面にこれらの金属膜をめっ
きしたものを少くとも1種混入して用いても良い。
Incidentally, B described in the first to third embodiments
As the conductive material mixed in the conductive resin having the stage characteristics, in place of Ag, fine particles of Cu, Au, solder or the like, or at least one kind of metal particles plated on the surface of fine plastic particles are mixed. You may use it.

【0027】また、Au,Cu,Al,Ni等からなる
厚さ30〜100μmの金属シートの両面にPb−Sn
合金,Au−Sn合金,Ag−Sn合金,Au,Al,
In等の金属膜を5〜50μmの厚さに形成した積層金
属シートを用いても良く、この場合、積層金属シートか
ら打抜き又はカッティングで形成された小片を回路基板
の端子に塗布したフラックスの粘着性を利用して粘着さ
せ第1のリフロー(ウェットバック)によりバンプを形
成し、このバンプ上に塗布したフラックスを介して半導
体チップの電極パッドと回路基板上のバンプとを合わせ
第2のリフローにより電極パッドとバンプを接合する。
Further, Pb-Sn is formed on both surfaces of a metal sheet made of Au, Cu, Al, Ni or the like and having a thickness of 30 to 100 μm.
Alloy, Au-Sn alloy, Ag-Sn alloy, Au, Al,
A laminated metal sheet in which a metal film of In or the like is formed to have a thickness of 5 to 50 μm may be used. In this case, a small piece formed by punching or cutting from the laminated metal sheet is applied to the terminals of the circuit board to adhere the flux. To form a bump by the first reflow (wetback), and the electrode pad of the semiconductor chip and the bump on the circuit board are combined with each other through the flux applied on the bump to perform the second reflow. Bond the electrode pads and bumps.

【0028】ここで、金属シートの材質とその両面に形
成する金属膜の材質との組合わせは金属間のバリア特性
を考慮に入れる必要があり、その適切な例としてPb−
Sn合金/Cu/Pb−Sn合金,Pb−Sn合金/N
i/Pb−Sn合金,Au/Ni/Au等の組合わせを
挙げることができる。
Here, the combination of the material of the metal sheet and the material of the metal film formed on both surfaces of the metal sheet needs to take the barrier property between the metals into consideration. As a suitable example, Pb-
Sn alloy / Cu / Pb-Sn alloy, Pb-Sn alloy / N
The combination of i / Pb-Sn alloy, Au / Ni / Au, etc. can be mentioned.

【0029】なお、回路基板の端子とバンプとの間又は
半導体チップの電極パッドとバンプとの間にそれぞれバ
リアメタル膜を設けても良い。
A barrier metal film may be provided between the terminals of the circuit board and the bumps or between the electrode pads of the semiconductor chip and the bumps.

【0030】[0030]

【発明の効果】以上説明したように本発明は、Bステー
ジ特性を有する導電性樹脂からなる導電性粘着シートを
小片に切離して回路基板の端子上に接着してバンプを形
成することにより、バンプの厚さおよび量を一定に設定
することができ、導電性接着剤の流れ出しによる端子間
の短絡不良やバンプの高さの不揃いによる接続不良を防
止できるという効果を有する。
As described above, according to the present invention, a conductive adhesive sheet made of a conductive resin having a B-stage characteristic is cut into small pieces and bonded to terminals of a circuit board to form bumps. It is possible to set the thickness and the amount thereof to be constant, and it is possible to prevent a short circuit between terminals due to the flow-out of the conductive adhesive and a connection failure due to uneven bump heights.

【0031】また、バンプの中間層に金属層を設けたも
のでは金属層がコアとなって半導体チップと回路基板と
の間隔を一定に設定でき、金属層の厚さを変えることで
間隔の大きさも任意に設定でき、半導体チップと回路基
板との熱膨張率の相違による熱ストレスの影響を低減で
きるという効果を有する。
Further, in the case where a metal layer is provided as an intermediate layer of the bump, the metal layer serves as a core to set a constant gap between the semiconductor chip and the circuit board, and the gap can be increased by changing the thickness of the metal layer. The thickness can also be set arbitrarily, and the effect of thermal stress due to the difference in thermal expansion coefficient between the semiconductor chip and the circuit board can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明するための工程順
に示した模式的断面図。
FIG. 1 is a schematic cross-sectional view showing the order of steps for explaining a first embodiment of the present invention.

【図2】本発明の第2の実施例を説明するための模式的
断面図。
FIG. 2 is a schematic sectional view for explaining a second embodiment of the present invention.

【図3】本発明の第3の実施例を説明するための工程順
に示した模式的断面図。
3A to 3D are schematic cross-sectional views showing the order of steps for explaining a third embodiment of the present invention.

【図4】従来の半導体装置の製造方法の第1の例を説明
するための模式的断面図。
FIG. 4 is a schematic cross-sectional view for explaining a first example of a conventional method for manufacturing a semiconductor device.

【図5】従来の半導体装置の製造方法の第2の例を説明
するための模式的断面図。
FIG. 5 is a schematic cross-sectional view for explaining a second example of the conventional method for manufacturing a semiconductor device.

【図6】従来の半導体装置の問題点を説明するための模
式的断面図。
FIG. 6 is a schematic cross-sectional view for explaining a problem of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 導電性粘着シート 2 ダイス 3,3a ポンチ 4 小片 5 ステージ 6 回路基板 7 端子 8,8a バンプ 9 金属シート 10 導電性粘着膜 11 半導体チップ 12 電極パッド 13 ボールバンプ 15 半田バンプ 16 ポリイミド膜 17 Cuボール 1 Conductive Adhesive Sheet 2 Dice 3,3a Punch 4 Small Piece 5 Stage 6 Circuit Board 7 Terminals 8,8a Bump 9 Metal Sheet 10 Conductive Adhesive Film 11 Semiconductor Chip 12 Electrode Pad 13 Ball Bump 15 Solder Bump 16 Polyimide Film 17 Cu Ball

───────────────────────────────────────────────────── フロントページの続き (72)発明者 日下 輝雄 東京都港区芝五丁目7番1号 日本電気株 式会社内 ─────────────────────────────────────────────────── --Continued front page (72) Inventor Teruo Kusaka 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 Bステージ特性を有する導電性樹脂をシ
ート状に形成した導電性粘着シートを低温の固体状態で
選択的に切断して小片を形成する工程と、前記小片が軟
化して粘着性を呈する温度に加熱した回路基板の端子上
に前記小片を接着してバンプを形成する工程と、前記バ
ンプ上に半導体チップの電極パッドを位置合わせして載
置し前記バンプを加熱して硬化させ前記バンプを介して
前記回路基板の端子と前記半導体チップの電極パッドと
を電気的に接続する工程とを含むことを特徴とする半導
体装置の製造方法。
1. A step of selectively cutting a conductive pressure-sensitive adhesive sheet having a conductive resin having B-stage characteristics formed in a sheet shape in a solid state at a low temperature to form a small piece, and the small piece being softened and having an adhesive property. And forming bumps by bonding the small pieces onto the terminals of the circuit board heated to a temperature of, and placing the electrode pads of the semiconductor chip on the bumps by aligning them and heating and curing the bumps. A method of manufacturing a semiconductor device, comprising a step of electrically connecting a terminal of the circuit board and an electrode pad of the semiconductor chip via the bump.
【請求項2】 導電性粘着シートが金属シートの両面に
Bステージ特性を有する導電性樹脂膜を形成した積層構
造からなる請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive adhesive sheet has a laminated structure in which a conductive resin film having B-stage characteristics is formed on both surfaces of a metal sheet.
【請求項3】 金属シートがAu,Cu,Alのいずれ
か1種からなる請求項2記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 2, wherein the metal sheet is made of any one of Au, Cu and Al.
【請求項4】 Bステージ特性を有する導電性樹脂がA
g,Cu,Auあるいは半田からなる金属微粒子又は微
粒状のプラスチック粒の表面に前記金属のいずれかをめ
っきした微粒子の少くとも1種を混入してなる請求項1
又は請求項2記載の半導体装置の製造方法。
4. A conductive resin having B-stage characteristics is A
2. At least one kind of fine particles obtained by plating the surface of metal fine particles or fine plastic particles made of g, Cu, Au or solder with any of the above metals.
A method for manufacturing a semiconductor device according to claim 2.
【請求項5】 導電性粘着シートを固体状態で打抜き法
あるいはカッティング法により切離して小片を形成する
請求項1又は請求項2記載の半導体装置の製造方法。
5. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive adhesive sheet is cut in a solid state by a punching method or a cutting method to form a small piece.
【請求項6】 金属シートの両面に半田膜又は金属膜を
形成した積層金属シートを選択的に切断して小片を形成
する工程と、前記小片を回路基板の端子上に載置してリ
フローしバンプを形成する工程と、前記バンプ上に半導
体チップの電極パッドを位置合わせして載置し前記バン
プを加熱リフローして接合し前記バンプを介して前記回
路基板の端子と前記半導体チップの電極パッドとを電気
的に接続する工程とを含むことを特徴とする半導体装置
の製造方法。
6. A step of selectively cutting a laminated metal sheet having a solder film or a metal film formed on both sides of a metal sheet to form a small piece, and placing the small piece on a terminal of a circuit board for reflow. A step of forming a bump, and an electrode pad of a semiconductor chip is aligned and placed on the bump, the bump is heated and reflowed to be joined, and the terminal of the circuit board and the electrode pad of the semiconductor chip are connected via the bump. And a step of electrically connecting to each other.
【請求項7】 金属シートがAu,Cu,Al,Niの
いずれか1種からなる請求項6記載の半導体装置の製造
方法。
7. The method of manufacturing a semiconductor device according to claim 6, wherein the metal sheet is made of any one of Au, Cu, Al and Ni.
【請求項8】 半田膜又は金属膜がPb−Sn合金,A
u−Sn合金,Ag−Sn合金,Au,Al,Inのい
ずれか1種からなる請求項6記載の半導体装置の製造方
法。
8. The solder film or the metal film is a Pb-Sn alloy, A
7. The method of manufacturing a semiconductor device according to claim 6, comprising any one of u-Sn alloy, Ag-Sn alloy, Au, Al and In.
【請求項9】 積層金属シートを打抜き法あるいはカッ
ティング法で切離して小片を形成する請求項6記載の半
導体装置の製造方法。
9. The method of manufacturing a semiconductor device according to claim 6, wherein the laminated metal sheet is separated by a punching method or a cutting method to form a small piece.
JP6170617A 1994-07-22 1994-07-22 Method for manufacturing semiconductor device Expired - Fee Related JP2540787B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6170617A JP2540787B2 (en) 1994-07-22 1994-07-22 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6170617A JP2540787B2 (en) 1994-07-22 1994-07-22 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0837206A true JPH0837206A (en) 1996-02-06
JP2540787B2 JP2540787B2 (en) 1996-10-09

Family

ID=15908195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6170617A Expired - Fee Related JP2540787B2 (en) 1994-07-22 1994-07-22 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2540787B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909180B2 (en) 2000-05-12 2005-06-21 Matsushita Electric Industrial Co., Ltd. Semiconductor device, mounting circuit board, method of producing the same, and method of producing mounting structure using the same
US7608860B2 (en) 2001-07-23 2009-10-27 Cree, Inc. Light emitting devices suitable for flip-chip bonding
EP2731126A1 (en) * 2012-11-09 2014-05-14 Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO Method for bonding bare chip dies
JP2019156648A (en) * 2018-03-07 2019-09-19 日本特殊陶業株式会社 Method of producing ceramic member comprising electroconductive part, and ceramic member

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909180B2 (en) 2000-05-12 2005-06-21 Matsushita Electric Industrial Co., Ltd. Semiconductor device, mounting circuit board, method of producing the same, and method of producing mounting structure using the same
US7608860B2 (en) 2001-07-23 2009-10-27 Cree, Inc. Light emitting devices suitable for flip-chip bonding
EP2731126A1 (en) * 2012-11-09 2014-05-14 Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO Method for bonding bare chip dies
WO2014073963A1 (en) * 2012-11-09 2014-05-15 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Method for bonding bare chip dies
CN104854686A (en) * 2012-11-09 2015-08-19 荷兰应用自然科学研究组织Tno Method for bonding bare chip dies
US9859247B2 (en) 2012-11-09 2018-01-02 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Method for bonding bare chip dies
CN104854686B (en) * 2012-11-09 2018-11-27 荷兰应用自然科学研究组织Tno Method for engaging bare chip matrix
JP2019156648A (en) * 2018-03-07 2019-09-19 日本特殊陶業株式会社 Method of producing ceramic member comprising electroconductive part, and ceramic member

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