JPH0836406A - Programmable controller - Google Patents

Abstract

PURPOSE:To miniaturize a programmable controller, which consists of a control operation storage part and one or more input/output means, by reducing the number of signal lines between the control operation storage part and input/ output means. CONSTITUTION:A programmable controller PC 10 consists of a control operation storage part 1A, a first input/output means 21 which communicates with the control operation storage part 1A by an address bus AB for parallel transmission of one address, a data bus DB for parallel transmission of data designated by one address, and a control bus CB, and second input/output means 31,... which settles the state communicatable with the control operation storage part 1A by the address transmitted through a serial signal line SL1 and the signal discriminating between input and output and next transmit/receive data by serial signal lines SL1 and SL2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller which is composed of a control operation storage section comprising control operation means and storage means, and one or more input / output means.

[0002]

2. Description of the Related Art A programmable controller PC1 is shown in FIG. 6 as an example of a programmable controller composed of a conventional control arithmetic storage unit and one or more input / output means.
Indicates. Figure 6 (a) shows the programmable controller PC1
In the figure, reference numeral 1 is a control operation storage unit, 21 and 22 are input / output means, which are elements constituting the programmable controller PC1. The control calculation storage unit 1 and the input / output unit 21 are mounted on the board B1 and
22 is mounted on the board B2, and the board B1 and the board B2 may not be divided as one board, or may be connected by a connector to be separated into two parts.

FIG. 6 (b) shows an example of the structure of a programmable controller PC1 constituted by a board B1, a board B2, and a board B3 to be connected to the right of the board B2 in FIG. 6 (a). It is a figure. Board B1, B2, B3
Is a circuit having a structure in which circuit components are mounted on a printed wiring board, and boards B1, B2, B3 are a mother board MB on which wiring is made on the printed wiring board and each board and mother board MB. It is connected with the connector to be connected. In the figure, connectors C1 and C2 for connecting the board B1 and the mother board MB are shown among the connectors. FIG. 6C is another example showing the structure of the programmable controller PC1 in which the boards B1 and B2 are connected by the connector C3 and two boards are stacked.

FIG. 7 (a) is a block diagram showing the inside of the control operation storage unit 1 shown in FIG. 6 (a). In the figure,
Reference numeral 11 is a control calculation means, and 12 is a storage means. The control calculation storage unit 1 is composed of these two parts. Control calculation means 11
A signal representing one address (abbreviated as an address signal in the following description) is controlled from the terminals A0 to AM in parallel through the address bus AB composed of signal lines connected to the respective terminals, and is controlled by the storage means 12. It is output to the outside of the arithmetic storage unit 1. Input / output of data to / from the control operation means 11, the storage means 12, and the outside of the control operation storage portion 1 is designated by one address via a data bus DB composed of signal lines connected to the terminals D0 to DN. The data is processed in parallel as one unit. Terminal CL
0 to CLL are terminals for inputting / outputting control signals such as giving the time of input / output, and are connected to the control bus CL composed of signal lines connected to the respective terminals. The control operation means 11 selects a partner to communicate by transmitting an address signal via the address bus DB, and via the data bus DB under the control of the control signal transmitted / received via the control bus CL. Input and output data.

FIG. 7B is a block diagram showing the inside of the input / output means 21 as an example of the input / output means. In the figure,
Reference numeral 21 is the same as the input / output means 21 of FIG. 6A, and the main part of the input / output means 21 is composed of an input / output circuit 211. In the input / output circuit 211, the addresses represented by the address signals transmitted from the control arithmetic storage unit 1 via the address bus AB are the terminals P00 to P0N.
If the address of port P0 consisting of P01 to P1N, the address of port P1 consisting of terminals P01 to P1N, or the address of port P2 consisting of terminals P20 to P2N is matched, communication with the control calculation memory unit 1 becomes possible and control is performed. When the signal value 0 is input to the terminal WR via the bus CL, the data output from the control operation storage unit 1 via the data bus DB is transferred to the port specified by the address signal from the control operation storage unit 1. Output. Further, when the signal value 0 is input to the terminal RD via the control bus CL in a state where the communication with the control calculation storage unit 1 is enabled by the above-mentioned procedure, the input / output unit 21 causes the control calculation storage unit 1 to operate. 1
The external data input to the port designated by the address signal from is input and the input data is transmitted to the control calculation storage unit 1 via the data bus DB.

[0006]

The programmable controller has been used in a very wide range as a control device mainly for sequence control, and therefore the programmable controller can be miniaturized and installed in a space as small as possible. Is required. However, as described above, in the conventional programmable controller including the control calculation storage unit and the input / output unit, the signal transmission between the control calculation storage unit and the input / output unit is equal to the number of bits representing one address. Address consisting of several signal lines
It is performed via a bus, a data bus composed of a number of signal lines equal to the number of bits forming data specified by one address, and a control bus for transmitting a control signal. The number of signal lines forming the address bus must be increased in accordance with the increase in the number of each input / output unit and the number of signal lines connected from each input / output unit to the outside. As a convenient number to represent the number, 8, 16
It is composed of signal lines such as books. In this way, since the number of signal lines connecting the control calculation storage unit and the input / output means reaches a considerable number, the area occupied by the signal lines on the printed wiring board forming the circuit of the programmable controller is the whole of the printed wiring board. It is not uncommon to reach more than half of the area, and the area occupied by the wiring on the printed wiring board is a major obstacle to downsizing the programmable controller.

In view of the circumstances described above, an object of the present invention is to reduce the number of signal lines, which is an obstacle to miniaturization, and to provide a smaller programmable controller.

[0008]

In order to achieve the above-mentioned object, according to the present invention, a control calculation storage unit comprising a control calculation unit and a storage unit, and one or more first input / output units,
In a programmable controller comprising one or more second input / output means or one or more second control operation storage section and one or more second input / output means, the first input / output means is one time point from the control operation storage section. With the address signal output via the address bus that transmits one address in parallel, and the control signal output via the control bus from the control calculation storage unit, communication becomes possible and between the control calculation storage unit. The second input / output means is a serial signal line consisting of two signal lines from the control calculation storage section, and communicates via a data bus that transmits in parallel the data of the unit designated by the address signal at one time point. It is possible to communicate with the address signal output via the control signal and the code indicating the control, and to input / output data to / from the control calculation storage unit via the serial signal line. That.

Further, the communication between the second input / output means and the control operation storage section is synchronized with the selection signal for selecting the second input / output means from the control operation storage section via the selection signal line in a bit unit. The communication between the second input / output unit and the control calculation storage unit, which is performed by the clock signal output from the control calculation storage unit for moving the data, causes the control calculation storage unit to select the second input / output unit. It is preferable to use a selection signal output via the selection signal line and a clock signal output from the control operation storage unit for moving data in synchronization with each other in bit units.

Furthermore, a serial signal having a higher transmission rate than the transmission rate of the signal between the second input / output means and the control calculation storage section via the high-speed transmission serial signal line communicates with the control calculation storage section. It is preferable to have three input / output means.

[0011]

When the data is output from the control calculation storage unit to the outside via the first input / output unit, the control calculation storage unit selects the first input / output unit as the first input / output unit via the address bus. The address signal is output, the data to be output to the outside is sent to the first input / output means via the data bus, and then the control signal for giving the time of data output is output via the control bus. The first input / output means receives the address signal and can communicate with the control calculation storage unit, and at the time given by the control signal, outputs the data input via the data bus to the outside. . When data is input to the control calculation storage unit via the first input / output unit, the control calculation storage unit can output an address signal and communicate with the first input / output unit in the same manner as when outputting data. State, a control signal is output to input externally input data to the first input / output means, and external data input to the first input / output means is input via the data bus. .

When outputting data from the control calculation storage unit to the outside via the second input / output unit, the control calculation storage unit first connects the second input / output unit to the second input / output unit via the serial signal line. The designated address signal and the code indicating the output of data are output, and then the data is output serially bit by bit. The second input / output means inputs the input address to its own input / output means, and the code means output, so that it continuously inputs data to be transmitted. When the input of this data is completed, the second input / output means outputs the data input to the outside. When external data is input from the control calculation storage unit via the second input / output unit, the control calculation storage unit first transfers the second data to the second input / output unit via the serial signal line.
An address signal designating the input / output means and a code indicating the input of data are output. Since the input address of the second input / output means is for its own input / output means, and the reference sign means input, external data is input, and subsequently input data is passed through the serial signal line. Then, the data is output bit by bit, and this data is input to the control calculation storage unit.

Further, in the programmable controller according to the present invention as set forth in claim 2, when the data is output to the outside from the control operation storage section via the second input / output means, the selection signal line is output from the control operation storage section. A signal for selecting the second input / output unit for output is transmitted via. The second input / output means for output receives this signal and becomes ready for communication with the control calculation storage section. In this state, the control operation storage section transmits the data to be output to the second input / output means for output bit by bit via the serial signal line. Second for output
The input / output unit inputs this data in synchronization with the clock signal transmitted from the control calculation storage unit, and when the input is completed, outputs the input data to the outside. When data is externally input from the control calculation storage unit via the second input / output unit, the control calculation storage unit is the input second input / output unit in the same manner as for the output second input / output unit. Select. The selected second input / output unit for input inputs data from the outside and then synchronizes the data input from the outside with the clock signal transmitted from the control operation storage unit.
A bit is output and this data is input to the control operation storage unit.

Further, in the programmable controller according to the present invention as defined in claim 3, third input / output means is provided, and the third input / output means is for high speed transmission in the same manner as the second input / output means. High-speed data communication with the control calculation storage unit is performed via the serial signal line.

[0015]

【Example】

(Embodiment 1) In the following description of the embodiment, the signal is 0.
Alternatively, a binary signal corresponding to some one of 1 is represented, and a signal having the same code as the terminal code represents a signal input to or output from the terminal having the same code.

FIG. 1A is a block diagram showing the main part of one embodiment of the programmable controller according to the present invention. In the figure, a PC 10 is a programmable controller, a board B1A on which a control operation storage unit 1A and an input / output unit 21 (hereinafter referred to as a second input / output unit 21) as a second input / output unit are mounted, A board B2A equipped with an input / output unit 31 (hereinafter referred to as a second input / output unit 31) as a second input / output unit, and an input / output unit 32 (also referred to as a second input / output unit) in the following description. The second input / output means 32) is mounted on the board B3A, and the boards B1A, B2A, and B3A are connected by a serial signal line composed of signal lines SL1 and SL2 connected by connectors. Address bus AB is connected to terminals A0-AM of control operation memory 1A, and terminals D0-DN of control operation memory 1A
Is connected to the data bus DB, and the control calculation storage unit 1A is connected to the terminals C0 to CL of the control bus CL.
The functions of these buses are the same as those of the same reference numerals shown in FIG. FIG. 1B shows a block diagram of the control calculation storage unit 1A. In the figure, 1A is a control calculation storage unit, which is composed of a control calculation storage unit 1 and a serial input / output circuit 13, and the control calculation storage 1 is the same as the control calculation storage unit 1 shown in FIG. . The serial input / output circuit 13 is connected to the control arithmetic storage unit 1 via the address bus AB, the data bus DB, and the control bus CL. Control calculation storage unit 1A
When the data is to be serially output from the control arithmetic storage unit 1A, the control arithmetic storage unit 1A serially inputs the address specifying the serial input / output circuit 13 via the address bus AB and the data to be output via the data bus DB. It outputs to the output circuit 13 and then transmits a control signal via the control bus CL, which gives a point in time for the serial input / output circuit 13 to store the data on the data bus DB. The serial input / output circuit 13 receives the address signal and receives the control calculation storage unit 1.
When the control signal is input, the data output from the control calculation storage unit is stored in the register RTM of the serial input / output circuit 13. The serial input / output circuit 13 is a register
Registered on condition that data is stored in RTM
The contents of RTM are sent to the terminal SND connected to the serial signal line SL1 bit by bit at a predetermined cycle. Data input from the outside to the control calculation storage unit 1A is performed as described below.
First, a signal value 0 (referred to as a start bit in the following description) indicating that the transmission of a signal is notified is input to the serial signal line SL2 from the outside. Series I / O circuit 13 starts
When a bit is input, the data following the start bit is sequentially input bit by bit and stored in the register RCV. When the data input is completed, the data is input to the control operation memory 1A via the control bus CL. Output a signal that represents. The control operation storage unit 1 establishes a state in which communication with the serial input / output circuit 13 is possible in the same manner as when data is output when this signal is input, and the contents of the register RCV are transferred to the data bus. Input via DB.

FIG. 1C shows a block diagram of the second input / output means 31. The second input / output unit 32 also has the same configuration as that shown in this drawing regarding the data communication with the control calculation storage unit 1A. The second input / output means is always in a state of waiting for the input of the start bit indicating the transmission start from the serial signal line SL1 except at the time of outputting the data to the outside. Second when the start bit is input
The input / output unit 31 stores in the register RTS the data input bit by bit at a predetermined cycle subsequent to the start bit, and the data stored in the register RTS includes a code indicating transmission, and the second input / output unit 31 When the data including the address of the port P0 whose output terminals are 31 terminals P00 to P0N is included,
The data that is sent next is received, stored in the register RTS, and when the storage of the data following the address is completed,
Outputs the contents of RTS in parallel to port P0 in bit units corresponding to pins P00–P0N. Data entered after the start bit contains a code indicating reception, and terminals P10 to
When the address of the port P1 that uses P1N as the input signal terminal is included, the serial input / output circuit 31 inputs the data input to the port P1 to the register RRS and serially inputs the contents of the input register RRS bit by bit. It is transmitted to the control calculation storage unit 1A via the signal line SL2.

FIG. 2 shows the serial input / output circuit shown in FIG. 1 (b).
The circuit diagram of the output circuit part of 13 is shown. In the figure, 13B is a parallel-input serial-output shift register, 13A is a register control circuit of the shift register 13B, and terminal SPC
The signal input to is 1 and the control calculation storage unit 1A (see FIG.
The data input via the data bus DB from (see (a)) is input to the shift register 13B in parallel. 13C decodes the address signal input from the control arithmetic storage unit 1A via the address bus AB, and if the address represented by the address signal is the address specifying the serial input / output circuit 13, the output terminal
Set the Y0 signal to 1. 13D is a control circuit, and the signal input from the terminal Y0 of the decoding circuit 13C is 1
When the signal WR input from the control operation memory unit 1A via the signal line WR in the control bus CB becomes 0, the signal to the terminal SPC of the register control circuit 13A is set to 1 and the signal WR becomes 0.
When it changes from 1 to 1, the signal at the terminal CO is set to 1. 13F is a clock circuit, and when the signal from the terminal CO of the control circuit 13D becomes 1, the clock signal CLK input from the control arithmetic storage unit 1A via the signal line CLK in the control bus CB is separated. It is a clock circuit that circulates and outputs a pulse of a predetermined cycle. From the control calculation storage unit 1A to the serial input / output circuit 13
The output of the data via is performed as follows. First, the control arithmetic storage unit 1A outputs an address signal designating the serial input / output circuit 13 to the address bus AB. This address signal is input to the decoding circuit 13C of the serial input / output circuit 13 and sets the signal output from the terminal Y0 to the control circuit 13D to 1. Next, the control operation storage unit 1A transmits the data to be transmitted to the serial input / output circuit 13 via the data bus DB, and this data is input to the register control circuit 13A. Further subsequently, the control calculation storage unit 1A sets the signal passing through the signal line WR to 0. Control circuit 13
Since the signal input from the terminal Y0 of the decoding circuit is 1 for D, when the signal WR becomes 0, the terminal S of the register 13A
Set the PC signal to 1. As a result, the data input from the control arithmetic storage unit 1A via the data bus DB is stored in the shift register 13B by the register control circuit 13A. When the signal WR returns from 0 to 1, the control circuit 13D sets the signal of the terminal SPC of the register control circuit to 0 and then sets the signal of the terminal CO to 1. Clock circuit 13F is a terminal of control circuit 13D
When the signal from CO becomes 1, a pulse with a predetermined cycle is output. When a pulse from the clock circuit is input to the terminal CK, the shift register 13B synchronizes with the pulse and outputs the data stored in the shift register 13B bit by bit.
Send to the terminal connected to SL1. When the clock circuit 13F finishes sending the number of pulses equal to the number of bits of the data stored in the shift register 13B, it outputs to the terminal CI of the control circuit 13D.
The signal output to is set to 1 and the pulse transmission is stopped. When the signal value 1 is input to the terminal CI, the control circuit 13D sets the signal RDY to be transmitted via one of the signal lines RDY in the control bus connected to the control calculation storage unit 1A to 1 and sets the control calculation storage unit. Notify 1A that data transmission is complete.
The input circuit from the signal line SL2 of the serial input / output circuit 13 is also made by the same method as that of the output circuit described above, and thus detailed description thereof will be omitted. Further, the configuration of the input / output circuit connected to the serial signal line for the input / output means 31C, 32C is also made by the same method as that of the input / output circuit 13 described above, and thus detailed description thereof will be omitted.

With the configuration of the programmable controller PC10 described above, the programmable controller PC10
The communication between the control calculation storage unit 1A and each input / output unit is performed as follows. That is, the communication between the control operation means 1A and the first input / output means is carried out by parallel signals in address units passing through the address bus AB, the data bus DB and the control bus CB, and the control operation means 1A and the second input / output means. Communication with the output means is performed by a serial signal line composed of two signal lines SL1 and SL2. (Embodiment 2) FIG. 3 shows another embodiment of the present invention. In the figure, a PC 11 is a programmable controller, a board B1B on which a control operation storage unit 1B and a second input / output unit 21 (not shown) are mounted, and an input / output unit 31 as a second input / output unit.
B In the following description, a board B2B mounting a second input / output means 31B) and an input / output means 32B as a second input / output means (hereinafter referred to as a second input / output means 32B)
It consists of a board B3B and a. The control calculation storage unit 1B is the same as the control calculation storage unit 1A shown in FIG. 1 except that the control calculation storage unit 1B has signals output via the terminals SEL0, SEL1, and CK. Terminal
The signals output from SEL0 and the terminal SEL1 are signals generated by decoding the address signal inside the control operation storage unit 1B, and are signals for selecting one of the second input / output units.
In this embodiment, since there are two terminals that output this selection signal, it is possible to distinguish and select up to four second input / output means. The terminal CK is a terminal for outputting a pulse signal CK for operating the internal circuits such as the second input / output means 31B and 32B in synchronization with the internal circuit of the control arithmetic storage unit 1B.

Second input / output means shown in FIG. 3 in FIG. 4 (a)
The block diagram of 31B is shown. The second input / output unit 31B includes a serial input / parallel output shift register 32A, a three-state buffer 32B, and a control circuit 32C, and a control calculation storage unit.
It is a circuit that outputs input data from 1B (see FIG. 2) to the outside. Data output is performed as described below. The control calculation storage unit 1B receives the selection signal SE from the terminals SEL0 and SEL1.
L0 and SEL1 are output, clock signal CK is output, and 1-bit signal line SL is synchronized with clock signal CK.
Output to the second input / output unit 31B via 1. Selection signal
SEL1 and SEL2 are input to the control circuit 32C of the second input / output means 31B, and this signal represents the address designating the second input / output means 31B. Therefore, the control circuit 32C outputs to the terminal OE of the three-state buffer 32B. The signal is set to 0, and the clock signal CK transmitted from the control calculation storage unit 1B is set to the shift register 32A.
Output to. When the clock signal CK is input to the terminal CK, the shift register 32A synchronizes with this signal
While shifting the data in 32A right by 1 bit,
Input the data transmitted from terminal DIN via signal line SL1 bit by bit. When the control circuit 32C completes the input of one data consisting of the number of bits determined by the number of pulses of the clock signal CK, it stops transmitting the pulse to the shift register 32B and sets the signal of the terminal OE of the three-state buffer 32B to 1. . Three-state buffer 32B has pin OE
While the signal input to is in the high impedance state and does not output data to the outside, when the signal input to the terminal OE becomes 1, the data output in parallel from the shift register 32A is output to the outside. Output to.

Second input / output means shown in FIG. 3 in FIG. 4 (b)
The block diagram of 32B is shown. The second input / output means 32B is a parallel input / serial output shift register 32L and a data latch 32M.
And a control circuit 32N, which outputs data received from the outside to the control calculation storage unit 1B (see FIG. 3). Data entry is performed as described below. The control calculation storage unit 1B selects signals SEL0 and SEL from terminals SEL0 and SEL1.
Outputs 1. The selection signals SEL1 and SEL2 are the second input / output means 32.
The signal is input to the control circuit 32N of B, and this signal represents the address designating the second input / output means 32B.
Outputs the signal value 1 to the terminal EN of the data latch 32M. When the signal value input to the terminal EN becomes 1, the data latch 32M inputs and stores the signals PI0 to PIN input in parallel from the outside. The control circuit 32N is followed by the control calculation storage unit.
The pulse signal CK output from 1B is the pin of the shift register 32L.
Output to CK. The shift register 32L outputs the contents of the shift register 32L to the pin when the pulse signal CK is input to the pin CK.
Shift left one bit to DOUT. As a result, the contents of the shift register 32L are transmitted to the control calculation storage section 1B via the serial signal line SL2. Data transmission is completed when the selection signal is input to the signal lines SEL0 and SEL1 and the subsequent pulse signal CK
Is determined by the control circuit 32N according to the number of (Embodiment 3) FIG. 5 shows an embodiment of the invention described in claim 3. In the figure, a PC 12 is a programmable controller, and a board 1C equipped with a control operation storage unit 1C and a second
Board B2C mounting the input / output means 31 as the input / output means (hereinafter referred to as the second input / output means 31) and the input / output means 32C as the third input / output means. Board B3C on which the output means 32C) is mounted.

The control arithmetic storage unit 1C communicates with the second input / output means 31 by a serial signal line consisting of a signal line SL1 connected to the terminal SND and a signal line SL2 connected to the terminal RCV, and the third input / output unit Signal line SLH1 that connects communication with means 32C to terminal SNDH
And a serial signal line for high-speed transmission consisting of a signal line SLH2 connected to the terminal RCVH. Control calculation storage unit 1C and second input / output means
The communication with 31 is performed at the same transmission speed by the same method as the communication between the control calculation storage unit 1A and the second input / output means 31 shown in FIG. The circuit connected to the high-speed transmission signal lines SLH1 and SLH2 synchronizes the operation of the elements constituting the circuit for handling high-speed digital signals, as compared with the circuit connected to the signal lines SL1 and SL2. The frequency of the clock signal has been increased so that the distinction between noise and signal is not lost, and the control operation storage unit 1C and the third input / output unit are provided.
The method of communication with 32C is the same as the method of communication between the control calculation storage unit 1C and the second input / output means 31, but communication is performed at a high speed.

[0023]

As described above, according to the present invention, there is provided a control calculation storage section comprising a control calculation means and a storage means, and a first control calculation storage section.
In the programmable controller comprising one or more of the input / output means and one or more of the second input / output means, or one or more of the control calculation storage section and the second input / output means, the first input / output The means is an address signal output from the control calculation storage unit via an address bus that transmits one address in parallel at one time, and a control signal from the control calculation storage unit.
Communication is made possible by the control signal output via the bus, and the data of the unit specified by the address signal is transmitted in parallel with the control calculation storage section at a time via a data bus. The second input / output unit can communicate with the control calculation storage unit by the address signal output from the control calculation storage unit via the serial signal line including the two signal lines and the code indicating the control. Since the data is input / output via the serial signal line, the input / output unit and the control calculation storage unit are connected when the programmable controller is composed of only the control calculation storage unit and the second input / output unit. Since only two signal lines are required, the space for wiring is greatly saved, and a small programmable controller can be provided. The first input / output unit is arranged near the control calculation storage unit and is used for high-speed data input / output such as image processing, and is connected to the control calculation storage unit only by two serial signal lines. When the 2 input / output means is arranged outside the first input / output means and used for low-speed input / output equipment such as operation switches and electromagnetic contactors, the wiring space is greatly reduced without degrading the function. The advantage is that a small programmable controller is saved.

Further, in the present invention, the communication with the second input / output means is synchronized with the selection signal which selects the second input / output means and which is output from the control operation storage section through the selection signal line in a bit unit. And a clock signal output from a control calculation storage unit for moving data, the input / output means having a simple structure and the signal line for transmitting data is a serial signal line. There is an effect that a small programmable controller composed of only books is provided.

Furthermore, a serial signal having a transmission speed higher than the transmission speed of a signal between the second input / output means and the control arithmetic storage unit via the high-speed transmission serial signal line is used to communicate with the control arithmetic storage unit. If the third input / output means is provided, the third input / output means is used for inputting / outputting data to / from a controlled object that requires high-speed data input / output. By using the second input / output means, there is an effect that a small-sized programmable controller suitable for the controlled object is provided.

[Brief description of drawings]

1A and 1B are diagrams showing an embodiment of a programmable controller according to the present invention, in which FIG. 1A is a block diagram showing a main part of a programmable controller, FIG. 1B is a block diagram of a control operation storage unit, and FIG. Block diagram of serial input / output circuit of control calculation memory

FIG. 2 is a circuit diagram showing details of the serial input / output circuit shown in FIG. 1 (b).

FIG. 3 is a block diagram of an embodiment of a programmable controller according to the present invention as set forth in claim 2;

4 is a block diagram of the input / output unit shown in the block diagram of FIG. 3, (a) is a block diagram of a second input / output unit for output, and (b) is a second input / output unit for input. Block diagram of

FIG. 5 is a block diagram of an embodiment of a programmable controller according to the present invention as set forth in claim 3;

6A and 6B are diagrams showing an example of a programmable controller composed of a conventional control calculation storage unit and input / output means, where FIG. 6A is a block diagram of the programmable controller, and FIG. 6B is shown in FIG. Diagram showing one example of the structure of the programmable controller, (c) is a diagram showing another example of the structure of the programmable controller shown in (a)

7A and 7B are diagrams showing constituent elements of the programmable controller shown in FIG. 6, in which FIG. 7A is a block diagram of the control operation storage unit shown in FIG. 6A, and FIG. Block diagram of input / output means shown in a)

[Explanation of symbols]

 1,1A Control memory 21 First I / O means 31,32 Second I / O means 13 Serial I / O circuit B1A, B2A, B3A Board AB Address bus DB Data bus CB Control bus SL1, SL2 Serial signal line

Claims (3)

[Claims] 1. A control calculation storage unit comprising a control calculation unit and a storage unit, one or more first input / output units, and one or more second input / output units, or the control calculation storage unit. A programmable controller comprising one or more second of the second input / output means, wherein the first input / output means is provided from the control operation storage section via an address bus for transmitting one address in parallel at one time point. It becomes possible to communicate by the output address signal and the control signal output from the control calculation storage unit via the control bus, and the unit data designated by the address signal is exchanged with the control calculation storage unit. The second input / output means communicates via a data bus transmitted in parallel at one time point, and the second input / output means outputs an address signal output from the control operation storage section via a serial signal line composed of two signal lines. A programmable controller, which can communicate with a control signal and a code indicating control, and which inputs and outputs data to and from the control calculation storage unit via the serial signal line. 2. The programmable controller according to claim 1, wherein the communication with the second input / output means selects the second input / output means, and is selected from the control operation storage section via a selection signal line. And a clock signal output from the control operation storage unit for moving data in synchronization with each other in bit units. 3. The programmable controller according to claim 1, wherein the programmable controller is connected via a serial signal line for high speed transmission.
A programmable controller, comprising: a third input / output unit for communicating with the control calculation storage unit by a serial signal having a transmission speed higher than that of a signal between the input / output unit and the control calculation storage unit.