JPH0836033A - Test pattern generating unit - Google Patents

Abstract

PURPOSE:To judge good and no-good of the block light function of a MUT at a high speed and at a low cost by switching a multiplexer to an expected value synthesizing unit so as to lead the area, in which block light of MUT (memory to be tested) has been carried out, and performing the logical comparison with the normal MUT lead data. CONSTITUTION:A data register 41 for taking the data signal from a data generating unit into an expected value synthesizing unit, and an address selector 44 for taking the specified bit out of the address are provided. A master data register file 42 for taking the data from the data generating unit into the specified area on the basis of the light signal from the control signal generating unit, and a light data register file 43 are provided. Output of these registers and files are synthesized to the expected value EDn by a data format 60, and this expected value EDn is output from the multiplexer 50 to a logical comparing unit. This expected value is compared with the normal MUT lead data so as to judge whether or not a block light function is good. All of these structural parts can be available at a low cost, and they can be operated at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator for testing a semiconductor memory, and more particularly to a test pattern generator for testing a semiconductor memory having a block write function.

[0002]

2. Description of the Related Art FIG. 8 shows an example of the configuration of a conventional semiconductor test apparatus for testing the quality of a device under test. FIG. 8 shows an example in which the device under test is a memory, and an address signal is supplied from the address generator 12 to the memory under test 2.
A data signal is supplied from the data generator 13, and a clock control signal for specifying writing, reading, etc. is supplied from the clock control signal generator 14. After these signals are supplied to the memory under test 2 to complete writing, the read data is supplied to the logical comparator 3 at the time of reading, and at the same time, the expected value data is supplied from the pattern generator 1 to the logical comparator 3. To be done. Each of the above-mentioned generation units is controlled by the sequence control unit 11. Then, the pattern generating section is configured by these respective generating sections and the control section.
An expected value generator 4 including a buffer memory for generating expected value data may be added as needed.

In recent years, the types of memories under test (hereinafter referred to as MUTs) have diversified, and there are memories having a block write function, for example, and it has become necessary to test these high-speed and complicated operations. The block write function means the following operation function. The block write is a function of simultaneously writing m words of data in the n-bit data register inside the MUT in one write operation (m × n block write), and the number of words written at this time is the lower several bits of the column address. The range is specified by. For example, in the case of the lower 2 bits, it is 4 words. Further, at the time of block write, the data input to the data pin of the MUT is used as word mask data, and the data in the mask register inside the MUT is used as data bit mask data. With each of these mask data, it is possible to individually specify a data bit or word for which data is not rewritten.

FIG. 9 is a conceptual diagram showing a range in which the memory area of the MUT is accessed by one 4 × 4 block write. A plurality of data bits (D0, D1, D2,
C0, C1, C2, C3 designated by decoding the lower 2 bits of the column address corresponding to D3).
The area indicated by is the area accessed by one block write.

FIG. 10 is an operation example showing the relationship of each data with respect to 16 memory cells accessed by a 4 × 4 block write operation. Of the 4 × 4 = 16 cells, the mask data bits are (MD0, MD1, MD2,
MD3). The data bits applied to the MUT data pins are (BD0, BD1, BD2, BD3)
Indicated by. Further, the data register bit used as write data at the time of block write is (RD0,
RD1, RD2, RD3). In FIG. 10, rewriting is prohibited where the mask data is 0. Therefore, the shaded area is prohibited from data rewriting.
That is, no data is updated for this part. When reading the block-written data, the data is read word by word as in the case of reading a normal memory.

In order to test the memory having the block write function as described above, it is necessary to generate the expected value in consideration of the mask data in the word direction and the bit direction, and the operation and combination thereof are complicated. The generation of expected value data for confirming the operation is complicated and difficult.

An MU having such a block write function
As a method of testing T, a method has been conventionally used in which an expected value generator that emulates a block write operation and generates an expected value is configured by a buffer memory. this is,
A buffer memory having a block write function with a memory capacity equivalent to that of the MUT is configured, and when the MUT performs a block write, the same operation is performed on the buffer memory side at the same time, and when the block-written data of the MUT is read, at the same time. The test is performed by reading the buffer memory side and using this as an expected value.

[0008]

In recent years, the operating speed of the MUT has been remarkably increased, and in order to construct a high-speed buffer memory capable of performing an operation equivalent to that of the MUT which performs this high-speed operation, the device becomes large in size and expensive. It is becoming unavoidable. This is because the high-speed general-purpose memory is expensive and the memory capacity is small. Further, in order to use a general-purpose memory slower than the MUT, the interleave method must be used, and this method requires a memory capacity which is several times as large as that of the MUT. As a result, the size and cost of the device are increased.

The object of the invention is to eliminate these drawbacks,
An object of the present invention is to provide a test pattern generator that can perform a block write function test of a MUT that can operate at high speed at high speed at low cost.

[0010]

In the test pattern generator 1 for generating expected value data for performing logical comparison of the device under test 2, the data generator 13 is generated by the first write signal from the control signal generator 15. A data register 41 for taking in the data signal from An address selector 44 for extracting a specific bit from the address generated by the address generator 12 is provided. Then, a mask data register file 42 is provided which takes in the data signal from the data generator 13 to the area designated by the data selection signal output from the address selector 44 by the second write signal from the control signal generator 15. . And
A write data register file 43 is provided that takes in the data signal from the data generator 13 to the area designated by the data selection signal output from the address selector 44 by the third write signal from the control signal generator 15. Then, according to the output signal of the address selector 44, the output signal of the mask data register file 42, and the output signal of the write data register file 43, the output data of the data register 41 or the output of the data generator 13 is output. A data formatter 60 that synthesizes and outputs data is provided. In this way, the test pattern generator is constructed.

Further, in the above test pattern generator, the output signal of the data formatter 60 or the data generator 1 is selected according to the selection signal from the control signal generator 15.
A test pattern generator may be configured by providing a multiplexer 50 that selectively outputs one of the three output signals.

[0012]

According to the present invention, when the block-written area of the MUT is read, the multiplexer 50 is switched to select the expected value from the expected value synthesizer 40 as shown in FIG. Then, the read data output by reading the MUT and the expected value are compared by the logical comparator 3 to determine whether they are good or bad. At this time, before the block write test, the read operation is performed while the data generator 13 again generates the data pattern in which the memory area is initialized. The data pattern generated again here is masked and is used for expected value synthesis as data that has not been updated. That is, the data formatter 60 in the expected value synthesizing unit uses the mask data in the mask data register file 42 and the write data register file 43 to determine the RDn data and the ID.
While switching the n data bit by bit, an expected value that is consistent with the state of the memory cell of the MUT after block write is generated.

[0013]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory test apparatus including a test pattern generator showing an embodiment of the present invention. FIG. 2 is a block diagram of the expected value generator in the test pattern generator. FIG. 3 is a configuration example of the data formatter in the expected value generation unit.

As shown in FIG. 1, the expected value synthesizer 40 generates expected value data corresponding to the block write function as described in detail below. In the multiplexer 50,
According to the control signal from the control signal generator 15, the output of the expected value synthesizer 40 is selected, or the expected value data from the data generator 13 is selected in order to correspond to the conventional function, and the logical comparator 3 is selected. give.

FIG. 2 is a block diagram of the expected value generator. As shown in FIG. 2, the data register 41 functions to take in the data signal from the data generator 13 in response to the write command 1 signal from the control signal generator 15. The output of the data register 41 is the data register bit R in the expected value combination of the block write area shown in FIGS.
It becomes Dn.

The address selector 44 extracts the bit of the column address which becomes indefinite at the time of block write from the MUT address generated by the address generation unit 12. This output becomes the column address signal (CAi). Further, the address selector 44 uses the mask data (MDn)
Or each data selection signal of write data (BDn) to MU
It works to retrieve from the T address.

Next, the mask data register file 42
In response to a write command 2 signal from the control signal generator 15, the data signal from the data generator 13 is taken into the area designated by the data selection signal output from the address selector 44. The output of the mask data register file 42 becomes the mask data bit MDn shown in FIG.

Next, the write data register file 43
In response to the write command 3 signal from the control signal generator 15, the data signal from the data generator 13 is taken into the area designated by the data selection signal output from the address selector 44. The output of the write data register file 43 becomes the data bit BDn applied to the data pin of the MUT at the time of block write shown in FIG.

The data formatter 60 is the MU.
In accordance with the block write operation of T, the input data signal (IDn), the data register bit signal (RDn), the mask data bit signal (MDn), and the data bit signal applied to the data pin of the MUT in the block write cycle of the MUT ( BDn), column address signal (CAi)
The expected value is synthesized with each data of (1) and output as (EDn).

FIG. 3 shows a 4 × 4 data formatter 60.
FIG. 4 shows an example of the configuration of the select logic 70. Further, FIG. 5 shows an example of the configuration of the data multiplexer (80 and 90).

FIG. 6 shows an example of a memory cell in the 4 × 4 block write area. The 4 × 4 = 16 cells shown in FIG. 6 are composed of 16 1-bit multiplexers (811, 812, ... 844) as shown in FIG. 5, and the select input of each multiplexer is shown in FIG. 1 logic gate group
Connected in pairs. Here, ID0-3 indicates an input data signal and RD0-3 indicates a data register signal. The outputs of the 16 multiplexers are 4-to-1 multiplexers (911, 921, ... 941) for each data bit of D0-3.
By connecting the lower 2-bit signal (CA0, CA1) of the column address from the address selector 44 to the 2-bit select input of this multiplexer,
4 × 4 = 16-bit data is the lower 2 of the column address
It is converted into the expected value ED0-3 of 4 bits which is the same as the ordinary memory read data of 4 bits by the bit signal.

The operation procedure is as follows. First, MUT
Prior to the block write function test, the address selector 44 in the expected value generation unit is used to specify the bit of the column address that is undefined at the time of block write, that is, the block configuration, and the data register 41 and the mask data. The address bits for switching the data in the register file 42 are designated. The address bit is specified based on the MUT test specifications, such as what mask data is used for the test for each test area of the memory. For example, if all memory areas are tested with the same test data, the data switching signal is set to zero.

Next, as a block write test of the MUT, data is written in a memory area to be tested for the block write function of the MUT by a normal write operation to initialize the memory cells. At this time, regarding the expected value generator,
No action needs to be taken. Then, when writing the block write data to the MUT internal data register, the same data is also written to the data register 41 of the expected value generating unit.

Next, when the mask data is written in the MUT internal mask register, the same data is written in the mask data register file 42 of the expected value generator. At this time, the address generator generates an address in the test area of the memory that performs block writing with this mask data.

Next, the block write operation of the MUT is performed. At this time, the expected value generating unit fetches the data applied to the data pin of the MUT into the write data register file 43. The fetching of data into the write data register file 43 need not be performed every block write operation of the MUT, but may be performed once in the test area of the memory that performs block write with this data. The MUT side performs the block write operation as many times as necessary.

In this way, the data in the mask register of the MUT and the data in the data register are changed to perform block writing in the entire test area of the MUT. It should be noted that the procedure may be such that data is written to the write data register file 43 or the mask data register file 42 either before or after block writing is performed on all test areas.

When reading the area in which the MUT block write is performed, as shown in FIG.
Is switched so as to select the expected value from the expected value synthesizing unit 40, and the read data output by normally reading the MUT and the expected value are compared by the logical comparator 3 to determine whether they are good or bad.
At this time, before the block write test, the read operation is performed while the data generator 13 again generates the data pattern in which the memory area is initialized. The data pattern generated again here is masked and is used for expected value synthesis as data that has not been updated. That is, the data formatter 60 in the expected value synthesizing unit switches the RDn data and the IDn data bit by bit according to each mask data of the mask data register file 42 and the write data register file 43, and the state of the memory cell of the MUT after the block write. It is possible to generate expected values that do not conflict with.

As described above, in the expected value pattern according to the present invention, a large number of general-purpose memories are not used as in the conventional case, and the select logic is composed of one AND gate as shown in FIG. Therefore, it can be operated at high speed and can be realized at low cost. Further, as shown in FIG. 5, the data multiplexer is composed of a 2-input or 4-input selector, which enables high-speed operation and can be realized at low cost. As described above, the data formatter 60 is fast and inexpensive, and the other register (4
1, 42, 43), selector 44, multiplexer 50
Can be realized at high speed and at low cost.

[0030]

Since the present invention is configured as described above, it has the following effects. A test pattern generator capable of performing a block write function test at high speed could be provided at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory test apparatus including a test pattern generator according to an embodiment of the present invention.

FIG. 2 is a block diagram of an expected value generator according to the present invention.

FIG. 3 shows a configuration example of a 4 × 4 data formatter 60.

FIG. 4 shows a configuration example of a select logic 70.

FIG. 5 shows a configuration example of a data multiplexer (80 and 90).

FIG. 6 shows an example of a memory cell in a 4 × 4 block write area.

FIG. 7 shows an expected value of a block write area.

FIG. 8 shows a configuration example of a conventional semiconductor test apparatus for testing the quality of a device under test.

FIG. 9 is a conceptual diagram showing a range in which the memory area of the MUT is accessed by one 4 × 4 block write.

FIG. 10 is an operation example showing a relationship of each data with respect to 16 memory cells accessed by a 4 × 4 block write operation.

[Explanation of symbols]

 1 pattern generator 2 memory under test 3 logical comparator 4 expected value generator 11 sequence controller 12 address generator 13 data generator 14 clock control signal generator 15 control signal generator 40 expected value synthesizer 41 data register 42 mask Data register file 43 Write data register file 44 Address selector 50 Multiplexer 60 Data formatter 70 Select logic 80, 90 Data multiplexer

Claims (2)

[Claims] 1. A test pattern generator (1) for generating expected value data for logically comparing a device under test (2) with a first write signal from a control signal generator (15),
A data register (41) for taking in a data signal from the data generator (13) is provided, an address selector (44) for taking out a specific bit from an address generated by the address generator (12) is provided, and a control signal generator (15) ) From the second write signal,
A mask data register file (42) is provided for capturing the data signal from the data generator (13) into the area specified by the data selection signal output from the address selector (44), and the mask signal register file (42) is provided. By the third write signal of
A write data register file (43) is provided to capture the data signal from the data generator (13) into the area specified by the data selection signal output from the address selector (44), and the output of the address selector (44) Depending on the signal, the output signal of the mask data register file (42), and the output signal of the write data register file (43), the output data of the data register (41) or the output of the data generator (13). A test pattern generator characterized in that a data formatter (60) for synthesizing and outputting data is provided. 2. The test pattern generator according to claim 1, wherein the output signal of the data formatter (60) or the output signal of the data generation unit (13) is selected according to a selection signal from the control signal generation unit (15). A test pattern generator characterized in that a multiplexer (50) for selectively outputting is provided.