JPH08340326A - Fifo register and data repeater - Google Patents

Abstract

PURPOSE: To provide a FIFO register realizing a short processing time from an input till an output with a simple configuration and to obtain the data repeater with high response performance regardless of a simple configuration. CONSTITUTION: A read pointer representing a register number storing head data is generated by an up-down counter UDCNT to a shift register SFTBUF receiving sequentially serially received data synchronously with a clock signal corresponding to the data and a multiplexer MPX is controlled by using the read pointer to extract data from a bit of a corresponding register. The FIFO register as above is used and data to be sent again are generated by correcting a frequency deviation or a timing difference produced in a data transmission line between communication systems. The updown counter UDCNT is cleared initially to zero and counts up by detecting a data write signal and counts down by detecting a data read signal to shift the read pointer, then the multiplexer MPX extracts directly the data from the register in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO register and a data repeater, and is used, for example, for correcting timing distortion due to frequency deviation or the like generated in a transmission line having a relatively long length in a serial data communication system. The present invention relates to a technology effectively used for a data repeater.

[0002]

2. Description of the Related Art A FIFO register is F irst I n F
irst O initially captured data based on the operation principle of ut is the first data buffer for outputting. The FIFO register can be used for timing adjustment of the serial signal to be transmitted. The timing adjustment can remove or correct an undesired timing difference or distortion in the serial signal transmitted through the signal transmission path. Therefore, the FIFO register can also be used as a repeater of a data transfer path in a communication system. There is a synchronous fall-through method as a FIFO register method that can be used for timing adjustment. In this system, data input to a shift register which is a FIFO register is sequentially shifted to the final stage with a clock faster than the data, and the data is output in the order of arrival.
The data shift timing is performed by the control circuit corresponding to each register, and the data shift is performed after confirming that the register in the subsequent stage is empty.

[0003]

In the synchronous fall-through type FIFO register in the above-mentioned prior art, input data can be output only at the final stage of the shift register. Therefore, the data shift time from the first stage to the final stage of the shift register is required in addition to the time required to correct the timing distortion, and the data output delay time required from the input to the output of the FIFO register is correspondingly required. There is. Further, in order to reduce the delay time, a high-speed operating frequency is required, so that its control becomes troublesome and the usability is poor.

It is an object of the present invention to provide a FIFO register which has a simple structure and which realizes shortening from input to output. Another object of the present invention is to provide a data repeater having a simple structure and high responsiveness.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a read pointer consisting of an up / down counter is provided for a shift register that sequentially takes in serially input data in synchronization with a corresponding clock signal, and the multiplexer is controlled using the read pointer. Get the data from the bit of the corresponding register. By using such a FIFO register, the frequency deviation and the timing difference occurring in the data transmission path between the communication systems are corrected to form data to be retransmitted.

[0006]

According to the above-mentioned means, the up / down counter is cleared to 0 in the initial state, and the read pointer is moved by counting up by detecting the write of data and counting down by detecting the read. Corresponding data can be retrieved directly in a short time.

[0007]

1 is a block diagram showing an embodiment of a FIFO register according to the present invention. Although not particularly limited, each circuit block shown in the same figure, together with other circuit blocks in the semiconductor integrated circuit in which it is mounted, is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Is formed.

The FIFO register shown in the figure receives asynchronous input data RDATA, write clock WRCLK, data valid signal DTENB, read clock signal RDCLK, and system clock SCLK generated from a circuit (not shown), and forms output data TDATA. To do. Input data RDATA above
Is input data as a serial signal from which timing adjustment or timing distortion should be removed. The write clock WRCLK is a clock signal generated in synchronization with each bit cell of the input data RDATA during the valid period of the input data RDATA. The data valid signal DTENB is a signal synchronized with the input data RDATA, and is a signal indicating whether or not the input data RDATA is valid.

The read clock signal RDCLK is a clock signal for controlling the output of the output data TDATA.
The system clock signal SCLK is a signal for internally synchronizing the input data RDATA, the write clock WRCLK, and the data valid signal DTENB that are supplied asynchronously, and relatively accurately controls each bit cell of the input data RDATA. It has a sufficiently short clock period for the data transfer rate of the input data RDATA so that it can be internally synchronized. The system clock signal SCLK has, for example, a frequency which is about 6 times as high as the data transfer rate of the input data RDATA or a cycle of 1/6.

The synchronizing section SYNC synchronizes the write clock WRCLK, the input data RDATA, the data valid signal DTENB, and the read clock RDCLK with the system clock SCLK as described above. That is, the synchronization unit SYNC
Is the synchronized input data corresponding to the above input data RDATA
SDATA, a synchronized write clock SWRCLK corresponding to the write clock WRCLK, a synchronized data valid signal SDTENB corresponding to the data valid signal DTENB, and a synchronized read clock SRDCLK corresponding to the read clock RDCLK are formed.

Write detection unit WEDG, read detection unit RE
It can be considered that the DG, the up / down counter control unit CNTRL, and the up / down counter UDCNT collectively constitute a read point signal generation unit.

The write detection unit WEDG detects the synchronized write clock SWRCLK to write data to the shift register SFTBUF by inputting data.
That is, the control for detecting the light and outputting the write signal UP is performed. In this case, writing of data to the shift register SFTBUF, in other words, the shift register SFTB
The UF shift operation is performed based on the synchronized write clock SWRCLK. In response to this, the write signal UP is formed based on the synchronized write clock SWRCLK.

The read detection unit REDG forms a read signal DOWN according to the synchronized read clock SRDCLK if the enable is instructed by the read enable signal RDENB output from the read enable control unit RDCNTRL to be described later. If the read enable signal RDENB has been instructed to disable the read detection unit REDG, the read detection unit REDG is disabled accordingly and the read signal DOWN is not output.

Up-down counter control unit CNTRL
Is for performing enable control of the up / down counter UDCNT, and is a synchronization data valid signal SDTEN.
B, Synchronized read clock SRDCLK, System clock SCL
Output of K and up / down counter UDCNT RDPTR
In response, the up / down counter enable signal CNTENB to be supplied to the up / down counter UDCNT is formed. The up / down counter control unit CNTRL receives the synchronization data valid signal SDTENB as an enable signal, and substantially forms the up / down counter enable signal CNTENB corresponding to the signal SDTENB. However, when the count value of the up / down counter UDCNT is 0 and the synchronization read signal SRDCLK is supplied thereto, the up / down counter enable signal CNTENB is set to the disable level.

The up-down counter UDCNT is cleared to 0 in the initial state, and the up-down counter enable signal CNTENB is enabled to start operating.
When the up / down counter enable signal CNTENB is disabled, the up / down counter UDCNT returns to the initial state. Up-down counter UDC
If the NT is enabled by the signal CNTENB, the NT receives the write signal UP supplied from the write detection unit WEDG as a count-up signal, counts up, and is supplied from the read detection unit REDG. The read signal DOWN is received as a down count signal to perform count down. However, the up-down counter UDCNT holds the count value in the previous state when the write signal UP and the read signal DOWN are simultaneously supplied.

The count value of the up / down counter UDCNT corresponds to the read pointer signal RDPTR and indicates the register number storing the leading data to be read by the shift register SFTBUF.

Although not particularly limited, the shift register SFTBUF is composed of 7-stage flip-flops 1 to 7. The details are that three stages are used to correct the data delay and the data advance, and one stage is used to read the data. The writing of data to the shift register SFTBUF and the shifting of data are performed by the synchronized reception clock signal SWRCLK.

In the multiplexer MPX, the read value of the data from the shift register SFTBUF is selected by the count value of the up / down counter UDCNT, that is, the read pointer signal RDPTR, and the data is taken out.

Read enable control unit RDCNTRL
Is not particularly limited, the up-down counter UDC
The read enable signal RDENB is set to the enable level so that the data reading becomes valid only when the count value of NT becomes "4". That is, when the input data arrives, first, it is detected that the write signal UP is counted four times, and the data can be read. That is, the serial input data is transferred to the intermediate position of the shift register SFTBUF, and the timing shift corresponding to the shift operation of 3 bits is corrected in each of the positive direction and the negative direction (advance and delay) with reference to the serial input data. You can

The data output control unit DTOUT does not read data until the read enable signal RDENB arrives. When the read enable signal RDENB arrives, the data reading is started, and the data taken out by the multiplexer MPX is synchronized with the synchronized read clock signal SRDCLK and is output serially. As a result, the timing distortion due to the frequency deviation or the like generated in the input data supplied through the transmission line is corrected, and the synchronized read clock signal SR
Data can be retransmitted to the receiving side terminal device in synchronization with DCLK.

FIG. 2 is a timing chart for explaining an example of the operation of the FIFO register according to the present invention. In the figure, the timing of the read operation of the leading data is mainly shown. In the synchronizing unit SYNC, the input data signal RDATA and the write clock signal WR
Synchronize CLK with system clock signal SCLK.
The synchronized write clock SWRCLK signal is used to write the synchronized input data signal SDATA to the shift register SFTBUF in order from the data D1. At this time, although not particularly limited, it takes 0.5 bit time to write to the shift register SFTBUF.

The data written in the shift register SFTBUF is sequentially shifted in the register by the synchronized write clock signal SWRCLK. At this time, the read pointer signal RDPTR is counted up in synchronization with the synchronized write clock signal SWRCLK. First bit is FIFO
After the data is stored in the register, the data is shifted by three stages and then read is started to absorb the data delay time due to the timing distortion of 3 bits. That is, when the read pointer signal RDPTR indicates the fourth-stage register, the read enable signal RDENB is output, and the data read is started by the synchronized read clock signal SRDCLK.

Here, one of the write clock signal WRCLK and the read clock signal RDCLK is one in which SWRCLK is input in synchronization with the input data RDATA, and the other is RD.
CLK is a clock for timing correction or timing distortion removal, and is asynchronous with each other. Therefore, there is a time difference or a phase difference between the write clock signal SWRCLK and the read clock signal SRDCLK.
In FIG. 2, examples of change timings due to a time difference or a phase difference of the synchronized read clock signal SDRCLK with respect to the synchronized write clock signal SWRCLK obtained via the synchronization unit SYNC are shown as (A) to (D). Write clock signal WRCLK and read clock signal, although not essential
If RDCLK and RDCLK have substantially equal average clock periods, the time difference between these signals will be as much as one bit time as shown.

In the circuit system having the configuration shown in FIG. 1, it takes one bit time for data to pass through or shift through each stage of the shift register SFTBUF. Therefore, the time from the first bit of the received data being shifted into the shift register SFTBUF to being read by the synchronized read clock signal SRDCLK is a maximum of 4.5 bit time.

FIG. 3 is a timing chart for explaining an example of the read start operation of the head data of the FIFO register of the embodiment of FIG. The synchronization input data signal SDATA is shifted in order from the first data D1 of the shift register SFTB according to the synchronization write clock signal SWRCLK.
Captured by UF. That is, the data D1, D2, D3, ... Are transferred from the first stage (FIFO1) to the seventh stage (FI1) of the shift register.
FO7) will be sequentially shifted.

As previously described, the read pointer signal
RDPTR is counted up when the write signal UP is detected and counted down when the read signal DOWN is detected. The read pointer signal RDPTR also increases the write signal UP.
When the read signal and the read signal DOWN are simultaneously detected, the value is maintained as it is. Then, the read pointer signal RDPTR
The data of the register stage indicated by the value (number) of is taken out by the multiplexer MPX. Multiplexer MP
The selection data signal MPXDATA extracted by X is synchronized with the synchronization clock signal SR by the data output unit DTOUT.
Read according to DCLK.

In FIG. 3, data D1 to data D6 shown in bold letters are data read by the synchronized read clock signal SRDCLK. In response, the output data TDATA
Is data synchronized with the synchronized read clock signal SRDCLK. The output data TDATA has the same content as the content of the synchronization input data signal SDATA input to the FIFO register, and its timing is adjusted or corrected to a desired timing. According to the example,
Even if the write timing and the read timing of the data to the FIFO register are different, the read pointer signal RD
The timing can be corrected by moving the pointer, which means PTR, and the data can be read with the minimum delay time.

In this embodiment, after the time required for correcting the timing distortion of the data is secured, the data is output from the register storing the leading data, and compared with the FIFO register of the synchronous fall through system. Data output delay time can be shortened. By enabling the data to be taken out from the middle of the shift register, the data output delay time can be reduced without increasing the operating frequency, in contrast to the synchronous fall-through method in which the data can be taken out only at the final stage of the shift register. It can be shortened.

FIG. 4 is a block diagram showing an embodiment of a data repeater using the FIFO register of the present invention. Although not particularly limited, each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The data repeater according to the present invention is a device for transmitting the received data to the next transmission line in order to extend the transmission line length of the local area network (LAN). In such data relay, it is necessary to correct the timing distortion due to the transmission medium or the like that occurs during communication and retransmit the data. The FIFO register as in the above embodiment is used for such timing correction.

When a carrier sensing multiple access / collision detection (CSMA / CD) type LAN system is constructed using data repeaters, the number of data repeaters connectable between any two terminals on the system. The communication distance that can be extended is limited by the time required for collision detection, that is, the round trip propagation delay time. LAN of CSMA / CD system
Then, the condition of (round-trip propagation delay time) <(minimum frame transmission time) must be satisfied so that collision can be detected reliably. Therefore, in order to extend the communication distance, it is necessary to shorten the data relay delay time of the data relay device as much as possible.

Although not particularly limited, the data repeater of FIG. 4 is configured to receive Manchester-coded reception data RDT and output or transmit timing-adjusted transmission data TDT. The data repeater in the figure is
It has two sets of receiving and transmitting circuits to enable bidirectional data communication. The data repeater has a system clock generation unit CLKGEN common to them, together with the above-mentioned two sets of reception / transmission system circuits.

The system clock generator CLKGEN is
A clock signal of each frequency necessary for each circuit block shown such as a system clock SCLK for performing synchronization and a read clock signal RDCLK serving as a data read clock is formed. The system clock SCLK is set to a high frequency such as 6 times the frequency of the Manchester encoded data.

Manchester-encoded data, as is known, is made to have its level changed in the middle of a bit cell, in other words in the middle of a 1-bit data transmission period, where 0's and 1's of the data are such bits. -Defined by the direction of level change in the center of the cell. That is, the 0 of the data corresponds to the change of the level from the high level to the low level at the center of the bit cell,
On the contrary, data 1 corresponds to a change from low level to high level. This means that Manchester-encoded data substantially has both a data component and a clock signal component in the data itself.

The reception data RDT is not particularly limited,
In the state where data communication is not performed, that is, in the standby state, it is maintained at the low level or the high level,
Alternatively, an idle pulse, that is, a short-time pulse that is generated once for a relatively long time, is made to appear.

In FIG. 4, the reception data RDT obtained by Manchester encoding is input to the decoding unit DECODER via the input buffer INBUF. The decoding technique itself for Manchester encoded data is well known, and the details of the decoding unit DECODER itself are not directly related to the present invention, so a detailed description thereof will be omitted. It is as follows.

That is, the decoding unit DECODER forms the reception data synchronized with the system clock SCLK (hereinafter referred to as synchronized reception data) by taking in the reception data RDT with the system clock SCLK. The decoding unit DECODER extracts a clock component from the synchronized reception data and forms the write clock WRCLK as described in FIG. 1 based on the clock component. The decoding unit DECODER also forms the input data RDATA corresponding to the transmission data component based on the synchronized reception data. The input data RDATA is NRZ coded data, and therefore has a low level corresponding to 0 of the data and a high level corresponding to 1 of the data, like the normal binary data. .

The reception state detection unit STAT receives the reception data RDATA from the input buffer INBUF in the system clock S.
Received in synchronism with CLK, detects whether the communication line is in the receiving state or the standby state based on the received data RDT,
The data valid signal DTENB is formed corresponding to the reception status.
Timing correction unit FIFO using FIFO register
R has basically the same configuration as shown in FIG. 1, and the system clock from the system clock generator CLKGEN is used.
SCLK, read clock signal RDCLK, decoding unit DECOD
Input data RDATA from ER, write clock signal WRCL
K and the data valid signal DT from the reception state detector STAT
In response to ENB, the timing distortion included in the reception data RDT is corrected and the same output data TDATA as the output data in FIG. 1 is generated.

The coding unit CODER outputs the output data of the NRT code corrected by the timing correction unit FIFOR.
Convert TDATA to Manchester coded data. The transmission control unit TCTL forms the transmission data TDT including the Manchester code data from the encoding unit CODER and the idle pulse indicating the standby state according to the reception state detected by the reception state detection unit STAT. The transmission data TDT output from the transmission control unit TCTL is transmitted to the communication line via the output buffer OUTBUF.

In this embodiment, the reception register can be retransmitted with a minimum delay time by using the FIFO register as described above in the data repeater. As described above, the number of data repeaters connectable between any two terminals on the LAN system and the extendable communication distance are limited by the time required for collision detection, that is, the round-trip propagation delay time. By applying the present invention, it is possible to further increase the number of data repeaters connectable between terminals and the extendable communication distance.

The operation and effect obtained from the above embodiment are as follows. That is, (1) For a shift register that sequentially takes in serially input data in synchronization with a corresponding clock signal, generate a read pointer indicating the register number storing the leading data with an up / down counter. By controlling the multiplexer using such a read pointer to extract the data from the bit of the corresponding register, it is possible to retransmit the received data with the minimum delay time.

(2) By configuring a LAN data repeater using the FIFO register as described above, the number of data repeaters connectable between terminals and the extendable communication distance can be further increased. The effect is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, FIG.
In, the number of stages of the shift register SFTBUF can be changed according to the number of bits of timing distortion to be corrected. Also, the number of bits of the multiplexer MPX can be changed according to the number of stages of the shift register SFTBUF. The circuit for forming the read pointer signal RDPTR for controlling the multiplexer MPX can take various embodiments such as the one using the up-down counter as described above and the one using the up-down shift register or the like. . Further, the frequency of the system clock SCLK can be changed according to the width of the timing distortion to be corrected.

The head data read timing described in FIG. 2 is not limited to the fourth stage of the shift register SFTBUF, and can be changed according to the number of bits of timing distortion. Further, the timing of writing the input data to the shift register SFTBUF is not restricted by shifting 0.5 bits with respect to the write clock signal WRCLK, and can be changed as necessary. The block configuration of the data repeater using the present invention is not limited to the form shown in FIG. In addition, received data RDT and transmitted data TDT
Is not limited to Manchester coded data, and the decoding unit D
It is not restricted to have ECODER and coding unit CODER.

[0045]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. For a shift register that sequentially takes in serially input data in synchronization with a corresponding clock signal, an up / down counter generates a read pointer indicating the register number that stores the leading data, and the read pointer is The received data can be retransmitted with a minimum delay time by controlling the multiplexer to extract the data from the bit of the corresponding register.

Using the FIFO register as described above, L
By configuring an AN data repeater, the number of data repeaters connectable between terminals and the extendable communication distance can be further increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a FIFO register according to the present invention.

FIG. 2 is a timing chart for explaining a leading data read start operation of the FIFO register of FIG.

3 is a timing chart for explaining an example of the operation of the FIFO register of FIG.

4 is a block diagram showing an embodiment of a data repeater using the FIFO register of FIG. 1. FIG.

[Explanation of symbols]

SYNC ... Synchronization unit, REDG ... Read clock detection unit, WEDG ... Write clock detection unit, UDCNT ... Up-down counter, CNTRL ... Up-down counter control unit, SFTBUF ... Shift register, MPX ... Multiplexer, DTOUT ... Data output control unit, FIF
OR ... Timing correction unit, TCTL ... Transmission control unit, SF
TBUF ... Shift register, FIFO1 to 7 ... Shift register 1st to 7th stages, RDCNTRL ... Read enable control unit, INBUF ... Input buffer, OUTB
UF ... Output buffer, STAT ... Reception state detection unit, CNTE
NB: Up-down counter enable signal, SCLK
… System clock signal, RDCLK… Read clock signal, WRCLK… Write clock signal, RDATA… Input data, DTENB… Data valid signal, SRDCLK… Synchronized read clock signal, SWRSCLK… Synchronized write clock signal, SD
ATA ... Synchronized input data signal, SDTENB ... Synchronized data valid signal, DOWN ... Read signal, UP ... Write signal, RDPTR ...
Read pointer signal, MPXDATA ... Selection data, RDENB ...
Read enable signal, TDATA ... Output data, D1-7 ...
Data 1 to 7, RDT ... Received data, TDT ... Transmitted data,
CLKGEN ... System clock generator, DECODE
R ... Decoding unit, CORDER ... Encoding unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masago Sato 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Nobuyoshi Furihata 5-chome, Mizumizumoto-cho, Kodaira-shi, Tokyo 22-1 No. 1 in Hitachi Microcomputer System Co., Ltd. (72) Inventor, Koji Suzuki No. 22-1 No. 5-21, Kamimizuhonmachi, Kodaira-shi, Tokyo In Hitachi Microcomputer System Co., Ltd. (72) Isamu Mochizuki, Kodaira-shi, Tokyo 5-22-1, Mizumotocho Hitachi Microcomputer System Co., Ltd. (72) Inventor Takami Shiramizu 3-12 Moriya-cho, Kanagawa-ku, Yokohama, Kanagawa Japan Victor Company of Japan (72) Inventor, Atsushi Sakamoto Yokohama, Kanagawa Victor Company of Japan, Ltd., 3-12 Moriya-cho, Kanagawa-ku, Japan

Claims (3)

[Claims] 1. A shift register for sequentially taking in serially input data in synchronism with a clock signal corresponding thereto, a multiplexer for selectively outputting information of each bit of the shift register, and storing head data. A read pointer indicating a register bit corresponding to an input operation and an output operation, and controlling the multiplexer using the read pointer to select data from the bit of the corresponding register. A FIFO register characterized by the following. 2. The read pointer counts an up-down counter that performs an up-count operation corresponding to the number of data input to the shift register and a down-count operation corresponding to the number of data output from the shift register. The FIFO register according to claim 1, wherein the FIFO register is generated by decoding an output. 3. A shift register for sequentially taking in serially input data in synchronization with a corresponding clock signal, a multiplexer for selectively outputting information of each bit of the shift register, and storing head data. And a select circuit that generates a read pointer indicating a register bit corresponding to an input operation and an output operation and controls the multiplexer using the read pointer to select data from the bit of the corresponding register.
A data repeater comprising an O register and forming data to be retransmitted by correcting frequency deviation and timing difference occurring in a data transmission line between communication systems.