JPH08339392A - Method and device for designing cell layout method and device for designing lsi layout - Google Patents

Abstract

PURPOSE: To provide a method for designing the cell layout and a method for designing an LSI layout by which the arrangement of a substrate contact conducting the auxiliary diffused layer of the characteristic inverse from the diffused layer composing a cell, a power source layer or a ground layer can be automatically set. CONSTITUTION: Based on the design data of an inputted cell and the substrate contact data showing the size of a preliminarily set substrate contact, at least one substrate contact arrangement area where the substrate contact within an auxiliary diffused layer area is possible to be arranged is retrieved, substrate contact arrangement data for arranging the substrate contact within the auxiliary diffused layer area corresponding to the retrieved substrate contact arrangement area is added to design data, and additional design data is outputted (S5). Further, also the auxiliary diffused layer arrangement area for arranging the auxiliary diffused layer is automatically retrieved and the corresponding auxiliary diffused layer arrangement data is added to design data (S1 to S4). The arrangement designs of the substrate contact and the auxiliary diffused layer can be automated and design efficiency is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell layout designing method and apparatus and an LSI (Large Scale Integration).
More specifically, the present invention relates to a designing method and device, in which a hole density and a conduction electron density which are opposite to the relationship between the hole density and the conduction electron density of a diffusion layer which is arranged in a cell which constitutes the LSI and which composes the cell. Auxiliary diffusion layer and power supply layer or GN having a relation
The present invention relates to a cell layout designing method and device for setting a placement position of a substrate contact that conducts with D (Ground; ground layer), and an LSI designing method and device using the same.

Generally, when an integrated LSI or the like is manufactured by using the integrated circuit technology, individual elements such as transistors constituting the LSI or the like are thinned and thinned on a semiconductor wafer such as silicon. It is manufactured by using the technology.

A thinned CMOS FET
(Complementary Metal-Oxide-Semiconductor Field Ef
The above transistors such as fect transistor) are, for example,
In the case of a P-channel type transistor, one transistor has a P-type diffusion layer corresponding to the source terminal, a polysilicon gate corresponding to the gate terminal, and a drain terminal (output terminal) on the N-type well layer. And corresponding aluminum terminals.

[0004]

2. Description of the Related Art In order to stabilize the potential of the P-type diffusion layer, an N-type auxiliary layer insulated from the P-type diffusion layer is formed on the N-type well layer in which the P-type diffusion layer is formed. It is effective to provide a diffusion layer and a substrate contact that connects this to the power supply layer.This substrate contact is placed so that the parasitic thyristor or the parasitic transistor becomes conductive due to an excessive input voltage, etc. This is widely and generally performed to prevent a so-called latch-up phenomenon in which a large current flows and the circuit operation becomes abnormal or the circuit is destroyed.

The substrate contact is used only for stabilizing the potential of the diffusion layer.
Is not directly involved in the operation of. Therefore, when arranging the substrate contact, the area occupied by the substrate contact is arranged as small as possible, and normally, among the respective figures in the cell layout, the figure showing the substrate contact is the smallest.

Next, the arrangement of substrate contacts in the prior art will be described with reference to FIGS. 8 and 9. At the beginning,
The design of the cell layout used for manufacturing the FET will be described with reference to FIG. Here, FIG. 8 shows one cell C.
P-channel FET 10P and N-channel FET 10N
2 shows a case where the two FETs of (1) are configured to be complementary. FIG. 8 shows EWS (Engineering Work Statio).
When designing a cell layout according to n), it is a drawing (EWS display screen) of the design data that shows where each layer (power supply layer, diffusion layer, etc.) should be placed. 2 is not a plan view of the FET device manufactured in FIG.

As shown in FIG. 8, a P-channel FET 10 is provided.
P is a power supply layer V _SS , an N-type well layer (N-type region layer) NW for accommodating the entire P-channel FET 10P, a P-type diffusion layer FLP corresponding to a source terminal, and a P-type diffusion layer FL.
A contact CO serving as a connecting portion for connecting P and the power supply layer V _SS between layers, a polysilicon gate PS corresponding to a gate terminal, an output terminal OUT corresponding to a drain terminal and formed of aluminum, and an output terminal OUT. Contact C as a connecting portion for interlayer connection with the P-type diffusion layer FLP
And O. Here, the hatched portion of the N-type well layer NW is a field region F for separating (isolating) the adjacent FETs.

The N-channel FET 10N includes a ground layer GND, a P-type well layer (P-type region layer) PW for accommodating the entire N-channel FET 10N, an N-type diffusion layer FLN corresponding to a source terminal, and an N-type diffusion layer FLN. Contact CO as a connecting portion for interlayer connection between the type diffusion layer FLN and the ground layer GND
And a polysilicon gate PS corresponding to the gate terminal,
The output terminal OUT, which corresponds to the drain terminal and is formed of aluminum, the output terminal OUT, and the N-type diffusion layer FLN
And a contact CO as a connecting portion for connecting between and. Here, like the P-channel FET 10P, the hatched portion of the P-type well layer PW is the field region F, and the polysilicon gate PS and the output terminal OUT are common to the P-channel FET 10P and the N-channel FET 10N. Has become. Further, an input terminal IN common to the N-channel FET 10N and the P-channel FET 10P is formed on the polysilicon gate PS.

Next, a case where a substrate contact for stabilizing the potential of each diffusion layer is arranged in the cell C shown in FIG. 8 will be described with reference to FIG. First, the case where one substrate contact is arranged for the P-channel FET 10P will be described.

As shown in FIG. 9, a P-channel FET 10 is provided.
One substrate contact CO to P _SWhen placing
First, the P-type diffusion layer FLP on the N-type well layer NW
Power layer V_SSN-type auxiliary diffusion layer to include
FLN_SIs formed. Then, the N-type auxiliary diffusion layer F
LN_SAnd power layer V_SSThe overlapping area is the substrate contact CO _S
And this board contact CO_SN type auxiliary diffusion by
Layer FLN_SAnd power layer V _SSWill be connected between layers.

[0011] Similarly, in the N-channel FET10N, first, in a region other than the N-type diffusion layer FLN on P type well layer PW, P-type auxiliary diffusion layer FLP _S is formed so as to include the ground layer GND . Then, this P-type auxiliary diffusion layer F
Substrate contact CO is the overlapping region of LP _S and ground layer GND.
_S, and the ground layer GND and P-type auxiliary diffusion layer FLP _S is interlayer connection by the substrate contact CO _S.

The P-type diffusion layer FLP and the N-type diffusion layer FL are formed by the substrate contact CO _S formed through the above steps.
Since the potential of N is stabilized and the latch-up phenomenon is prevented, the P-channel FET 10P and the N-channel F are
The ET10N complementarily operates stably.

[0013]

However, when arranging the substrate contact CO _S in the cell, the layout, size, etc. of the substrate contact CO _S are designed in accordance with the layout rule including the cell. In the past, the designer himself had to design the layouts one by one, and also had to check the size etc. based on the design rule.

As a result, a great deal of labor and time are required for the design of the substrate contact that is not directly involved in the operation of the FET, resulting in a problem that the efficiency of cell design is significantly reduced.

Further, since the designer designs the layout, even if the cells have the same function, the layout of the substrate contacts may be different if the designers are different, and as a result, the design of the entire cell is different. There was also a problem that it was inconvenient for production.

Therefore, the present invention has been made in view of the above problems, and an object thereof is a cell layout designing method and apparatus capable of automatically setting the arrangement of substrate contacts, and an LSI layout designing. A method and apparatus are provided.

[0017]

According to a first aspect of the present invention, a hole density opposite to a relationship between a hole density and a conduction electron density of a diffusion layer such as a P-type diffusion layer forming a cell such as an FET is reversed. Cell layout design for arranging a substrate contact for electrically connecting an auxiliary diffusion layer such as an N-type diffusion layer having a relationship of conduction electron density with a power supply layer or a ground layer in an auxiliary diffusion layer region corresponding to the auxiliary diffusion layer. In the method, at least one of the substrate contacts in the auxiliary diffusion layer region can be arranged based on the inputted design data of the cell and substrate contact data indicating a preset size of the substrate contact. A search step of searching a substrate contact placement region, and an arrangement for arranging the substrate contact in the auxiliary diffusion layer corresponding to the searched substrate contact placement region. Add the data in the design data, configured and a data addition step of outputting an additional design data.

According to the second aspect of the present invention, the relationship between the hole density and the conduction electron density is opposite to the relationship between the hole density and the conduction electron density in the diffusion layer such as the P-type diffusion layer that constitutes the cell such as FET. A cell layout designing method for arranging an auxiliary diffusion layer such as an N-type diffusion layer and a substrate contact for electrically connecting the auxiliary diffusion layer and a power supply layer or a ground layer in an auxiliary diffusion region corresponding to the auxiliary diffusion layer. A first search step of searching an auxiliary diffusion layer arrangement area in which the auxiliary diffusion layer can be arranged in the cell based on the input design data of the cell, and the searched auxiliary diffusion layer arrangement area Corresponding to the addition of auxiliary diffusion layer placement data for placing the auxiliary diffusion layer in the cell to the design data,
A first data adding step of outputting first additional design data;
At least one substrate in which the substrate contact can be arranged in the auxiliary diffusion layer arrangement region based on the first additional design data and the substrate contact data indicating a preset size of the substrate contact. A second search step of searching for a contact placement region, and substrate contact placement data for placing the substrate contact in the auxiliary diffusion layer placement region corresponding to the searched substrate contact placement region, the first design data Added to
A second data adding step of outputting second additional design data;
It is configured with.

The invention according to claim 3 is the input FE
An N-type diffusion layer having a relationship between the hole density and the conduction electron density that is opposite to the relationship between the design data of the cell such as T and the hole density and the conduction electron density of the diffusion layer such as the P-type diffusion layer forming the cell. The substrate contact in the auxiliary diffusion layer region corresponding to the auxiliary diffusion layer based on preset substrate contact data indicating the size of the substrate contact for electrically connecting the auxiliary diffusion layer such as the power supply layer or the ground layer. A search step of searching for at least one substrate contact placement region that can be placed, and placement data for placing the substrate contact in the auxiliary diffusion layer region corresponding to the searched substrate contact placement region. A cell layout design step including a data addition step of adding to the design data and outputting the additional design data; the cell design data and the board contour; An input step of inputting Todeta, configured and a display step of displaying a cell layout based on the additional design data.

The invention according to claim 4 is the input FE
Based on the design data of the cell such as T, the relationship between the hole density and the conduction electron density of the auxiliary diffusion layer arranged in the cell, which is the diffusion layer such as the P-type diffusion layer constituting the cell is opposite. A first search step of searching an auxiliary diffusion layer arrangement region in the cell in which an auxiliary diffusion layer such as an N-type diffusion layer having a relationship between the hole density and the conduction electron density can be arranged. A first data adding step of adding auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell corresponding to the auxiliary diffusion layer arrangement area to the cell design data and outputting first additional design data; , The first additional design data and the substrate contact arranged in the auxiliary diffusion layer arrangement region, which indicates the size of the substrate contact for electrically connecting the auxiliary diffusion layer and the power supply layer or the ground layer, and is set in advance. Board contact A second search step of searching for at least one substrate contact placement region in the auxiliary diffusion layer placement region in which the substrate contact can be placed, based on Correspondingly, a second data adding step of adding substrate contact placement data for placing the substrate contact in the auxiliary diffusion layer placement region to the first design data and outputting second additional design data. It comprises a cell layout design process, an input process for inputting the cell design data and the substrate contact data, and a display process for displaying a cell layout based on the second additional design data.

According to a fifth aspect of the present invention, the relationship between the hole density and the conduction electron density is opposite to the relationship between the hole density and the conduction electron density in the diffusion layer such as a P-type diffusion layer that constitutes a cell such as FET. In a cell layout design device for arranging a substrate contact for electrically connecting an auxiliary diffusion layer such as an N-type diffusion layer with a power supply layer or a ground layer in an auxiliary diffusion layer region corresponding to the auxiliary diffusion layer. At least one substrate contact arrangement region in which the substrate contact can be arranged in the auxiliary diffusion layer region is searched based on the cell design data and the substrate contact data indicating a preset size of the substrate contact. And a placement means for placing the substrate contact in the cell corresponding to the retrieved substrate contact placement area. Add the design data, and includes a data adding unit such as a CPU for outputting an additional design data.

According to a sixth aspect of the present invention, the relationship between the hole density and the conduction electron density is opposite to the relationship between the hole density and the conduction electron density in the diffusion layer such as the P-type diffusion layer that constitutes the cell such as FET. A cell layout design device for arranging an auxiliary diffusion layer such as an N-type diffusion layer and a substrate contact for electrically connecting the auxiliary diffusion layer and a power supply layer or a ground layer in the cell, the design of the input cell First search means such as a CPU for searching an auxiliary diffusion layer arrangement area in which the auxiliary diffusion layer can be arranged in the cell based on the data, and the above-mentioned corresponding auxiliary diffusion layer arrangement area A first data adding unit such as a CPU that adds auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell to the design data and outputs first additional design data; and the first additional design data and A CPU for searching at least one substrate contact arrangement region in which the substrate contact can be arranged in the auxiliary diffusion layer arrangement region based on substrate contact data indicating a preset size of the substrate contact. And a second search means for adding the substrate contact placement data for placing the substrate contact in the auxiliary diffusion layer placement region corresponding to the searched substrate contact placement region to the first design data, And a second data adding unit such as a CPU that outputs the second additional design data.

The invention according to claim 7 is the input FE
An N-type diffusion layer having a relationship between the hole density and the conduction electron density that is opposite to the relationship between the design data of the cell such as T and the hole density and the conduction electron density of the diffusion layer such as the P-type diffusion layer forming the cell. The substrate contact in the auxiliary diffusion layer region corresponding to the auxiliary diffusion layer based on preset substrate contact data indicating the size of the substrate contact for electrically connecting the auxiliary diffusion layer such as the power supply layer or the ground layer. Retrieval means such as a CPU for retrieving at least one substrate contact placement region that can be placed, and placement data for placing the substrate contact in the cell corresponding to the retrieved substrate contact placement region. Cell layout design means including a data addition means such as a CPU for adding to the design data and outputting the additional design data; the cell data and the base; Configured to include an input means such as a keyboard for entering the contact data, and a display unit such as a display for displaying the cell layout based on the additional design data.

The invention according to claim 8 is the input FE
Based on the design data of the cell such as T, the relationship between the hole density and the conduction electron density of the auxiliary diffusion layer arranged in the cell, which is the diffusion layer such as the P-type diffusion layer constituting the cell is opposite. A first searching means such as a CPU for searching an auxiliary diffusion layer arrangement region in the cell in which an auxiliary diffusion layer such as an N-type diffusion layer having a relationship between the hole density and the conduction electron density can be arranged. A CPU or the like which adds auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell corresponding to the formed auxiliary diffusion layer arrangement area to the cell design data and outputs the first additional design data. First data adding means, and the first
Preliminary substrate contact data indicating additional design data and substrate contacts arranged in the auxiliary diffusion layer arrangement region, the size of the substrate contact for electrically connecting the auxiliary diffusion layer and the power supply layer or the ground layer. Based on
Corresponding to the searched second substrate contact arrangement region such as a CPU for searching at least one substrate contact arrangement region in which the substrate contact can be arranged within the auxiliary diffusion layer arrangement region. A second data adding means such as a CPU for adding substrate contact arrangement data for arranging the substrate contact in the auxiliary diffusion layer arrangement area to the first design data and outputting second additional design data; A cell layout design means including
An input unit such as a keyboard for inputting the cell design data and the substrate contact data, and a display unit such as a display for displaying a cell layout based on the second additional design data are configured.

[0025]

According to the invention described in claim 1, in the searching step, at least one substrate contact arrangement capable of arranging the substrate contact in the auxiliary diffusion layer region based on the cell design data and the substrate contact data. Search the area.

Then, in the data adding step, layout data for arranging the substrate contact in the auxiliary diffusion layer region corresponding to the searched substrate contact placement region is added to the design data, and the additional design data is output. .

Therefore, the board contact arrangement area is automatically searched, and the arrangement data for arranging the board contact is added to the cell design data based on the area. Therefore, the design data for arranging the board contact can be obtained. Manufacturing can be automated.

According to the second aspect of the present invention, in the first searching step, the auxiliary diffusion layer arrangement region in which the auxiliary diffusion layer can be arranged in the cell is searched based on the cell design data.

Then, in the first data adding step, auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell corresponding to the retrieved auxiliary diffusion layer arrangement area is added to the design data, and the first addition is performed. Output design data.

Next, based on the first additional design data and the substrate contact data indicating the preset size of the substrate contact, the substrate contact is arranged in the auxiliary diffusion layer arrangement region in the second searching step. Search for at least one substrate contact placement area that is possible.

Thereafter, corresponding to the retrieved substrate contact placement region, in the second data addition step, substrate contact placement data for placing a substrate contact in the auxiliary diffusion layer placement region is added to the first design data. Then, the second additional design data is output.

Therefore, the auxiliary diffusion layer arrangement area and the substrate contact arrangement area are automatically searched, and the auxiliary diffusion layer arrangement data and the substrate contact arrangement data are added to the cell design data based on this, so that the auxiliary diffusion layer is obtained. The production of design data for placement of regions and substrate contacts can be automated.

According to the third aspect of the invention, the cell design data and the substrate contact data are input in the input step. As a result, in the search step included in the cell layout design step, at least one substrate contact arrangement area where the substrate contact can be arranged in the auxiliary diffusion layer area is searched based on the cell design data and the substrate contact data.

Then, in the data adding step included in the cell layout designing step, layout data for arranging the substrate contact in the auxiliary diffusion layer region corresponding to the searched substrate contact placement region is added to the design data, Output additional design data.

Then, in the display step, the cell layout based on the additional design data is displayed. Therefore, the board contact placement area is automatically searched, and the placement data for placing the board contact is added to the cell design data based on this, so the production of the design data for placing the board contact is automated. Then, the LSI can be designed.

According to the invention described in claim 4, in the input step, cell design data and substrate contact data are input. As a result, in the first search step included in the cell layout design step, the auxiliary diffusion layer arrangement area in the cell in which the auxiliary diffusion layer can be arranged is searched based on the input cell design data.

Then, in the first data adding step included in the cell layout designing step, the auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell is provided corresponding to the retrieved auxiliary diffusion layer arranging area. Added to the design data,
Output the first additional design data.

Next, based on the first additional design data and the substrate contact data, the substrate contact can be arranged in the auxiliary diffusion layer arrangement region in the second searching step included in the cell layout designing step. At least one substrate contact placement area is searched.

After that, the second substrate included in the cell layout design process corresponding to the retrieved substrate contact arrangement region.
In the data adding step, the substrate contact arrangement data for arranging the substrate contact in the auxiliary diffusion layer arrangement area is added to the first design data, and the second additional design data is output.

Then, in the display step, the cell layout based on the second additional design data is displayed. Therefore, the auxiliary diffusion layer arrangement area and the substrate contact arrangement area are automatically searched, and the auxiliary diffusion layer arrangement data and the substrate contact arrangement data are added to the cell design data based on the search. The LSI can be designed by automating the production of design data for arranging the contacts.

According to the invention described in claim 5, the searching means can arrange at least one substrate contact in the auxiliary diffusion layer region based on the input cell design data and substrate contact data. The substrate contact arrangement area is searched and output to the data adding means.

Then, the data adding means adds layout data for arranging the substrate contact in the auxiliary diffusion layer region to the design data, corresponding to the searched substrate contact placement region.

Therefore, since the board contact arrangement area is automatically searched and the arrangement data for arranging the board contact is added to the cell design data based on the area, the design data for arranging the board contact can be obtained. Manufacturing can be automated.

According to the sixth aspect of the present invention, the first searching means searches the auxiliary diffusion layer arrangement region in which the auxiliary diffusion layer can be arranged in the cell based on the cell design data, 1 Output to the data addition means.

Then, the first data adding means adds the auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell corresponding to the retrieved auxiliary diffusion layer arrangement area to the design data, and the first addition Output design data.

Next, based on the first additional design data and the substrate contact data indicating the preset size of the substrate contact, the second searching means arranges the substrate contact in the auxiliary diffusion layer arrangement region. Search for at least one substrate contact placement area that is possible.

Then, the second data adding means, corresponding to the retrieved substrate contact placement region, adds the substrate contact placement data for placing the substrate contact in the auxiliary diffusion layer placement region to the first design data. Then, the second additional design data is output.

Therefore, the auxiliary diffusion layer arrangement area and the substrate contact arrangement area are automatically searched, and the auxiliary diffusion layer arrangement data and the substrate contact arrangement data are added to the cell design data based on this, so that the auxiliary diffusion layer is formed. The production of design data for placement of regions and substrate contacts can be automated.

According to the invention described in claim 7, the input means inputs the cell data and the substrate contact data. As a result, the search unit included in the cell layout design unit selects at least one substrate contact arrangement region in which the substrate contact in the auxiliary diffusion layer region can be arranged based on the input cell design data and substrate contact data. Search for.

Then, the data adding means included in the cell layout design means adds layout data for arranging the substrate contacts in the auxiliary diffusion layer region to the design data in correspondence with the retrieved substrate contact layout region, Output additional design data.

After that, the display means displays the cell layout based on the additional design data. Therefore, the board contact placement area is automatically searched, and the placement data for placing the board contact is added to the cell design data based on this, so the production of the design data for placing the board contact is automated. Then, the LSI can be designed.

According to the invention of claim 8, the input means inputs the cell design data and the substrate contact data. As a result, in the first search means included in the cell layout design means, the auxiliary diffusion layer arrangement area in the cell in which the auxiliary diffusion layer can be arranged is searched based on the input cell design data, and the cell layout is performed. The data is output to the first data adding unit included in the designing unit.

Then, in the first data adding means included in the cell layout design means, corresponding to the retrieved auxiliary diffusion layer arrangement area, auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell is provided. Added to the design data,
The first additional design data is output to the second searching means included in the cell layout designing means.

Next, based on the first additional design data and the substrate contact data, the second search means included in the cell layout design means can arrange the substrate contact in the auxiliary diffusion layer arrangement region. At least one substrate contact arrangement area is searched and output to the second data adding means included in the cell layout designing means.

After that, the second element included in the cell layout design means is provided corresponding to the retrieved substrate contact placement area.
The data adding means adds the substrate contact arrangement data for arranging the substrate contact in the auxiliary diffusion layer arrangement area to the first design data, and outputs the second additional design data to the display means.

Then, the cell layout based on the second additional design data is displayed on the display means. Therefore, the auxiliary diffusion layer arrangement area and the substrate contact arrangement area are automatically searched, and the auxiliary diffusion layer arrangement data and the substrate contact arrangement data are added to the cell design data based on the search. The LSI can be designed by automating the production of design data for arranging the contacts.

[0057]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to FIGS. In the following embodiments, not only the process for disposing the substrate contact, but also the process for disposing the auxiliary diffusion layer connected to the power supply layer or the ground layer by the substrate contact is automatically performed.

First, the configuration of the LSI design apparatus according to the embodiment will be described with reference to FIG. As shown in Figure 1,
The LSI design apparatus S according to the embodiment inputs the design data of the cell C, which is designed in advance and before the board contacts are arranged, and the board contact data such as the size of the board contact set based on the design rule in advance. A keyboard 1 as an input means for storing the design data of the cell C and the board contact data when the design data and the board contact data of the cell C are designed by another design device. Reading device 2 such as an FD drive as an input means for reading the data from the recording medium according to the instruction of the keyboard 1, a searching means for performing a process for arranging a substrate contact, a data adding means, a first and a second search. Means and a processing device 3 such as a CPU as the first and second data adding means, and a substrate contact in the processing device 3. A ROM (Read Only Memory) 4 for (corresponding to the flowchart shown in FIG. 2 described later) of the program for the end processing such as storing, and output as necessary,
A display 5 as a display unit for displaying a cell layout in which the board contacts are arranged as a result of the board contact arrangement process, and an FD drive, an HD (Hard Disk) drive or the like for storing the result of the board contact arrangement process. The device 6 and the printer 7 for outputting the result of the substrate contact placement processing as data are configured.

Next, focusing on the substrate contact placement processing in the processing apparatus 3, the LSI design apparatus S according to the embodiment.
2 will be described with reference to FIGS. 2 to 7 by taking as an example the case where the substrate contact is arranged for the cell C composed of the CMOS FET described in FIG.

As shown in the flowchart of FIG. 2, in the LSI design apparatus S according to the embodiment, first, a cell C having no substrate contact input from the input means such as the keyboard 1 (see FIG. 8). On the N-type well layer NW (see FIG. 8) in the region where the P-channel FET 10P (see FIG. 8) is formed on the basis of the design data of FIG. An N-type auxiliary diffusion layer FLN _S (see FIG. 8) is arranged in all the regions. Similarly, a vacant region other than the N-type diffusion layer FLN (see FIG. 8) on the P-type well layer PW (see FIG. 8) in the region where the N-channel FET 10N (see FIG. 8) is formed. all to place a P-type auxiliary diffusion layer FLP _S (see FIG. 8) (step S1). The result of executing step S1 is shown in FIG. Note that FIG. 3 shows a case where three cells C (see FIG. 8) are arranged in parallel to form one LSI, and FIG. 3 shows that when designing a cell layout, It is a drawing of the design data of each layer (display screen of EWS), and does not show a plan view of the actually manufactured cell C (similar in FIGS. 4 and 6).

As shown in FIG. 3, the P-channel FET 10
At P, the N-type well layer NW is provided with the N-type auxiliary diffusion layer FLN _{S in} all available regions of the free region other than the P-type diffusion layer FLP. Similarly, N
In channel FET10N, a P-type well layer PW, of free space other than the N-type diffusion layer FLN, P-type auxiliary diffusion layer FLP _S all areas can be arranged is arranged.

In step S1, the P type diffusion layer FLP
Alternatively, if the N-type auxiliary diffusion layer FLN _S or the P-type auxiliary diffusion layer FLP _S is arranged in all the empty areas other than the N-type diffusion layer FLN, then in step S2, the polysilicon gate P
The N-type auxiliary diffusion layer FLN _S or the P-type auxiliary diffusion layer FLP _S on the extension of S in the longitudinal direction is deleted. This is because, if the longitudinal direction of the extension on the polysilicon gate PS is N-type auxiliary diffusion layer FLN _S or P-type auxiliary diffusion layer FLP _S, because there would further transistor is formed.

Next, in step S3, based on the substrate contact data input by the input means, a graphic corresponding to a region smaller than the substrate contact region as the minimum region on the cell C (in the flow chart shown in FIG. 2, Since the substrate contact area is 1.2 μm square, it is determined whether or not there is a smaller figure).
Then, if a graphic smaller than the substrate contact exists (step S3; NO), the graphic is deleted (step S4), and the process returns to the determination of step S3. If there is no figure smaller than the substrate contact (step S3; YES), the N-type auxiliary diffusion layer FLN _{S used} so far is used.
Or an auxiliary diffusion layer arrangement data corresponding to the area for arranging the P-type auxiliary diffusion layer FLP _S, in addition to the design data of the cell C that is input at the beginning, the process proceeds to step S5.

FIG. 4 shows the result of executing the processing of steps S2 to S4. As shown in FIG. 4, in the P-channel FET 10P, the N-type auxiliary diffusion layer FLN _S on the extension of the polysilicon gate PS in the longitudinal direction is removed, and the N of the portion smaller than the size of the substrate contact is removed.
The type auxiliary diffusion layer FLN _S (in FIG. 3, the N type auxiliary diffusion layer FLN _{S at} the boundary portion of each cell C) is deleted. Similarly, in the N-channel FET10N, polysilicon gate P-type auxiliary diffusion layer FLP _S in the longitudinal direction of the extension on the PS is removed, further P-type auxiliary diffusion layer FLP _S smaller portions than the size of the substrate contact (A portion similar to the N-type auxiliary diffusion layer FLN _S ) is deleted.

Steps S1 to S described above
The operation of No. 4 is executed based on the following design rule. That is, 1) to place the P-type auxiliary diffusion layer FLP _S or N-type auxiliary diffusion layer FLN _S in a region that does not overlap with the polysilicon gates in all of the LSI including a polysilicon gate PS.

2) P-type auxiliary diffusion layer F in the design rule
The auxiliary diffusion layer narrower than the minimum width (length of one side of the substrate contact) of LP _S or N type auxiliary diffusion layer FLN _S is deleted.
The P-type auxiliary diffusion layer FLP so as to satisfy the above design rules
By disposing the _S or N type auxiliary diffusion layer FLN _S , it is not necessary to check the design rule after the layout design.

Next, referring to FIG. 5, A- in FIG.
An element cross-sectional structure in the case where the A ′ part is manufactured as an actual element will be described. As shown in FIG. 5, A in FIG.
When fabricated -A 'part as the actual element, P ^- type substrate P-type well layer PW is formed on the B, and spaced apart from each other thereon N-type diffusion layer FLN and P-type auxiliary diffusion layer FLP _S
Is formed. Further, the field region F is formed in the region including the peripheral portion of the P-type well layer PW.

[0068] Further, the N-type diffusion layer FLN and P-type auxiliary diffusion layer FLP _S, PSG; ground layer GND via the insulating layer I of (Phosho-Silicate Glass phosphorus silicate glass film) or the like is formed by aluminum deposition or the like To be done. At that time, the ground layer G
Part of the ND and the N-type diffusion layer FLN is conducted, and this part becomes the contact CO.

If it is determined in step S3 that a figure smaller than the substrate contact does not exist (step S3).
3; YES), as described above, the N-type auxiliary diffusion layer FLN _S
Or P-type auxiliary diffusion layer FLP auxiliary diffusion layer arrangement data corresponding to the area for arranging the _S is added to the cell C of the design data inputted in the beginning, then, P-type auxiliary diffusion layer FLP _S or N-type auxiliary diffusion A substrate contact is arranged in the region on the power supply layer V _SS or the ground layer GND on the layer FLN _S (step S5). In the processing of step S5, based on the substrate contact data inputted from the keyboard 1 or reader 2 (. Indicating the size of the substrate contacts), P-type auxiliary diffusion layer FLP _S or N-type auxiliary diffusion layer FLN
_The substrate contact is arranged in the region on the power supply layer V _SS or the ground layer GND on _S where the substrate contact can be arranged. At this time, the substrate contacts may be arranged in all the regions in which the substrate contacts can be arranged, or may be arranged in only one substrate contact arrangement region in one cell C where the substrate contacts can be arranged. Further, if there is no region where the substrate contact can be arranged in one cell C, the substrate contact can be arranged in the adjacent cell C, thereby substituting the function of the substrate contact in the one cell C. Good.

The result of executing the process of step S5 is shown in FIG.
Shown in 6 is a the P-type auxiliary diffusion layer FLP _S or N-type auxiliary diffusion layer FLN _S, of the area on the power supply layer V _SS or ground layer GND, the substrate contact is available space all placement substrate contact CO _S is located.

Next, referring to FIG. 7, B- in FIG.
The element cross-sectional structure in the case where the B ′ part is manufactured as an actual element will be described. As shown in FIG. 7, B in FIG.
When fabricated -B 'part as the actual element, in addition to the device structure shown in FIG. 5, the conductive part of the ground layer GND and the P-type auxiliary diffusion layer FLP _S, this portion becomes a substrate contact CO _S ing.

In step S5, the substrate contact C
After setting the position of the O _S is the substrate contact C
O _S substrate contact arrangement data corresponding to the positions of said auxiliary diffusion layer arranged data is further added to the design data of the added cell C, is stored in the storage device 6.

Thereafter, based on the design data of the cell C to which the stored auxiliary diffusion layer arrangement data and the stored substrate contact arrangement data are stored, an element having a structure as shown in FIG. 7 is actually manufactured by using the LSI manufacturing technique. To be done.

As described above, according to this embodiment,
P-type auxiliary diffusion layer FLP _S or N-type auxiliary diffusion layer FLN _S corresponding regions and a region corresponding to the substrate contacts CO _S in is automatically searched, auxiliary diffusion layer arrangement data and the substrate contact arrangement data based on this because it is added to the design data of the cell C, the auxiliary diffusion layer FLP _S (or FLN
_S ) and substrate contact CO _S , the LSI can be designed by automating the production of design data. Further, it is not necessary to perform a check based on the design rule after designing.

[0075]

As described above, according to the invention described in claim 1 or 5, the substrate contact arrangement area is automatically searched, and the arrangement data for arranging the substrate contact is based on the area. Since it is added to the design data of, the production of the design data for arranging the board contact can be automated.

Therefore, since it is not necessary for the designer to determine the arrangement of the board contacts and to confirm the design rule for the board contacts, the time required for the cell layout design can be greatly shortened and the design efficiency can be improved. Is improved.

According to the second or sixth aspect of the invention, the auxiliary diffusion layer arrangement area and the substrate contact arrangement area are automatically searched, and the auxiliary diffusion layer arrangement data and the substrate contact arrangement data are stored in the cell based on this. Since it is added to the design data, the production of the design data for arranging the auxiliary diffusion layer region and the substrate contact can be automated.

Therefore, it is not necessary for the designer to determine the arrangement of the auxiliary diffusion layer and the substrate contact, and it is not necessary to confirm the design rule for the auxiliary diffusion layer and the substrate contact. Can be significantly shortened and the design efficiency can be improved.

According to the third or seventh aspect of the present invention, the substrate contact arrangement area is automatically searched and the arrangement data for arranging the substrate contact is added to the cell design data based on this. The LSI can be designed by automating the production of design data for arranging the board contacts.

Therefore, since it is not necessary for the designer to determine the arrangement of the board contacts and to confirm the design rule for the board contacts, the time required for the LSI design including the cell layout can be greatly reduced. ,
Design efficiency is improved.

According to the fourth or eighth aspect of the invention, the auxiliary diffusion layer arrangement area and the substrate contact arrangement area are automatically searched, and the auxiliary diffusion layer arrangement data and the substrate contact arrangement data are stored in the cell based on this. Since it is added to the design data, the LSI can be designed by automating the production of the design data for arranging the auxiliary diffusion layer region and the substrate contact.

Therefore, it is not necessary for the designer to determine the arrangement of the auxiliary diffusion layer and the substrate contact, and further, it is not necessary to confirm the design rule for the auxiliary diffusion layer and the substrate contact, so that the LSI design including the cell layout is performed. The time required for designing can be greatly reduced and the design efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram of an LSI design device according to an embodiment.

FIG. 2 is a flowchart showing an operation of a substrate contact placement process of the embodiment.

FIG. 3 is a diagram showing an arrangement of auxiliary diffusion layers in an example.

FIG. 4 is a diagram showing the arrangement of a modified auxiliary diffusion layer in the example.

5 is a diagram showing an actual element cross-sectional structure of a portion AA ′ in FIG.

FIG. 6 is a diagram showing the arrangement of substrate contacts according to the operation of the embodiment.

FIG. 7 is a diagram showing an actual element cross-sectional structure of a BB ′ portion in FIG.

FIG. 8 is a diagram showing a configuration of a cell (CMOS FET) in a conventional technique.

FIG. 9 is a diagram showing an arrangement of substrate contacts according to a conventional technique.

[Explanation of symbols]

1 ... Keyboard 2 ... reading device 3 ... processing apparatus 4 ... ROM 5 ... display 6 ... storage device 7 ... printer 10P ... P-channel FET 10 N ... N-channel FET B ... P ^- -type substrate C ... cell CO ... Contacts CO _S ... substrate Contact I ... Insulating film F ... Field region FLP ... P type diffusion layer FLP _S ... P type auxiliary diffusion layer FLN ... N type diffusion layer FLN _S ... N type auxiliary diffusion layer PW ... P type well layer NW ... N type well layer PS … Polysilicon gate IN… Input terminal OUT… Output terminal V _SS … Power supply layer GND… Ground layer S… LSI design device

Claims (8)

[Claims] 1. A substrate for electrically connecting an auxiliary diffusion layer and a power supply layer or a ground layer, which have a relationship of hole density and conduction electron density opposite to that of a diffusion layer which constitutes a cell. In a cell layout design method for arranging a contact in the auxiliary diffusion layer region corresponding to the auxiliary diffusion layer, the input design data of the cell and substrate contact data indicating a preset size of the substrate contact are used. A search step of searching for at least one substrate contact placement region in which the substrate contact can be placed in the auxiliary diffusion layer region, and the auxiliary diffusion layer region corresponding to the searched substrate contact placement region. A data adding step of adding arrangement data for arranging the board contact inside the design data and outputting the additional design data. , Cell layout design method characterized in that it comprises a. 2. An auxiliary diffusion layer having a relationship between a hole density and a conduction electron density which is opposite to a relationship between a hole density and a conduction electron density of a diffusion layer constituting a cell, and the auxiliary diffusion layer and a power supply layer or a ground layer. In a cell layout designing method for arranging a substrate contact for conducting between and in an auxiliary diffusion layer region corresponding to the auxiliary diffusion layer, the auxiliary diffusion layer in the cell is arranged based on the input design data of the cell. A first search step of searching for an auxiliary diffusion layer arrangement area that can be arranged, and an auxiliary diffusion layer arrangement for arranging the auxiliary diffusion layer in the cell corresponding to the searched auxiliary diffusion layer arrangement area A first data adding step of adding data to the design data and outputting a first additional design data; and a base indicating the size of the first additional design data and the preset substrate contact. A second search step of searching for at least one substrate contact placement region in which the substrate contact can be placed in the auxiliary diffusion layer placement region based on plate contact data; and the searched substrate contact placement A second data adding step of adding substrate contact arrangement data for arranging the substrate contact in the auxiliary diffusion layer arrangement area corresponding to the area to the first design data and outputting second additional design data; And a cell layout designing method. 3. An auxiliary diffusion layer and a power source layer having a relationship between the hole density and the conduction electron density which is opposite to the relationship between the input cell design data and the hole density and conduction electron density of the diffusion layer constituting the cell. Alternatively, at least one of the substrate contacts can be arranged in the auxiliary diffusion layer region corresponding to the auxiliary diffusion layer on the basis of preset substrate contact data indicating the size of the substrate contact that conducts with the ground layer. Search step for searching for the substrate contact placement area, and adding layout data for placing the board contact in the auxiliary diffusion layer area to the design data in correspondence with the searched board contact placement area. A cell layout design process including a data addition process for outputting design data, and inputting the cell design data and the board contact data. Input step and, LSI designing method characterized by and a display step of displaying a cell layout based on the additional design data. 4. The auxiliary diffusion layer arranged in the cell based on the inputted cell design data, and the positive density opposite to the relationship between the hole density and the conduction electron density of the diffusion layer constituting the cell. A first search step of searching for an auxiliary diffusion layer arrangement region in the cell in which an auxiliary diffusion layer having a relationship between pore density and conduction electron density can be arranged, and a first search step corresponding to the searched auxiliary diffusion layer arrangement region A first data adding step of adding auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell to the cell design data, and outputting first additional design data; and the first additional design data and Based on preset substrate contact data indicating a size of a substrate contact arranged in the auxiliary diffusion layer arrangement region, which makes the auxiliary diffusion layer electrically connect to the power supply layer or the ground layer. A second search step of searching at least one substrate contact placement region in which the substrate contact can be placed in the auxiliary diffusion layer placement region; and the second search step corresponding to the searched substrate contact placement region. A cell layout designing step comprising: a second data adding step of adding substrate contact placement data for placing the substrate contact in the auxiliary diffusion layer placement region to the first design data and outputting second additional design data. An LSI design method comprising: an input step of inputting the cell design data and the substrate contact data; and a display step of displaying a cell layout based on the second additional design data. 5. A substrate for electrically connecting an auxiliary diffusion layer and a power supply layer or a ground layer, which has a relationship of hole density and conduction electron density opposite to that of a diffusion layer forming a cell. In a cell layout design device for arranging a contact in an auxiliary diffusion layer region corresponding to the auxiliary diffusion layer, the input cell design data and substrate contact data indicating a preset size of the substrate contact are used. Search means for searching at least one substrate contact placement region in which the substrate contact can be placed in the auxiliary diffusion layer region, and the search means in the cell corresponding to the searched substrate contact placement region. Data adding means for adding layout data for arranging board contacts to the design data and outputting the additional design data. A cell layout design device characterized in that 6. An auxiliary diffusion layer having a relationship between a hole density and a conduction electron density which is opposite to a relationship between a hole density and a conduction electron density of a diffusion layer constituting a cell, and the auxiliary diffusion layer and a power supply layer or a ground layer. In a cell layout design device for arranging a substrate contact that conducts with the auxiliary diffusion layer in the auxiliary diffusion layer region corresponding to the auxiliary diffusion layer, the auxiliary diffusion layer in the cell is set based on the input design data of the cell. First searching means for searching an auxiliary diffusion layer arrangement area that can be arranged, and auxiliary diffusion layer arrangement for arranging the auxiliary diffusion layer in the cell corresponding to the searched auxiliary diffusion layer arrangement area First data adding means for adding data to the design data and outputting first additional design data; and a base for indicating the size of the first additional design data and the preset substrate contact. Second search means for searching at least one substrate contact placement region in which the substrate contact can be placed in the auxiliary diffusion layer placement region based on plate contact data; and the searched substrate contact placement Second data adding means for adding substrate contact arrangement data for arranging the substrate contact in the auxiliary diffusion layer arrangement area to the first design data and outputting second additional design data corresponding to the area; A cell layout design apparatus comprising: 7. An auxiliary diffusion layer and a power supply layer having the relationship between the hole density and the conduction electron density, which is opposite to the relationship between the input cell design data and the hole density and conduction electron density of the diffusion layer forming the cell. Alternatively, at least one of the substrate contacts can be arranged in the auxiliary diffusion layer region corresponding to the auxiliary diffusion layer on the basis of preset substrate contact data indicating the size of the substrate contact that conducts with the ground layer. Search means for searching the substrate contact placement area, and placement data for placing the substrate contact in the auxiliary diffusion layer area corresponding to the searched substrate contact placement area are added to the design data. A cell layout designing means including a data adding means for outputting design data; and inputting the cell data and the board contact data. Input means for, LSI designing apparatus comprising: a display means for displaying the cell layout based on the additional design data. 8. Based on the input cell design data, an auxiliary diffusion layer arranged in the cell, wherein the diffusion layer constituting the cell has a positive hole density and a conduction electron density which are opposite to each other. First search means for searching an auxiliary diffusion layer arrangement region in the cell in which an auxiliary diffusion layer having a relationship between hole density and conduction electron density can be arranged, and a first search means corresponding to the searched auxiliary diffusion layer arrangement region. And a first data adding means for adding auxiliary diffusion layer arrangement data for arranging the auxiliary diffusion layer in the cell to the cell design data and outputting first additional design data, and the first additional design data and Based on preset substrate contact data indicating a size of a substrate contact arranged in the auxiliary diffusion layer arrangement region, which makes the auxiliary diffusion layer electrically connect to the power supply layer or the ground layer. Second search means for searching at least one substrate contact placement region in which the substrate contact can be placed in the auxiliary diffusion layer placement region, and the second search means corresponding to the searched substrate contact placement region. A cell layout designing means comprising: a second data adding means for adding substrate contact arrangement data for arranging the substrate contact in the auxiliary diffusion layer arrangement area to the first design data and outputting second additional design data. An LSI design apparatus comprising: an input unit that inputs the cell design data and the substrate contact data; and a display unit that displays a cell layout based on the second additional design data.