JPH08339342A - Channel controller - Google Patents

Abstract

PURPOSE: To provide a channel controller having a high data transfer processing efficiency by detecting channel buffers having free areas and preferentially controlling the data write to the channel buffer, where data is not held at all, out of channel buffers. CONSTITUTION: A channel controller 2 includes channels 22-1 to 22-N provided correspondingly to peripheral devices 3-1 to 3-N, a channel control part 23 which sends a channel number calculation signal 204 indicating the channel to be controlled in accordance with a memory request signal 201 and an idle signal 204 from each channel 22, and a storage control part 21 which sends data in a main storage device 1 to one of channels 22 in accordance with the channel calculation signal 204. Thus, the idle signal also is referred to settle the channel number, and data is preferentially written in the channel buffer where data is not held at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel control device, and more particularly to a channel control device for transferring data between a main memory device and peripheral devices.

[0002]

2. Description of the Related Art Generally, a supercomputer is provided with an input / output channel device for processing a large amount of data between a main storage device and peripheral devices at high speed.

A plurality of channels are usually connected not only to a super computer but also to an input / output channel device of a large general-purpose computer. Usually, all the connected channels are controlled by one storage control unit, so that it is necessary to efficiently issue a request from the channel or an instruction to the channel to all the channels.

Conventionally, this type of channel control device controls a data transfer between a memory control unit and a peripheral device and a memory control unit for controlling data transfer between a main memory device and a channel. A channel, a buffer built in this channel for temporarily storing transfer data between the storage control unit and peripheral devices, and a channel that issues a channel index signal to the storage control unit in response to a request from the channel. And a control unit.

The channel controller manages the data transfer between the main memory and the peripheral devices. In the channel control device, the storage control unit controls data transfer between the main storage device and the channel. The channel requests a memory request from the channel control unit when the buffer in the channel has a free space.

Upon receipt of the memory request, the channel control unit cyclically selects a channel number from the channels which are issuing memory requests at that time, and issues the channel number to the storage control unit. For example, it is assumed that the channel control device has 10 channels numbered 0 to 9, and the channel control unit cyclically indexes channels in the order of channels 0, 1, 2 ,. Then, if channel 0 is currently being processed, the channel control unit issues the index of channel 1 to the storage control unit as the channel to be processed with the highest priority, to the storage control unit. Similarly, if channel 9 is being processed, channel 0 is the channel to be processed with the highest priority.

An apparatus of this type is also disclosed in Japanese Patent Laid-Open No. 5-128044. This is because the free area of the buffer in the channel is detected by the difference between the write pointer and the read pointer and the memory request is output, and when the requests conflict with each other, the request of the younger or older channel is given priority. It is a configuration that accepts.

[0008]

However, in each of the above-mentioned conventional channel control devices, the priority order of requests is cyclically determined, so that the data transfer processing efficiency of the entire system is not necessarily high. .

Japanese Patent Laid-Open No. 5-173923 discloses a device for predicting a data overrun and prioritizing requests based on the data transfer rate and the like. However, the publication does not specifically disclose a method of predicting data overrun, and cannot improve processing efficiency.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a channel control device having high data transfer processing efficiency.

[0011]

A channel control device according to the present invention has N channels (N is an integer of 2 or more, the same applies hereinafter) for temporarily holding data to be transferred between a main memory device and a peripheral device. A channel control device for controlling writing of data to a buffer in a predetermined priority order, and first detecting means for detecting one of the N channel buffers that does not hold any data, and the detection means. Channel control means for preferentially controlling data writing to the selected channel buffer.

In addition to the above configuration, another channel control device according to the present invention further includes second detection means for detecting a free area among the N channel buffers. Is characterized in that data write control is preferentially performed on the channel buffer detected by the first detecting means and detected by the second detecting means.

[0013]

In addition to detecting an empty area of the channel buffer, an empty area of the channel buffer is detected. Data write control is preferentially performed for a channel buffer that does not hold any data.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a channel control device according to the present invention. In the figure, a channel controller 2 according to an embodiment of the present invention includes a main memory device 1 and a peripheral device 3-i (i = 1, 2, ...
Is provided between the two devices and controls the data transfer between both devices.

The channel control device 2 of this example comprises a peripheral device 3
-Channels 22-i provided corresponding to each of i,
Memory request signal 201 from each channel 22-i
And a channel control unit 23 for transmitting a channel number indexing signal 204 indicating a channel to be controlled according to the idle signal 202, and a channel in which data in the main storage device 1 is channeled according to the channel number indexing signal 204 transmitted. 22-i, and the storage control unit 21 for sending to any of the units 22-i.

Each channel 22-i includes a channel buffer 221-i for temporarily holding data to be sent to the corresponding peripheral device 3-i, and an idle signal 202 when the channel buffer is not busy. Is sent.

The channel controller 23 controls each channel 22-
A register 232 which has a bit corresponding to i and whose bit is set to "1" only while the memory request signal is transmitted from the corresponding channel, an N-bit output signal 205 of this register 232, and each channel 22 -
Priority channel determination circuit 233 that ANDs corresponding bits with the N-bit idle signal 202 from i.
And a channel number determining circuit 231 that sends out a channel number indexing signal 204 according to the N-bit output signal of the determination circuit 233 and the N-bit output signal 205 of the register 232.

In such a configuration, the channel control device 2
Controls data transfer between the main storage device 1 and the peripheral device 3-i. The storage control unit 21 determines the channel number to process the memory request by the channel number indexing signal 204 from the channel number determination circuit 231 in the channel control unit 23. Then, the control unit 21 causes the main storage device 1 and the channel buffer 2 for the channel
21-i to control the flow of data.

The channel 22-i controls the flow of data between the storage controller 21 and the peripheral device 3-i. Also,
When a certain amount of data in the buffer 221 is transferred and an empty area is created in the buffer, the memory request signal 201 is issued to the register 232.

Each buffer 221-i has a storage controller 21.
The data between the peripheral device 3-i and the peripheral device 3-i are temporarily stored. Each of the buffers 221-i has no stored data in the buffers (is not in a busy state),
The idle signal 202 is issued to the priority channel determination circuit 231 in the channel control unit 23.

When the memory request signal 201 from the channel 22 is received, the register 232 holds which channel the signal is from. In response to this holding, the storage control unit 21 performs memory request processing for the channel. That is, the storage control unit 21 uses the main storage device 1
Send data from the channel to that channel. Then, until the holding area corresponding to the channel in the register 232 is reset, the channel number determination circuit 231 and the priority channel determination circuit 23 in the channel control unit 23.
The memory request signal corresponding to the channel is distributed to the channels 3 and 3.

The priority channel determination circuit 233 has two inputs, a memory request signal corresponding to each channel distributed from the register 232 and an idle signal 202 indicating that the transfer data of the buffer 221 has been exhausted.
In this priority channel determination circuit 233, the memory request signal 201 and the idle signal 202 from the same channel are both True (the memory request is issued from a certain channel, and the channel from which the memory request is issued When the idle signal indicating that the transfer data of the buffer has been exhausted is issued), the priority indexing signal 203 is issued to the channel number determination circuit 231.

The channel number decision circuit 231 has two inputs, a memory request signal from the register 232 and a priority index signal 203 from the priority channel determination circuit 233. Normally, the channel number determination circuit 231 determines the channel number of the channel to be processed by the memory request signal from the register 232, and issues the channel number indexing signal 203 to the storage controller 21. When the priority indexing signal 203 from the priority channel determining circuit 233 is received, the channel number indicated by the priority indexing signal 203 is set as the channel number to be preferentially processed, and the channel number indexing signal 204 is used. The storage control unit 21 is notified.

The storage control unit 21 receives the channel number determined by the channel determining circuit 231 in the channel control unit 23 by the channel number indexing signal 204, and performs memory request processing for the channel. That is, the data from the main storage device 1 is sent to the channel.

Normally, the channel number determination circuit 231 is
The memory request signal obtained by the register 232 is cyclically indexed by a well-known round robin algorithm or the like to determine the channel number. Here, the priority channel determination circuit 233 receives an idle signal generated due to the lack of transfer data in the buffer 221, and the priority indexing signal 203 is sent to the channel number determination circuit 2.
When issued to 31, the channel number determining circuit 231 preferentially indexes the channel number obtained from the received priority indexing signal. By such control, the channel can be effectively used, and the processing efficiency of the system can be improved.

Here, the channel number determining circuit 231 will be described. 2 is a block diagram showing an internal configuration of the channel number determination circuit in FIG. 1, and the same parts as those in FIG. 1 are designated by the same reference numerals.

In the figure, a channel number determining circuit 23
1 is a counter 60 that maximizes the number “N” of channels (“1” is next to “N”), and this counter 6
Decoder 5 that decodes the count value output from 0 and sets one signal line corresponding to channels 1 to N to "1"
0, an AND gate group 70 that logically ANDs the output signal 205 of the register 233, which is a memory request signal from each channel, and the signal from the decoder 50, and the register 10 that holds the output of this AND gate group 70. It is composed of.

The channel number determination circuit 231 also stores the register 20 for holding the priority indexing signal from the priority channel determination circuit 233 and the firmware 40 for writing the register 30 according to the outputs of the registers 10 and 20.
And a register 30 for transmitting a channel number indexing signal written by the firmware 40.

In such a configuration, the counter 60 performs an operation of incrementing by 1 from "1" to "N", and this count value is constantly input to the decoder 50. The decoder 50 decodes the count value and outputs 1
The value of the signal line corresponding to each channel from 1 to N is set to "1". That is, only one of the signal lines 1 to N extending from the decoder 50 becomes “1”. If the memory request signal corresponding to each channel and the signal from the decoder 50 corresponding to each channel are both "1", "1" is written in the bit corresponding to that channel in the register 10. Be done.

The idle signal 203 from the channel is written in the register 20 as it is. Firmware 4
0 uses both the data held in the registers 10 and 20 to determine the final channel number and writes the result in the register 30.

Further description will be given with reference to FIG. FIG. 3 is a flowchart showing the operation of the firmware 40 shown in FIG. In the figure, first, the firmware reads the contents of the register 10 (step 301) and judges whether all the bits of the register 10 are "0" (step 302). If all the bits of the register 10 are "0", the reading in step 301 is continued (step 302 → 301).

When all the bits of the register 10 are not "0" (even if there is one bit "1"), the contents of the register 20 are read this time (step 303), and all the bits of the register 20 are "0". It is determined (step 304).

If all the bits of the register 20 are "0", it can be judged that the idle signal is not transmitted from any channel. Therefore, in this case, the channel number is determined from the contents of the register 10 and the register 3
Write the value to 0.

On the other hand, all the bits of the register 20 are "0".
If not (if there is 1 in 1 bit), it can be determined that the idle signal is transmitted from any channel. Therefore, in this case, the channel number is determined from the contents of the register 20 and the value is written in the register 30.

In short, not only is the channel number determined in accordance with the memory request signal, but the channel number is also determined by referring to the idle signal sent when no data is held in the channel buffer. By preferentially writing data to the channel buffer in which no data is held, the processing efficiency can be improved.

In the conventional device, even if the usage status of the channel buffer is different for each channel, the usage status of the channel buffer is not reflected in the processing for determining the channel number, and a deviation occurs in the memory request processing of each channel. That reduced the processing efficiency of the entire system. On the other hand, in this apparatus, the usage state of the channel buffer is reflected in the channel number confirmation processing, thereby eliminating the deviation of the channel memory request processing and preventing the system processing efficiency from deteriorating.

That is, the channel issues a memory request to the channel controller 23 when a certain amount of free space is generated in the channel buffer. However, since the channel control unit 23 cyclically determines the channel number, it takes time from when the channel issues a memory request to when the channel is indexed by the channel control unit and the memory request process is executed. Wait until the turn of the channel comes). If there is no more data in the channel buffer during that period, the channel issues an idle signal 202 to the channel controller 23. The channel control unit 23 monitors the memory request signal 201 and the idle signal 202 from the same channel, and when both the memory request signal and the idle signal from the same channel are True (“1”), the storage control device 1 Preferentially index that channel to.

Although the channel issues the memory request signal to the channel control unit 23, when the data in the channel buffer is exhausted, the idle signal 202 is issued to the channel control unit 23. As a result, the channel control unit 23 can preferentially perform the memory request processing for the channel over the other channels, and thus can control the channel in the usage state of the channel buffer.

[0040]

As described above, the present invention has the effect that the data transfer processing efficiency can be improved by performing processing by referring to the usage status of the channel buffer in addition to the memory request signal. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a channel control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a channel number determination circuit in FIG.

FIG. 3 is a flowchart showing the operation of firmware in the channel number determination circuit of FIG.

[Explanation of symbols]

 1 Main Storage Device 2 Channel Control Device 3-1 to 3-N Peripheral Device 21 Storage Control Device 22-1 to 22-N Channel 23 Channel Control Unit 221-1 to 221-N Channel Buffer 231 Channel Number Confirmation Circuit 232 Register 233 Priority channel judgment circuit

Claims (3)

[Claims] 1. Data write control is performed with a predetermined priority to N (N is an integer of 2 or more) channel buffers that temporarily hold data to be transferred between a main memory device and a peripheral device. A channel control device, which detects first one of the N channel buffers in which no data is held, and write control of data preferentially to the detected channel buffer. And a channel control means for performing the above. 2. The first detecting means determines that no data is held in the channel buffer when any of the N channel buffers is not busy. Channel controller. 3. Further comprising second detecting means for detecting one of the N channel buffers having a free area,
2. The channel control means preferentially performs data write control on the channel buffer detected by the first detection means and detected by the second detection means. 2. The channel control device according to 2.