JPH08335828A - Voltage control oscillator and integrated bias circuit - Google Patents

Voltage control oscillator and integrated bias circuit

Info

Publication number
JPH08335828A
JPH08335828A JP7143046A JP14304695A JPH08335828A JP H08335828 A JPH08335828 A JP H08335828A JP 7143046 A JP7143046 A JP 7143046A JP 14304695 A JP14304695 A JP 14304695A JP H08335828 A JPH08335828 A JP H08335828A
Authority
JP
Japan
Prior art keywords
circuit
controlled oscillator
substrate
voltage controlled
impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7143046A
Other languages
Japanese (ja)
Other versions
JP3435901B2 (en
Inventor
Yoshihiko Imai
芳彦 今井
Mitsuhiro Shimozawa
充弘 下沢
Kenji Ito
健治 伊東
Akio Iida
明夫 飯田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14304695A priority Critical patent/JP3435901B2/en
Publication of JPH08335828A publication Critical patent/JPH08335828A/en
Application granted granted Critical
Publication of JP3435901B2 publication Critical patent/JP3435901B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

PURPOSE: To provide a compact voltage control oscillator and a compact integrated bias circuit which have the reduced phase noise changes caused by the oscillation frequency and also can be tuned to the wide bands. CONSTITUTION: A tuning circuit consists of a serial resonance circuit including of a varactor diode 2 and a serial inductor 3 and an impedance transformer 4 which inverts the impedance with desired frequency. A negative resistance amplifier circuit consists of a field effect transistor 1 and a feedback inductor 5 and then partly feeds the oscillation power that is supplied to a load resistor 7 to the input side via a capacitor 6. Then the transformer 4 having transformation ratio (n) applies the impedance inversion to the Junction capacity Cj and the equivalent serial resistance Rs of the diode 2 to transform them into a parallel circuit of inductance Cj /n<2> and conductance n<2> Rs . The transformer 4 also applies the impedance inversion to the serial inductance Ls and transforms it into the parallel capacitance n<2> Ls .

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明はマイクロ波/ミリ波帯
に適用する電圧制御発振器(VCO)とマイクロ波回路
一般に適用する集積バイアス回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator (VCO) applied to a microwave / millimeter wave band and an integrated bias circuit applied to a microwave circuit in general.

【0002】[0002]

【従来の技術】たとえば文献(Kimishima
M.etal.:“A Semi−Monolithi
c Wideband VCO with Outpu
t Power Control Copabilit
y Using an Active Power S
plitter”,IEEE MTT−S Diges
t,HH−6,pp.1317−1320,1992)
に示す従来例のマイクロ波帯VCOは図22(a)のよ
うに、第1の同調回路は、バラクタダイオード2aと並
列インダクタ3aから成る並列共振回路から構成する。
第2の同調回路は、バラクタダイオード2bと並列イン
ダクタ3bから成る並列共振回路から構成する。増幅回
路は、電界効果トランジスタ1で構成し、発振電力を負
荷抵抗7に出力する。またたとえば特開平4−3120
04号公報に示す従来例のマイクロ波帯VCOは図23
(a)のように、同調回路は、バラクタダイオード2と
所望発振周波数で概90度の電気長をもつ特性アドミタ
ンスYt の伝送線路4aと所望発振周波数で概180度
の電気長をもつ先端開放線路20とから構成する。増幅
回路は、電界効果トランジスタ1と直列帰還インダクタ
5とから構成し、発振電力を負荷抵抗7に出力する。ま
た一般に従来例のマイクロ波帯VCOは図24(a)の
ように、バラクタダイオード2を基板122上に取り付
けるとき、基板上の取付パターン127と地導体間でバ
ラクタダイオード2に並列の固定浮遊容量Caを図24
(b)のように付加することになる。さらにバラクタダ
イオード2を電界効果トランジスタ1に密結合し広帯域
発振器を形成する場合には、マイクロストリップ線路1
23を低インピーダンス線路にし、電界効果トランジス
タ1用とバラクタダイオード2用各バイアス回路124
と125を高周波漏れ込みの少ない高インピーダンス線
路にする。
2. Description of the Related Art For example, a document (Kimishima)
M. et al. : "A Semi-Monolithi
c Wideband VCO with Outpu
t Power Control Cobilit
y Using an Active Power S
"plitter", IEEE MTT-S Diges
t, HH-6, pp. 1317-1320, 1992).
As shown in FIG. 22A, in the microwave band VCO of the conventional example shown in FIG. 22, the first tuning circuit is composed of a parallel resonant circuit including a varactor diode 2a and a parallel inductor 3a.
The second tuning circuit is composed of a parallel resonant circuit including a varactor diode 2b and a parallel inductor 3b. The amplifier circuit is composed of the field effect transistor 1 and outputs the oscillation power to the load resistor 7. Further, for example, Japanese Patent Laid-Open No. 4-3120
The microwave band VCO of the conventional example shown in Japanese Patent No. 04 is shown in FIG.
(A) As in the tuning circuit, an open end having an electrical length of approximate 180 degrees by a transmission line 4a and the desired oscillation frequency characteristic admittance Y t with an electrical length of approximate 90 degrees varactor diode 2 and the desired oscillation frequency It is composed of the line 20. The amplifier circuit includes a field effect transistor 1 and a series feedback inductor 5, and outputs oscillation power to the load resistor 7. Further, generally, in the microwave band VCO of the conventional example, when the varactor diode 2 is mounted on the substrate 122 as shown in FIG. 24A, a fixed stray capacitance parallel to the varactor diode 2 is provided between the mounting pattern 127 on the substrate and the ground conductor. Figure 24 shows Ca
It will be added as shown in (b). Further, when the varactor diode 2 is tightly coupled to the field effect transistor 1 to form a wide band oscillator, the microstrip line 1
Bias circuits 124 for the field effect transistor 1 and the varactor diode 2 are used as the low impedance line 23.
And 125 are high impedance lines with little high frequency leakage.

【0003】上記従来例のマイクロ波帯VCOは、広帯
域発振の難易と発振周波数による位相雑音変化の多少と
が二律背反の関係になり広帯域特性と雑音特性をトレー
ドオフする方式を採る。
The conventional microwave band VCO employs a system in which the difficulty of wideband oscillation and the amount of change in phase noise due to the oscillation frequency are in a trade-off relationship, and the wideband characteristic and the noise characteristic are traded off.

【0004】上記従来例は図22(a)のように、電界
効果トランジスタ1のソースとゲート端子から第1と第
2の並列共振回路を見込むアドミタンスYs5とYg3は、
次のようになる。 Ys5=1/jωLp1+1/(Rs +1/JωCj ) =1/jωLp1+{jωCj +(ωCj2s }/ {1+(ωCjs2 } ≒1/jωLp1+jωCj +(ωCj2s (∵1≫(ωCjs2 ) Yg3≒1/jωLP2+jωCj +(ωCj2s ここにCj とRS はバラクタダイオード2aと2bの接
合容量と等価直列抵抗、LP1とLP2は並列インダクタ3
aと3bのインダクタンスを表す。従ってYS5とYg3
一方が容量性、他方が誘導性になるように印加電圧に応
じCj を変え周波数制御をし発振周波数を変えるとき、
S5とYg3のコンダクタンス成分(ωCj2s が大
きく変わるから共振回路のQは大きく変わり、図22
(b)のようにQが大きいときは位相雑音が低くなり、
Qが小さいときは位相雑音が高くなって、発振周波数に
よる位相雑音の変化が大きい。また図23(b)のよう
に伝送線路4aの作用でバラクタダイオード2の接合容
量(Cj )と等価直列抵抗(Rs )がインピーダンス反
転され、それぞれインダクタンス(Lv =−(Yt2
/ω2j )とコンダクタンス(Gv =Rst 2)にな
り、一方先端開放線路20は等価インダクタンス(L
r )とキャパシタンス(Cr )とコンダクタンス(G
r )の並列回路で表わされるから、図23(a)のよう
に電界効果トランジスタ1のソース端子から同調回路側
を見込むアドミタンスYs6は、次のようになる。 Ys6=(Yt2 ・(Rs +1/jωCj ) +(Gr +jωCr +1/jωLr ) =(Yt2s +Gr +j{(ωCr −1/ωLr ) −(Yt2 /ωCj } 従って|ωCr −1/ωLr |≧|(Yt2 /ωCj
|となり、発振周波数の帯域はLr とCr でほぼ決まる
とともに、Ys6のコンダクタンス成分(Yt2s
r はCj に依存しないから共振回路のQは一定とな
り、発振周波数による位相雑音の変化は少ない。また図
24(a)のように形成すると、バラクタダイオード2
の接合容量変化比na (Ca のあるとき)は、次のよう
になる。 na =(Cjmax+Ca )/(Cjmin+Ca ) =(ni ・Cjmin+Ca )/(Cjmin+Ca ) ={ni ・(Cjmin+Ca )−(ni −1)−Ca }/ (Cjmin+Ca ) =ni −{(ni −1)・Ca }/(Cjmin+Ca ) <nia =ε0 εr S/d ここにCjmaxとCjminはCj の最大と最小値、ni はバ
ラクタダイオード2の接合容量変化比(Ca のないと
き)、ε0 とεr は真空と基板122の誘電率、Sは取
付パターン127の面積、dは基板122の厚さを表
す。従ってCa が大きくなるほどna は低下し、発振周
波数の帯域は狭くなり所望の発振周波数帯域が得られな
くなる。
In the above conventional example, as shown in FIG. 22 (a), the admittances Y s5 and Y g3 that allow the first and second parallel resonant circuits to be seen from the source and gate terminals of the field effect transistor 1 are:
It looks like this: Y s5 = 1 / jωL p1 + 1 / (R s + 1 / JωC j ) = 1 / jωL p1 + {jωC j + (ωC j ) 2 R s } / {1+ (ωC j R s ) 2 } ≈1 / jωL p1 + jωC j + (ωC j ) 2 R s (∵1» (ωC j R s) 2) Y g3 ≒ 1 / jωL P2 + jωC j + (ωC j) 2 R s wherein the C j and R S is a varactor diode Junction capacitance of 2a and 2b and equivalent series resistance, L P1 and L P2 are parallel inductors 3
It represents the inductance of a and 3b. Therefore, when changing the oscillation frequency by changing C j according to the applied voltage so that one of Y S5 and Y g3 becomes capacitive and the other becomes inductive,
Since the conductance component (ωC j ) 2 R s of Y S5 and Y g3 changes significantly, the Q of the resonance circuit changes greatly.
When Q is large as in (b), the phase noise is low,
When Q is small, the phase noise is high and the change in the phase noise due to the oscillation frequency is large. Further, as shown in FIG. 23B, the junction capacitance (C j ) and the equivalent series resistance (R s ) of the varactor diode 2 are impedance-inverted by the action of the transmission line 4a, and the inductance (L v = − (Y t ) 2
/ Ω 2 C j ) and conductance (G v = R s Y t 2 ), while the open-ended line 20 has an equivalent inductance (L
r ) and capacitance (C r ) and conductance (G
Since it is represented by the parallel circuit of r ), the admittance Y s6 looking into the tuning circuit side from the source terminal of the field effect transistor 1 as shown in FIG. 23A is as follows. Y s6 = (Y t ) 2 · (R s + 1 / jωC j ) + (G r + jωC r + 1 / jωL r ) = (Y t ) 2 R s + G r + j {(ωC r −1 / ωL r ) − (Y t ) 2 / ωC j } Therefore, | ωC r −1 / ωL r | ≧ | (Y t ) 2 / ωC j
|, And the oscillation frequency band is almost determined by L r and C r , and the conductance component (Y t ) 2 R s + of Y s6
Since G r does not depend on C j , Q of the resonance circuit is constant, and the change in phase noise due to the oscillation frequency is small. If formed as shown in FIG. 24A, the varactor diode 2 is formed.
The junction capacitance change ratio n a (when C a is present) is as follows. n a = (C jmax + C a ) / (C jmin + C a ) = (n i · C jmin + C a ) / (C jmin + C a ) = {n i · (C jmin + C a ) − (n i −1) ) -C a} / (C jmin + C a) = n i - {(n i -1) · C a} / (C jmin + C a) <n i C a = ε 0 ε r S / d C here maximum and minimum values of jmax and C jmin is C j, (in the absence of C a) n i is the junction capacitance change ratio of the varactor diode 2, epsilon 0 and epsilon r is the dielectric constant of vacuum and the substrate 122, S is attached pattern The area of 127, d represents the thickness of the substrate 122. Thus C a is larger the n a is reduced, the band of the oscillation frequency can not be obtained a desired oscillation frequency band becomes narrower.

【0005】[0005]

【発明が解決しようとする課題】上記のような従来の電
圧制御発振器では、広帯域特性と雑音特性をトレードオ
フする方式を採るから、広帯域発振が容易なものは発振
周波数による位相雑音の変化が多く、発振周波数による
位相雑音の変化が少ないものは広帯域発振が困難であ
る。また同じ種類の基板上にバイアス回路を含め全回路
パターンを形成するから、基板上の取付パターンと地導
体間の浮遊容量が大きくなり、接合容量の変化比が低下
し所望の発振周波数帯域を得られない、実現できる所望
線路インピーダンス範囲の制約を受け設計自由度を制限
する、特にオクターブを越える帯域を必要とするマイク
ロ波用バイアス回路に適用するとき帯域両端で特性劣化
を生じるなどの問題点があった。
The conventional voltage controlled oscillator as described above adopts a method of trade-off between the wide band characteristic and the noise characteristic. Therefore, a wide band oscillator that is easy to oscillate has many phase noise changes due to the oscillation frequency. Broadband oscillation is difficult for those with little change in phase noise due to oscillation frequency. In addition, since the entire circuit pattern including the bias circuit is formed on the same type of board, the stray capacitance between the mounting pattern on the board and the ground conductor increases, and the change ratio of the junction capacitance decreases and the desired oscillation frequency band is obtained. However, there is a problem that the freedom of design is restricted by the range of desired line impedance that can be realized, especially when applied to a microwave bias circuit that requires a band exceeding an octave, characteristic deterioration occurs at both ends of the band. there were.

【0006】この発明が解決しようとする課題は、電圧
制御発振器で位相雑音の発振周波数による変化が少なく
かつ広帯域に同調でき、マイクロ波回路一般に適用する
集積バイアス回路で所望の小型化を実現する方式(小型
化広帯域発振方式)を提供することにある。
A problem to be solved by the present invention is to realize a desired miniaturization in an integrated bias circuit which is generally applied to a microwave circuit, because a voltage controlled oscillator has little change in phase noise due to an oscillation frequency and can be tuned in a wide band. (Miniaturized wideband oscillation system).

【0007】[0007]

【課題を解決するための手段】この発明の電圧制御発振
器は半導体発振素子と可変容量素子を備えるもので、ま
た集積バイアス回路はマイクロ波回路一般に適用するも
ので、上記課題を解決するためつぎの手段を設け、小型
化低雑音広帯域発振方式を採ることを特徴とする。
The voltage controlled oscillator of the present invention comprises a semiconductor oscillator and a variable capacitance element, and an integrated bias circuit is generally applied to microwave circuits. It is characterized in that a means is provided and a miniaturized low noise wideband oscillation system is adopted.

【0008】同調回路は、可変容量素子とインダクタン
スから成る直列共振回路と所望発振周波数でインピーダ
ンス反転をするインピーダンス変成器とから構成する。
または当該同調回路にさらに別途抵抗を直列に接続し形
成する。
The tuning circuit is composed of a series resonance circuit composed of a variable capacitance element and an inductance and an impedance transformer for performing impedance inversion at a desired oscillation frequency.
Alternatively, a resistor is additionally connected to the tuning circuit in series to form the tuning circuit.

【0009】インピーダンス変成器は、所望発振周波数
で概90度の電気長をもつ伝送線路で形成する。または
インダクタと並列キャパシタから成る集中定数回路もし
くは並列キャパシタに代えて可変容量素子を用い当該イ
ンピーダンス変成比を変える集中定数回路で形成する。
または1/4波長結合線路もしくは発振条件を容易に満
足する超伝導材料上の1/4波長結合線路で形成する。
または中心周波数の異なる複数のインピーダンス変成器
の両端に第1と第2の切替器を設け、所望発振周波数に
より当該インピーダンス変成器の1つを選択し形成す
る。
The impedance transformer is formed by a transmission line having an electrical length of about 90 degrees at a desired oscillation frequency. Alternatively, a lumped constant circuit including an inductor and a parallel capacitor or a lumped constant circuit that changes the impedance transformation ratio by using a variable capacitance element instead of the parallel capacitor is used.
Alternatively, it is formed of a quarter-wavelength coupled line or a quarter-wavelength coupled line on a superconducting material that easily satisfies the oscillation condition.
Alternatively, first and second switching devices are provided at both ends of a plurality of impedance transformers having different center frequencies, and one of the impedance transformers is selected and formed according to a desired oscillation frequency.

【0010】直列共振回路は、当該可変容量素子に対し
互いに半数ずつ異なる極性の向きに偶数個直列に接続し
形成する。または当該可変容量素子の等価直列抵抗より
十分大きな抵抗を並列に接続し形成する。
The series resonant circuit is formed by connecting an even number of series variable circuits in the directions of polarities different from each other by half. Alternatively, a resistance sufficiently larger than the equivalent series resistance of the variable capacitance element is connected in parallel and formed.

【0011】電圧制御発振器は、2つの相異なる発振素
子端子に対し第1と第2の同調回路を接続し形成する。
または第1と第2の各同調回路の当該インピーダンス変
成器に対し所望発振周波数で概45度ないし90度と概
90度ないし135度の電気長をもつ伝送線路で形成す
る。または第1と第2の各同調回路の当該直列共振回路
に対し異なる可変容量素子印加直流電圧で当該共振周波
数を違えて形成する。または帰還キャパシタに代えて発
振電力の一部を入力に帰還するもしくは別途発振電力の
出力を負荷に結合する可変容量素子を設け、発振周波数
に応じ当該容量を制御する。
The voltage controlled oscillator is formed by connecting first and second tuning circuits to two different oscillation element terminals.
Alternatively, the impedance transformer of each of the first and second tuning circuits is formed of a transmission line having an electrical length of approximately 45 to 90 degrees and approximately 90 to 135 degrees at a desired oscillation frequency. Alternatively, the resonant frequencies are formed differently by different DC voltages applied to the series resonant circuits of the first and second tuning circuits. Alternatively, instead of the feedback capacitor, a variable capacitance element for returning a part of the oscillation power to the input or separately coupling the output of the oscillation power to the load is provided, and the capacitance is controlled according to the oscillation frequency.

【0012】電圧制御発振器は集積回路形成時、発振素
子と可変容量素子に直流電圧を供給する高インピーダン
ス線路のバイアス回路等もしくは発振素子の整合回路等
を形成する第1の基板と低インピーダンスのインピーダ
ンス変成器を形成する第2の基板、または発振素子の整
合回路等を形成する第1の基板と可変容量素子の取付パ
ターン等を形成する第2の基板との誘電率もしくは基板
厚を違える。
The voltage controlled oscillator has a low impedance with a first substrate forming a bias circuit or the like of a high impedance line for supplying a DC voltage to the oscillation element and the variable capacitance element or a matching circuit of the oscillation element when forming an integrated circuit. The dielectric constant or the substrate thickness of the second substrate forming the transformer or the first substrate forming the matching circuit of the oscillating element and the second substrate forming the mounting pattern of the variable capacitance element are different.

【0013】集積バイアス回路は集積回路形成時、整合
回路等を形成する第1の基板とスパイラルインダクタそ
の他の高インピーダンス線路のバイアス回路等を形成す
る第2の基板との誘電率もしくは基板厚を違える。また
は当該誘電率もしくは基板厚の違う発振素子の整合回路
等を形成する第1の基板上にスパイラルインダクタその
他の高インピーダンス線路のバイアス回路等を形成する
第2の基板を実装する。またはベースプレート上に実装
する基板上に形成する発振素子の整合回路に対しもしく
は当該基板上に設ける貫通穴の上空を経由するようにベ
ースプレート上に実装する中継用キャパシタを介し、ワ
イアを空中に張り直接接続し給電するバイアス回路とし
てのインダクタを形成する。またはベースプレート上に
設ける段差の下段と上段に前記基板と中継用キャパシタ
を実装する。またはベースプレート上に実装する前記基
板上に設ける段差の下段と上段に発振素子の整合回路と
中継用パターンを形成し、当該整合回路に対し当該中継
用パターンを介し前記ワイアを空中に張る。または前記
整合回路を形成する同じ基板上に実装する前記中継用キ
ャパシタを介する。または基板上に形成するマイクロス
トリップ線路から垂直上方にワイアを空中に張り上方か
ら給電するバイアス回路としてのインダクタを形成す
る。
When forming an integrated circuit, the integrated bias circuit has a different dielectric constant or substrate thickness between the first substrate forming a matching circuit and the like and the second substrate forming a bias circuit of a high-impedance line such as a spiral inductor. . Alternatively, a second substrate on which a spiral inductor and other bias circuits for high impedance lines are formed is mounted on the first substrate on which a matching circuit for oscillating elements having different dielectric constants or substrate thicknesses is formed. Or, by attaching a wire in the air directly to the matching circuit of the oscillation element formed on the substrate mounted on the base plate or via a relay capacitor mounted on the base plate so as to pass through the through hole provided on the substrate. An inductor is formed as a bias circuit for connecting and supplying power. Alternatively, the substrate and the relay capacitor are mounted on the lower and upper steps of the step provided on the base plate. Alternatively, a matching circuit of the oscillating element and a relay pattern are formed on the lower and upper steps of the step provided on the substrate mounted on the base plate, and the wire is stretched in the air through the relay pattern to the matching circuit. Alternatively, via the relay capacitor mounted on the same substrate forming the matching circuit. Alternatively, a wire is formed vertically above the microstrip line formed on the substrate in the air to form an inductor as a bias circuit for feeding power from above.

【0014】[0014]

【作用】この発明の電圧制御発振器は上記手段で、所望
発振周波数で概90度の電気長をもつ伝送線路、集中定
数回路、1/4波長結合線路その他のインピーダンス変
成器と直列共振回路とから成る同調回路により等価並列
共振回路を形成し当該可変容量素子接合容量を変化する
ことにより広帯域に同調できるようにするとともに、当
該共振回路のQを一定にすることにより発振周波数によ
る位相雑音の変化を少なくする。また集積回路形成時の
回路パターン形成基板の誘電率または基板厚を違えるこ
とにより、または空中に張るワイアで所望のバイアス回
路を形成することにより対地容量を低減し広帯域特性を
改善するとともに、実装面積を小さくする。
The voltage controlled oscillator of the present invention comprises the transmission line having the electrical length of about 90 degrees at the desired oscillation frequency, the lumped constant circuit, the quarter wavelength coupling line and other impedance transformers and the series resonance circuit. An equivalent parallel resonance circuit is formed by the tuning circuit consisting of the variable capacitance element and the variable capacitance junction capacitance is changed to enable tuning in a wide band, and by keeping Q of the resonance circuit constant, a change in phase noise due to an oscillation frequency is suppressed. Reduce. Also, by changing the permittivity or substrate thickness of the circuit pattern forming substrate when forming an integrated circuit, or by forming a desired bias circuit with a wire that extends in the air, it is possible to reduce the capacitance to ground and improve the wideband characteristics, and to reduce the mounting area. To reduce.

【0015】[0015]

【実施例】この発明を示す一実施例の電圧制御発振器
(VCO)は図1(a)のように、同調回路は、バラク
タダイオード2と直列インダクタ3から成る直列共振回
路と所望発振周波数でインピーダンス反転機能をもつイ
ンピーダンス変成器4とから構成する。増幅回路は、電
界効果トランジスタ1と直列インダクタ5と負荷抵抗7
に出力する発振電力の一部を入力側に帰還するキャパシ
タ6とから構成する。キャパシタ8は、バラクタダイオ
ード2に対するバイアス電圧を阻止する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A voltage controlled oscillator (VCO) according to an embodiment of the present invention has a tuning circuit as shown in FIG. 1A, a tuning circuit, a series resonance circuit composed of a varactor diode 2 and a series inductor 3, and an impedance at a desired oscillation frequency. The impedance transformer 4 has an inverting function. The amplifier circuit includes a field effect transistor 1, a series inductor 5, and a load resistor 7.
And a capacitor 6 for returning a part of the oscillation power output to the input side to the input side. The capacitor 8 blocks the bias voltage for the varactor diode 2.

【0016】上記実施例のVCOは、発振周波数による
位相雑音が低く変化の少ないかつ広帯域に同調できる特
性を実現する方式(広帯域発振方式)を採る。
The VCO of the above embodiment adopts a system (broadband oscillation system) which realizes characteristics that the phase noise due to the oscillation frequency is low, changes little, and can be tuned in a wide band.

【0017】上記実施例は図1(a)のように、電界効
果トランジスタ1のソース端子から同調回路側を見込む
アドミタンスYs は、図1(b)のようにインピーダン
ス変成器4(インピーダンス変成比n)の作用でバラク
タダイオード2の接合容量(Cj )と等価直列抵抗(R
s )のインピーダンス反転インダクタンス(Cj /n
2 )とコンダクタンス(n2s )および直列インダク
タ(Ls )のインピーダンス反転キャパシタンス(n2
S )が並列に変換されるから、次のようになる。 Ys =n2 ・(Rs +1/jωCj +jωLs ) =n2s +jn2 (ωLs −1/ωCj ) 従って共振角周波数ωr =1/(Lsj1/2 とな
り、バラクタダイオード2の印加電圧を変えCj を変え
るとωr は広帯域に同調できるとともに、Ys のコンダ
クタンス成分n2s はCj に依らず共振回路のQが一
定となるから、発振周波数による位相雑音の変化は少な
い。
In the above embodiment, as shown in FIG. 1A, the admittance Y s looking into the tuning circuit side from the source terminal of the field effect transistor 1 is the impedance transformer 4 (impedance transformation ratio) as shown in FIG. 1B. n), the junction capacitance (C j ) of the varactor diode 2 and the equivalent series resistance (R
s ) impedance reversal inductance (C j / n
2 ) and conductance (n 2 R s ) and impedance reversal capacitance (n 2 R s ) of the series inductor (L s ).
Since L s ) is converted in parallel, Y s = n 2 · (R s + 1 / jωC j + jωL s ) = n 2 R s + jn 2 (ωL s −1 / ωC j ) Therefore, the resonance angular frequency ω r = 1 / (L s C j ) 1/2 Therefore, when the applied voltage of the varactor diode 2 is changed and C j is changed, ω r can be tuned in a wide band, and the conductance component n 2 R s of Y s becomes constant regardless of C j. Phase noise changes little with frequency.

【0018】なお図1(a)の上記実施例でインピーダ
ンス変成器4は図2(a)のように、所望発振周波数で
概90度の電気長をもつ特性アドミタンスYt の伝送線
路4aで形成してもよい。伝送線路4aと直列インダク
タ3は図2(b)のように、基板101上に形成するマ
イクロストリップ線路102とワイア103で実現す
る。上記実施例では図2(a)のように、電界効果トラ
ンジスタ1のソース端子から同調回路側を見込むアドミ
タンスYs1は、次のようになる。 Ys1=(Yt2 ・(Rs +1/jωCj +jωLs ) =(Yt2s +j(Yt2 (ωLS −1/ωCj ) 従って共振角周波数ωr =1/(Lsj1/2 とな
り、上記と同じにCj を変えるとωr は広帯域に同調で
きるとともに、Ys1のコンダクタンス成分(Yt2
s は発振周波数に依らず一定であり、発振周波数による
位相雑音の変化は少ない。
[0018] Note that as shown in FIG. 1 impedance transformer 4 in the above embodiment of (a) FIG. 2 (a), formed by the transmission lines 4a characteristics admittance Y t with an electrical length of approximate 90 degrees at the desired oscillation frequency You may. The transmission line 4a and the series inductor 3 are realized by the microstrip line 102 and the wire 103 formed on the substrate 101, as shown in FIG. In the above embodiment, as shown in FIG. 2A, the admittance Y s1 looking into the tuning circuit side from the source terminal of the field effect transistor 1 is as follows. Y s1 = (Y t) 2 · (R s + 1 / jωC j + jωL s) = (Y t) 2 R s + j (Y t) 2 (ωL S -1 / ωC j) Accordingly resonance angular frequency omega r = 1 / (L s C j ) 1/2 , and if C j is changed in the same manner as above, ω r can be tuned in a wide band and the conductance component (Y t ) 2 R of Y s1 can be obtained.
s is constant regardless of the oscillation frequency, and the change in phase noise due to the oscillation frequency is small.

【0019】また図1(a)の上記実施例でインピーダ
ンス変成器4は図3(a)のように、所望発振周波数で
インピーダンス反転機能をもつ特性インピーダンスZc
(インダクタンスLと並列キャパシタンスCのとき(L
/2C)1/2 )の伝送線路に等価な集中定数回路4bで
形成してもよい。回路をより小型化できる。集中定数回
路4bは図3(b)のように、ワイア103とチップコ
ンデンサ104で実現する。
Further, in the above embodiment of FIG. 1A, the impedance transformer 4 has a characteristic impedance Z c having an impedance inverting function at a desired oscillation frequency as shown in FIG. 3A.
(When inductance L and parallel capacitance C (L
It may be formed by the lumped constant circuit 4b equivalent to the / 2C) 1/2 ) transmission line. The circuit can be made smaller. The lumped constant circuit 4b is realized by the wire 103 and the chip capacitor 104 as shown in FIG.

【0020】また図3(a)の上記実施例で集中定数回
路4bは図4のように、バラクタダイオードなどの可変
容量素子で可変キャパシタンスCv を形成する集中定数
回路4cとし、外部制御電圧でCv を変え当該インピー
ダンス変成比nを変えるようにしてもよい。同調回路側
と電界効果トランジスタ1間の結合度を変えられるか
ら、発振周波数による位相雑音の変化が少ない広帯域発
振ができる。
In the above embodiment of FIG. 3A, the lumped constant circuit 4b is a lumped constant circuit 4c which forms a variable capacitance C v with a variable capacitance element such as a varactor diode as shown in FIG. C v may be changed and the impedance transformation ratio n may be changed. Since the degree of coupling between the tuning circuit side and the field effect transistor 1 can be changed, wideband oscillation with little change in phase noise due to the oscillation frequency can be performed.

【0021】また図1(a)の上記実施例でインピーダ
ンス変成器4は図5のように、1/4波長結合線路4d
で形成してもよい。マイクロ波帯で広帯域性をもつとと
もに阻止キャパシタ8を設ける必要がないから、部品点
数を低減できる。
In the above embodiment of FIG. 1A, the impedance transformer 4 has a quarter wavelength coupling line 4d as shown in FIG.
You may form with. Since it has a wide band property in the microwave band and it is not necessary to provide the blocking capacitor 8, the number of parts can be reduced.

【0022】また図5の上記実施例で1/4波長結合線
路4dは、電界効果トランジスタ1と1/4波長結合線
路4d間に仮定する節点から同調回路側と増幅回路側を
見込む反射係数Γt とΓa に対し、発振条件(|Γt
Γa |≧1、∠(Γt ・Γa)=2nπ、n=0、±
1、±2、…)を容易に満足する超伝導材料で実現して
もよい。多重反射による損失を低減し安定な発振ができ
る。
Further, in the above embodiment of FIG. 5, the 1/4 wavelength coupling line 4d has a reflection coefficient Γ that allows the tuning circuit side and the amplification circuit side to be seen from the assumed node between the field effect transistor 1 and the 1/4 wavelength coupling line 4d. For t and Γ a , the oscillation condition (| Γ t ·
Γ a | ≧ 1, ∠ (Γ t · Γ a ) = 2nπ, n = 0, ±
1, ± 2, ...) may be easily realized with a superconducting material. Loss due to multiple reflection can be reduced and stable oscillation can be achieved.

【0023】また図1(a)の上記実施例で直列共振回
路は図6(a)のように、互いに極性を逆にし直列接続
をするバラクタダイオード2−1と2−2および直列イ
ンダクタ3−1と3−2と3−3を組み合わせ構成して
もよい。バラクタダイオード2−1と2−2を共振素子
として使用するとき、当該ベースバンド雑音が当該非線
形性でアップコンバージョンされ生じる位相雑音を大き
く低減できる。バラクタダイオード2−1と2−2は図
6(b)のように、基板101上に形成するパターン1
06に取り付け、制御電圧供給線107に接続する。図
6(c)のように、発振波による当該接合容量の時間的
変化を互いに逆とし相殺する。
In the above embodiment of FIG. 1A, the series resonance circuit has varactor diodes 2-1 and 2-2 and series inductor 3-in which the polarities are opposite to each other and are connected in series as shown in FIG. 6A. You may comprise 1 and 3-2 and 3-3 in combination. When the varactor diodes 2-1 and 2-2 are used as resonant elements, the phase noise generated by up-conversion of the baseband noise due to the nonlinearity can be greatly reduced. The varactor diodes 2-1 and 2-2 have a pattern 1 formed on the substrate 101 as shown in FIG.
It is attached to 06 and is connected to the control voltage supply line 107. As shown in FIG. 6C, the temporal changes in the junction capacitance due to the oscillating waves are made opposite to each other to cancel.

【0024】また図1(a)の上記実施例で直列共振回
路は図7(a)のように、抵抗器9(バラクタダイオー
ド2の等価直列抵抗Rs より十分大きな抵抗R1 をも
つ)を並列に挿入してもよい。また同調回路は図8
(a)のように、抵抗器10を直列に挿入してもよい。
不要発振等を起こりにくくできる。上記実施例は図7
(a)と図8(a)のように所望周波数発振時、バラク
タダイオード2と直列インダクタ3は直列共振状態に近
いから、直列共振回路を見込むインピーダンスZ1 はバ
ラクタダイオード2の等価直列抵抗Rs (1〜2Ω)を
介し短絡状態になり、Z1 ≒Rs になる。図7(a)で
並列抵抗器19を含み直列共振回路を見込むインピーダ
ンスZ1 ´は、Z1 ´=Z1 ・R1 /(Z1 +R1 )≒
S ・R1 /(Rs +R1 )=Rs /{1+(RS /R
1 )}≒Rs (∵Z1 ≒RS 、R1 ≫Rs )になり、並
列抵抗器9の付加によるインピーダンス変化は無視で
き、所望発振周波数で直列共振回路のQは低下しない。
一方図7(b)のようにインピーダンスZ1 とZ1 ´を
スミスチャート表示すると、Z1 とZ1 ´の周波数に対
する軌跡を示す実線と破線が実軸に交差する点が直列共
振周波数になり、所望発振周波数以外ではZ1 のリアク
タンス分がある程度大きな値になりZ1 ≒Rs が成立し
ないから、回路損失の増加状態になり不要発振等が起こ
りにくくなる。また図8(a)で直列抵抗器10を含み
同調回路を見込むインピーダンスZ2 ´は、インピーダ
ンス変成器4の特性インピーダンスをZ0 (数+Ω)、
インピーダンス変成器4と直列共振回路を見込むインピ
ーダンスをZ2とすればZ2 ´=Z2 +R2 ≒Z0 2/Z1
+R2 ≒Z0 2/Rs +R2 ≒Z0 2/Rs (∵Z1 ≒Rs
、Z0 2/Rs ≫R2 )になり直列抵抗器10の付加に
よるインピーダンスの変化は無視でき、所望発振周波数
で同調回路のQは低下しない。一方図8(b)のように
インピーダンスZ2 とZ2 ´をスミスチャート表示する
と、Z2 とZ2 ´の周波数に対する軌跡を示す実線と破
線が実軸に交差する点が等価的に並列共振周波数にな
り、所望発振周波数以外ではZ1 のリアクタンス分があ
る程度大きな値になりZ1 ≒Rs が成立しないから、R
2 を付加する影響が現われ(Z0 2/Rs のRs が大きな
値となり)、回路損失の増加状態になり不要発振等が起
こりにくくなる。
Further, in the above embodiment of FIG. 1A, the series resonance circuit includes a resistor 9 (having a resistance R 1 sufficiently larger than the equivalent series resistance R s of the varactor diode 2) as shown in FIG. 7A. You may insert in parallel. The tuning circuit is shown in Fig. 8.
The resistor 10 may be inserted in series as in (a).
Unnecessary oscillations can be made less likely to occur. The above embodiment is shown in FIG.
As shown in FIGS. 8A and 8A, when the desired frequency is oscillated, the varactor diode 2 and the series inductor 3 are close to the series resonance state. Therefore, the impedance Z 1 for the series resonance circuit is equivalent to the equivalent series resistance R s of the varactor diode 2. A short circuit occurs via (1 to 2 Ω) and Z 1 ≈R s . In FIG. 7A, the impedance Z 1 ′ including the parallel resistor 19 and looking into the series resonance circuit is Z 1 ′ = Z 1 · R 1 / (Z 1 + R 1 ) ≈
R S · R 1 / (R s + R 1 ) = R s / {1+ (R s / R
1 )} ≈R s (∵Z 1 ≈R S , R 1 >> R s ), the impedance change due to the addition of the parallel resistor 9 can be ignored, and the Q of the series resonance circuit does not decrease at the desired oscillation frequency.
On the other hand, when the impedances Z 1 and Z 1 ′ are displayed on the Smith chart as shown in FIG. 7B, the series resonance frequency is the point where the solid line and the broken line showing the locus with respect to the frequencies of Z 1 and Z 1 ′ intersect the real axis. In addition to the desired oscillation frequency, the reactance component of Z 1 becomes a large value to some extent and Z 1 ≈R s does not hold, so that the circuit loss increases and unnecessary oscillation or the like hardly occurs. Further, in FIG. 8A, the impedance Z 2 ′ including the series resistor 10 and looking into the tuning circuit is the characteristic impedance of the impedance transformer 4 as Z 0 (number + Ω),
If the impedance considering the impedance transformer 4 and the series resonance circuit is Z 2 , then Z 2 ′ = Z 2 + R 2 ≈Z 0 2 / Z 1
+ R 2 ≈ Z 0 2 / R s + R 2 ≈Z 0 2 / R s (∵Z 1 ≈R s
, Z 0 2 / R s >> R 2 ) and the change in impedance due to the addition of the series resistor 10 can be ignored, and the Q of the tuning circuit does not decrease at the desired oscillation frequency. On the other hand, when the impedances Z 2 and Z 2 ′ are displayed on the Smith chart as shown in FIG. 8B, the points where the solid line and the broken line showing the loci with respect to the frequencies of Z 2 and Z 2 ′ intersect the real axis are equivalent to parallel resonance. Frequency, and the reactance of Z 1 becomes a large value to some extent other than the desired oscillation frequency, and Z 1 ≈R s does not hold.
The effect of adding 2 appears (R s of Z 0 2 / R s has a large value), the circuit loss increases, and unnecessary oscillation is less likely to occur.

【0025】また図2(a)の上記実施例でインピーダ
ンス変成器4は図9のように、当該制御電圧を阻止する
キャパシタ8と11を介しダイオードスイッチ12で切
り換え、所望発振周波数で90度に近い電気長をもつ方
を選択する2個の中心周波数の異なるインピーダンス変
成器4d−1と4d−2としてもよい。インピーダンス
反転帯域を拡大するから、インピーダンス変成器4自身
の周波数特性によるインピーダンス反転帯域の制限によ
る帯域両端における共振回路のQの変化を小さくでき、
より広帯域な発振器を実現できる。
In the above embodiment of FIG. 2A, the impedance transformer 4 is switched by the diode switch 12 via the capacitors 8 and 11 for blocking the control voltage as shown in FIG. Two impedance transformers 4d-1 and 4d-2 having different center frequencies may be selected so as to select ones having a closer electrical length. Since the impedance inversion band is expanded, the change in Q of the resonant circuit at both ends of the band due to the limitation of the impedance inversion band due to the frequency characteristic of the impedance transformer 4 itself can be reduced,
A wider band oscillator can be realized.

【0026】また図2(a)の上記実施例で図10
(a)のように、電界効果トランジスタ1のソースとゲ
ート端子に対し、バラクタダイオード2aと2b、直列
インダクタ3aと3bおよび特性アドミタンスYt1とY
t2の伝送線路4a−1と4a−2から構成する同調回路
を接続してもよい。発振条件を満たす周波数帯域を広
げ、より広帯域な発振器を実現できる。上記実施例では
図10(a)のように、電界効果トランジスタ1のソー
スとベース端子から同調回路側を見込むアドミタンスY
s2とYg は、次のようになる。 Ys2=(Yt12 ・(Rs +1/jωCj +jωLs ) =(Yt12s +j(Yt12 (ωLS −1/ωCj ) Yg =(Yt22 ・(Rs +1/jωCj +jωLs ) =(Yt22s +j(Yt12 (ωLS −1/ωCj ) 従って共振角周波数ωr =1/(Lsj1/2 とな
り、直列インダクタ3aと3bの値を変えると、あるい
はバラクタダイオード2−1と2−2の印加電圧を変え
j1とCj2を変えるとωr は広帯域に同調でき、Ys2
g の一方が容量性、他方が誘導性になる範囲で発振周
波数を変えられる。図10(b)のようにたとえばLs1
≠Ls2のとき、2つの同調回路の各共振角周波数ωr
(Ys2とYg の虚数部Im (Ys2)とIm (Yg )が0
になる角周波数)は、常にある間隔(たとえばYs2が誘
導性でYg が容量性になる周波数範囲)を置いて同調電
圧に応じ変わる。またYs2とYg のコンダクタンス成分
(Yt12s と(Yt22sは発振周波数に依らず
一定であり、発振周波数による位相雑音の変化は少な
い。Ys2とYg の差を形成するには、パラメータのいず
れかを互いに他方と違うもの、たとえばLs1≠Ls2、C
j1≠Cj2などとすればよい。
Further, in the above embodiment of FIG.
(A), in respect to the source and the gate terminal of the field effect transistor 1, varactor diodes 2a and 2b, a series inductor 3a and 3b and characteristic admittance Y t1 and Y
A tuning circuit composed of t2 transmission lines 4a-1 and 4a-2 may be connected. A frequency band satisfying the oscillation condition can be widened to realize a wider-band oscillator. In the above-described embodiment, as shown in FIG. 10A, the admittance Y in which the tuning circuit side is seen from the source and base terminals of the field effect transistor 1.
s2 and Y g are as follows. Y s2 = (Y t1 ) 2 · (R s + 1 / jωC j + jωL s ) = (Y t1 ) 2 R s + j (Y t1 ) 2 (ωL S −1 / ωC j ) Y g = (Y t2 ) 2 · (R s + 1 / jωC j + jωL s) = (Y t2) 2 R s + j (Y t1) 2 (ωL S -1 / ωC j) Accordingly resonance angular frequency ω r = 1 / (L s C j) 1 Becomes / 2 , and if the values of the series inductors 3a and 3b are changed, or if the applied voltages of the varactor diodes 2-1 and 2-2 are changed and C j1 and C j2 are changed, ω r can be tuned in a wide band, and Y s2 and Y The oscillation frequency can be changed within the range in which one of g is capacitive and the other is inductive. As shown in FIG. 10B, for example, L s1
When ≠ L s2 , each resonance angular frequency ω r of the two tuning circuits
(Y s2 and Y g of the imaginary part I m (Y s2) and I m (Y g) is 0
The angular frequency at which is always dependent on the tuning voltage at certain intervals (for example, the frequency range in which Y s2 is inductive and Y g is capacitive). Further, the conductance components (Y t1 ) 2 R s and (Y t2 ) 2 R s of Y s2 and Y g are constant regardless of the oscillation frequency, and the change in phase noise due to the oscillation frequency is small. To form the difference between Y s2 and Y g , one of the parameters differs from the other, eg L s1 ≠ L s2 , C
It suffices if j1 ≠ C j2 or the like.

【0027】また図10(a)の上記実施例で伝送線路
4a−1と4a−2は図11のように、所望発振周波数
でθ1 とθ2 (θ1 ≠θ2 )の電気長をもつ特性アドミ
タンスYt1とYt2の伝送線路4a−3と4a−4を用い
てもよい。バラクタダイオード2aと2bおよび直列イ
ンダクタ3aと3bが同じでも伝送線路4a−3と4a
−4を介し見込むアドミタンスYs3とYg1を違えられる
から、構成上の利点が大きい。
In the above embodiment of FIG. 10A, the transmission lines 4a-1 and 4a-2 have electrical lengths θ 1 and θ 21 ≠ θ 2 ) at the desired oscillation frequency as shown in FIG. the transmission line 4a-3 and 4a-4 characteristic admittance Y t1 and Y t2 with may be used. Even if the varactor diodes 2a and 2b and the series inductors 3a and 3b are the same, the transmission lines 4a-3 and 4a
Since the admittances Y s3 and Y g1 that can be expected via -4 can be made different, the advantage in the configuration is great.

【0028】また図10(a)の上記実施例で電界効果
トランジスタ1のソースとゲート端子に接続する各同調
回路は図12のように、バラクタダイオード2aと2b
および直列インダクタ3aと3b間に直流阻止キャパシ
タ13aと13bを挿入し、端子15から供給する制御
電圧に対し高周波阻止インダクタ14aと14bを介
し、一方は加算器17で電圧源16からの固定オフセッ
ト電圧を加え、他方はそのままバラクタダイオード2a
と2bに印加してもよい。同一制御電圧でバラクタダイ
オード2aと2bの接合容量Cj1とCj2に差をもたせ、
互いに他方と違うアドミタンスYs4とYg2が得られるか
ら、当該各同調回路は同じ構造でよく、構成上の利点が
大きい。
In the above embodiment of FIG. 10A, the tuning circuits connected to the source and gate terminals of the field effect transistor 1 have varactor diodes 2a and 2b as shown in FIG.
And DC blocking capacitors 13a and 13b are inserted between the series inductors 3a and 3b, and a high-frequency blocking inductors 14a and 14b are provided for the control voltage supplied from the terminal 15. One is an adder 17 and a fixed offset voltage from the voltage source 16. And the other is the same as the varactor diode 2a.
And 2b may be applied. With the same control voltage, the junction capacitances C j1 and C j2 of the varactor diodes 2a and 2b are made different from each other,
Since the admittances Y s4 and Y g2 different from each other are obtained, the tuning circuits may have the same structure, which is a great structural advantage.

【0029】また図1(a)の上記実施例で帰還キャパ
シタ6は図13のように、バラクタダイオード18に代
えて負荷抵抗7に出力する発振電力の一部を入力側に帰
還してもよい。また当該発振電力は図14のように、バ
ラクタダイオード19による結合回路で負荷抵抗7に出
力してもよい。発振周波数が低域ならば大きく、高域な
らば小さくなるようにバラクタダイオード18と19の
接合容量を変化するから、発振周波数に対する入力帰還
量の周波数特性を補正でき、発振周波数に依らず一定の
入力帰還量を保ち発振器を安定に動作できる。また発振
周波数による負荷への結合量の周波数特性を補正でき、
発振器の出力レベルを発振周波数によらず一定に保て
る。
Further, in the above embodiment of FIG. 1A, the feedback capacitor 6 may return a part of the oscillation power output to the load resistor 7 to the input side instead of the varactor diode 18, as shown in FIG. . Alternatively, the oscillated power may be output to the load resistor 7 by a coupling circuit including a varactor diode 19, as shown in FIG. Since the junction capacitance of the varactor diodes 18 and 19 is changed so as to be large when the oscillation frequency is low and small when the oscillation frequency is high, the frequency characteristic of the input feedback amount with respect to the oscillation frequency can be corrected and is constant regardless of the oscillation frequency. The amount of input feedback is maintained and the oscillator can operate stably. Also, the frequency characteristic of the amount of coupling to the load due to the oscillation frequency can be corrected,
The output level of the oscillator can be kept constant regardless of the oscillation frequency.

【0030】また上記実施例の電圧制御発振器で図15
のように、発振素子の整合回路109や電界効果トラン
ジスタ1とバラクタダイオード2とに対し直流電圧を供
給するバイアス回路110を高インピーダンス線路で形
成する第1の基板108より薄い厚さか、大きい誘電率
の第2の基板111上に低インピーダンスのマイクロス
トリップ線路として所望発振周波数で概90度の電気長
をもつインピーダンス変成器4を形成してもよい。バラ
クタダイオード2を電界効果トランジスタ1に密結合し
発振器を広帯域化できるとともに小型で変成化の大きい
インピーダンス変成器として形成できるから、広帯域か
つ小型の発振器を実現できる。
In the voltage controlled oscillator of the above embodiment, FIG.
As described above, the matching circuit 109 of the oscillating element or the bias circuit 110 for supplying the DC voltage to the field effect transistor 1 and the varactor diode 2 is thinner than the first substrate 108 formed of a high impedance line, or has a larger dielectric constant. The impedance transformer 4 having a low impedance microstrip line and an electrical length of about 90 degrees at the desired oscillation frequency may be formed on the second substrate 111. Since the varactor diode 2 is tightly coupled to the field effect transistor 1 so that the oscillator can have a wide band and can be formed as a small impedance transformer having a large transformation, a wide band and compact oscillator can be realized.

【0031】また上記実施例に限らない電圧制御発振器
で図16のように、発振素子の整合回路109等を形成
する第1の基板108より厚い厚さか小さい誘電率の第
2の基板113上にバラクタダイオード2の取付パター
ン114を形成してもよい。取付パターン114と地導
体間の浮遊容量Ca を低減するから、Ca による発振周
波数帯域の減少度合いが少ない発振器を実現できる。 Ca =ε0 εr S/d ここにε0 とεr は真空と基板113の誘電率、Sは取
付パターンの面積、dは基板113の厚さを表す。
Further, in the voltage controlled oscillator which is not limited to the above-mentioned embodiment, as shown in FIG. 16, it is formed on the second substrate 113 which is thicker or smaller in dielectric constant than the first substrate 108 which forms the matching circuit 109 of the oscillating element. The mounting pattern 114 of the varactor diode 2 may be formed. Since the stray capacitance C a between the mounting pattern 114 and the ground conductor is reduced, it is possible to realize an oscillator in which the degree of decrease in the oscillation frequency band due to C a is small. C a = ε 0 ε r S / d where ε 0 and ε r are vacuum and the dielectric constant of the substrate 113, S is the area of the mounting pattern, and d is the thickness of the substrate 113.

【0032】また上記実施例に限らないマイクロ波回路
一般に適用する集積バイアス回路で図17のように、発
振素子の整合回路109等を形成する第1の基板108
より厚い厚さか小さい誘電率の第2の基板113上にバ
イアス回路110の高インピーダンス線路をスパイラル
インダクタ115で形成してもよい。浮遊容量を低減す
るから、広帯域性を改善できる。
Further, as shown in FIG. 17, a first substrate 108 for forming a matching circuit 109 for an oscillating element is an integrated bias circuit generally applied to a microwave circuit not limited to the above embodiment.
The high impedance line of the bias circuit 110 may be formed by the spiral inductor 115 on the second substrate 113 having a larger thickness or a smaller dielectric constant. Since the stray capacitance is reduced, the broadband property can be improved.

【0033】また上記実施例で図18のように、発振素
子の整合回路109等を形成する親基板108上に実装
する子基板113(親基板108より厚さが厚いか誘電
率が小さい必要は必ずしもない)上にバイアス回路11
0を形成してもよい。また図19(a)のようにベース
プレート117上に実装する基板108上に形成する発
振素子の整合回路109に対しベースプレート117上
に実装する中継用キャパシタ119を介し空中に張るワ
イア118で直接接続し給電するバイアス回路110と
してのインダクタとしてもよい。また図19(b)のよ
うにベースプレート117上に実装する基板108上に
設けるキリ穴120上方を経由しワイア118を空中に
張ってもよい。図19(a)と図19(b)の場合の実
装断面を示す図20(a)に対し、図20(b)のよう
にベースプレート117上に設ける段差の下段と上段に
基板108と中断用キャパシタ119を実装してもよ
い。また図20(c)のようにベースプレート117上
に実装する基板108上に設ける段差の下段と上段に発
振素子の整合回路109と中継用パターン121を形成
し、当該整合回路109に対し当該中継用パターン12
1を介し当該ワイア118を空中に張ってもよい。また
図20(d)のようにベースプレート117上に実装す
る基板108上に形成する発振素子の整合回路109に
対し同じ基板108上に実装する中継用キャパシタ11
9を介しワイア118を空中に張ってもよい。いずれも
対地容量を低減し広帯域性を改善できるとともにより実
装面積を小さくできる。
In the above-described embodiment, as shown in FIG. 18, the sub-board 113 mounted on the main board 108 for forming the matching circuit 109 of the oscillating element, etc. (need to have a larger thickness or a smaller dielectric constant than the main board 108) Bias circuit 11 on top
0 may be formed. Further, as shown in FIG. 19A, the matching circuit 109 of the oscillation element formed on the substrate 108 mounted on the base plate 117 is directly connected to the matching circuit 109 of the oscillation element via the relay capacitor 119 mounted on the base plate 117 by a wire 118 extending in the air. An inductor may be used as the bias circuit 110 that supplies power. Further, as shown in FIG. 19B, the wire 118 may be stretched in the air via the upper side of the drill hole 120 provided on the substrate 108 mounted on the base plate 117. In contrast to FIG. 20A showing the mounting cross section in the case of FIGS. 19A and 19B, the board 108 and the interruption are provided on the lower and upper steps of the step provided on the base plate 117 as shown in FIG. 20B. The capacitor 119 may be mounted. Further, as shown in FIG. 20C, the matching circuit 109 of the oscillating element and the relay pattern 121 are formed in the lower and upper steps of the step provided on the substrate 108 mounted on the base plate 117, and the matching circuit 109 is used for the relay. Pattern 12
The wire 118 may be stretched in the air through 1. Further, as shown in FIG. 20D, the relay capacitor 11 mounted on the same substrate 108 as the matching circuit 109 of the oscillation element formed on the substrate 108 mounted on the base plate 117.
The wire 118 may be stretched in the air through the cable 9. In either case, the capacitance to ground can be reduced, the wide band performance can be improved, and the mounting area can be further reduced.

【0034】また上記実施例に限らないマイクロ波一般
に適用する集積バイアス回路で図21(a)のように、
基板108上に形成するマイクロストリップ線路109
−1から垂直上方の空中に張るワイア118で上方から
給電するバイアス回路110としてのインダクタとして
もよい。ワイア118の方向およびマイクロストリップ
線路109−1上の高周波電流Jと磁界Hの方向が直交
するから、高周波磁界Hで誘導するワイア118上の高
周波電流J´を極小にできる。さらにワイア118をマ
イクロストリップ線路109−1の幅方向中央で接続す
れば図21(b)のように、高周波電流密度が最小にで
きるから、ワイア118への高周波電流の漏れ込みを最
小にできる。
In addition, as shown in FIG. 21 (a), an integrated bias circuit generally applied to microwaves not limited to the above embodiment,
Microstrip line 109 formed on substrate 108
An inductor may be used as a bias circuit 110 that feeds power from above by a wire 118 extending vertically from -1 in the air. Since the direction of the wire 118 and the direction of the high frequency current J on the microstrip line 109-1 and the magnetic field H are orthogonal to each other, the high frequency current J ′ on the wire 118 induced by the high frequency magnetic field H can be minimized. Further, if the wire 118 is connected at the center of the width direction of the microstrip line 109-1, the high frequency current density can be minimized as shown in FIG. 21B, so that the leakage of the high frequency current into the wire 118 can be minimized.

【0035】また上記実施例で発振素子は電界効果トラ
ンジスタを適用する場合を説明したが、バイポーラトラ
ンジスタその他ガンダイオードやインパットダイオード
などの負性抵抗をもつダイオードでもよいのはいうまで
もない。
Further, although the case where the field effect transistor is applied to the oscillating element has been described in the above embodiment, it goes without saying that it may be a bipolar transistor or a diode having a negative resistance such as a Gunn diode or an impatt diode.

【0036】[0036]

【発明の効果】上記のようにこの発明の電圧制御発振器
では、位相雑音の発振周波数による変化が少なくかつ広
帯域で同調できる方式を採り、またマイクロ波回路一般
に適用する集積バイアス回路では所望の小型化を実現す
る方式を採るから、従来のように広帯域発振の難易と発
振周波数による位相雑音変化の多少とが二律反背の関係
になり広帯域特性と雑音特性をトレードオフしかつ実現
の制約を受ける方式に比べ、安定で広帯域性に優れかつ
小型の電圧制御発振器と集積バイアス回路を実現できる
効果がある。
As described above, the voltage controlled oscillator according to the present invention adopts a system in which the phase noise is little changed by the oscillation frequency and can be tuned in a wide band, and the integrated bias circuit generally applied to microwave circuits can be miniaturized to a desired size. , The difficulty of wideband oscillation and the amount of change in phase noise due to the oscillation frequency are in a tradeoff relationship as in the past, and there is a trade-off between wideband characteristics and noise characteristics and there is a restriction on realization. Compared with the method, it has an effect of realizing a stable and excellent wide band and small-sized voltage controlled oscillator and integrated bias circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明を示す一実施例の電圧制御発振器の
構成図と当該同調回路側を見込むアドミタンスの等価回
路図。
FIG. 1 is a configuration diagram of a voltage-controlled oscillator according to an embodiment of the present invention and an equivalent admittance circuit diagram in which the tuning circuit side is considered.

【図2】 この発明を示す他の一実施例の構成図と実装
図。
FIG. 2 is a configuration diagram and an implementation diagram of another embodiment showing the present invention.

【図3】 この発明を示す他の一実施例の構成図と実装
図。
FIG. 3 is a configuration diagram and an implementation diagram of another embodiment showing the present invention.

【図4】 この発明を示す他の一実施例の構成図。FIG. 4 is a configuration diagram of another embodiment showing the present invention.

【図5】 この発明を示す他の一実施例の構成図。FIG. 5 is a configuration diagram of another embodiment showing the present invention.

【図6】 この発明を示す他の一実施例の構成図と実装
図と接合容量の時間に対する変化を説明する図。
FIG. 6 is a configuration diagram of another embodiment showing the present invention, a mounting diagram, and a diagram for explaining changes in junction capacitance with time.

【図7】 この発明を示す他の一実施例の構成図と当該
直列共振回路側を見込むインピーダンスのスミスチャー
ト。
FIG. 7 is a configuration diagram of another embodiment showing the present invention and a Smith chart of impedance looking into the series resonance circuit side.

【図8】 この発明を示す他の一実施例の構成図と当該
同調回路側を見込むインピーダンスのスミスチャート。
FIG. 8 is a configuration diagram of another embodiment showing the present invention and a Smith chart of impedance looking into the tuning circuit side.

【図9】 この発明を示す他の一実施例の構成図。FIG. 9 is a block diagram of another embodiment showing the present invention.

【図10】 この発明を示す他の一実施例の構成図と共
振角周波数の同調電圧に対する変化を説明する図。
FIG. 10 is a configuration diagram of another embodiment showing the present invention and a diagram for explaining changes in resonance angular frequency with respect to a tuning voltage.

【図11】 この発明を示す他の一実施例の構成図。FIG. 11 is a configuration diagram of another embodiment showing the present invention.

【図12】 この発明を示す他の一実施例の構成図。FIG. 12 is a configuration diagram of another embodiment showing the present invention.

【図13】 この発明を示す他の一実施例の構成図。FIG. 13 is a configuration diagram of another embodiment showing the present invention.

【図14】 この発明を示す他の一実施例の構成図。FIG. 14 is a configuration diagram of another embodiment showing the present invention.

【図15】 この発明を示す他の一実施例の実装図。FIG. 15 is a mounting view of another embodiment showing the present invention.

【図16】 この発明を示す他の一実施例の実装図。FIG. 16 is a mounting view of another embodiment showing the present invention.

【図17】 この発明を示す他の一実施例の実装図。FIG. 17 is a mounting view of another embodiment showing the present invention.

【図18】 この発明を示す他の一実施例の実装図。FIG. 18 is a mounting view of another embodiment showing the present invention.

【図19】 この発明を示す他の一実施例の実装図。FIG. 19 is a mounting view of another embodiment of the present invention.

【図20】 この発明を示す他の一実施例の実装断面
図。
FIG. 20 is a mounting cross-sectional view of another embodiment showing the present invention.

【図21】 この発明を示す他の一実施例の実装図と高
周波電流密度の線路幅方向変化を説明する図。
FIG. 21 is a mounting diagram of another embodiment showing the present invention and a diagram for explaining changes in high-frequency current density in the line width direction.

【図22】 従来例の電圧制御発振器の構成図と位相雑
音の周波数特性を説明する図。
FIG. 22 is a diagram illustrating a configuration of a conventional voltage controlled oscillator and a diagram illustrating frequency characteristics of phase noise.

【図23】 他の従来例の構成図と当該同調回路側を見
込むアドミタンスの等価回路。
FIG. 23 is a block diagram of another conventional example and an admittance equivalent circuit that looks into the tuning circuit side.

【図24】 他の従来例の実装図と浮遊容量を説明する
図。
FIG. 24 is a mounting diagram of another conventional example and a diagram illustrating stray capacitance.

【符号の説明】[Explanation of symbols]

1 電界効果トランジスタ、2、2−1、2−2、2
a、2b バラクタダイオード、3、3−1、3−2、
3−3、3a、3b 直列インダクタ、4 インピーダ
ンス変成器、4a、4a−1、4a−2 伝送線路、4
b、4c 集中定数回路、4d、4d−1、4d−2
1/4波長結合線路、5 直列インダクタ、6 帰還キ
ャパシタ、7 負荷抵抗、8 直流阻止キャパシタ、9
並列抵抗器、10 直列抵抗器、11 直流阻止キャ
パシタ、12 ダイオードスイッチ、13a、13b
直流阻止キャパシタ、14a、14b 高周波阻止イン
ダクタ、15 制御電圧供給端子、16 オフセット電
圧源、17 加算器、18バラクタダイオード、19
バラクタダイオード、101 基板、102 マイクロ
ストリップ線路、103 ワイア、104 チップコン
デンサ、105 基板、106 取付パターン、107
制御電圧供給線、108 第1の基板、109 整合
回路、109−1 マイクロストリップ線路、110
バイアス回路、111 第2の基板、112 ワイア、
113 第2の基板、114 取付パターン、115
スパイラルインダクタ、116 ワイア、117 ベー
スプレート、118 ワイア、119 中継用キャパシ
タ、120 キリ穴、121中継用パターン。なお図
中、同一符号は同一または相当部分を示す。
1 field effect transistor, 2, 2-1, 2-2, 2
a, 2b Varactor diodes 3, 3, 3-1, 3-2,
3-3, 3a, 3b Series inductor, 4 Impedance transformer, 4a, 4a-1, 4a-2 Transmission line, 4
b, 4c lumped constant circuit, 4d, 4d-1, 4d-2
1/4 wavelength coupled line, 5 series inductor, 6 feedback capacitor, 7 load resistor, 8 DC blocking capacitor, 9
Parallel resistor, 10 series resistor, 11 DC blocking capacitor, 12 Diode switch, 13a, 13b
DC blocking capacitor, 14a, 14b High frequency blocking inductor, 15 Control voltage supply terminal, 16 Offset voltage source, 17 Adder, 18 Varactor diode, 19
Varactor diode, 101 substrate, 102 microstrip line, 103 wire, 104 chip capacitor, 105 substrate, 106 mounting pattern, 107
Control voltage supply line, 108 first substrate, 109 matching circuit, 109-1 microstrip line, 110
Bias circuit, 111 second substrate, 112 wire,
113 second substrate, 114 mounting pattern, 115
Spiral inductor, 116 wires, 117 base plate, 118 wires, 119 relay capacitor, 120 drill holes, 121 relay pattern. In the drawings, the same reference numerals indicate the same or corresponding parts.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 飯田 明夫 鎌倉市大船五丁目1番1号 三菱電機株式 会社電子システム研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akio Iida 5-1-1, Ofuna, Kamakura-shi Electronic Systems Research Center, Mitsubishi Electric Corporation

Claims (25)

【特許請求の範囲】[Claims] 【請求項1】 半導体発振素子と可変容量素子を備える
電圧制御発振器において、前記可変容量素子とインダク
タから成る直列共振回路と所望発振周波数でインピーダ
ンス反転をするインピーダンス変成器とから構成する同
調回路を設けることを特徴とする電圧制御発振器。
1. A voltage controlled oscillator including a semiconductor oscillating element and a variable capacitance element, wherein a tuning circuit including a series resonance circuit including the variable capacitance element and an inductor and an impedance transformer for performing impedance inversion at a desired oscillation frequency is provided. A voltage controlled oscillator characterized in that
【請求項2】 インピーダンス変成器について所望発振
周波数で概90度の電気長をもつ伝送線路で形成するこ
とを特徴とする請求項1記載の電圧制御発振器。
2. The voltage controlled oscillator according to claim 1, wherein the impedance transformer is formed by a transmission line having an electrical length of about 90 degrees at a desired oscillation frequency.
【請求項3】 インピーダンス変成器についてインダク
タと並列キャパシタから成る集中定数回路で形成するこ
とを特徴とする請求項1記載の電圧制御発振器。
3. The voltage controlled oscillator according to claim 1, wherein the impedance transformer is formed by a lumped constant circuit including an inductor and a parallel capacitor.
【請求項4】 集中定数回路について並列キャパシタに
代えて可変容量素子を用い当該インピーダンス変成器の
変成比を変えることを特徴とする請求項3記載の電圧制
御発振器。
4. The voltage controlled oscillator according to claim 3, wherein a variable capacitance element is used instead of the parallel capacitor in the lumped constant circuit to change the transformation ratio of the impedance transformer.
【請求項5】 インピーダンス変成器について1/4波
長結合線路で形成することを特徴とする請求項1記載の
電圧制御発振器。
5. The voltage controlled oscillator according to claim 1, wherein the impedance transformer is formed of a quarter wavelength coupling line.
【請求項6】 1/4波長結合線路について発振条件を
容易に満足するように超伝導材料を用い形成することを
特徴とする請求項5記載の電圧制御発振器。
6. The voltage controlled oscillator according to claim 5, wherein the quarter-wave coupling line is formed of a superconducting material so as to easily satisfy the oscillation condition.
【請求項7】 直列共振回路について当該可変容量素子
に対し互いに半数ずつが異なる極性の向きに偶数個直列
に接続し形成することを特徴とする請求項1、2、3、
4、5または6記載の電圧制御発振器。
7. The serial resonance circuit is formed by connecting even numbers of series variable circuits in the directions of polarities different from each other to the variable capacitance element in series.
The voltage controlled oscillator according to 4, 5, or 6.
【請求項8】 直列共振回路について当該可変容量素子
の等価直列抵抗より十分大きな抵抗を並列に接続し形成
することを特徴とする請求項1、2、3、4、5、6ま
たは7記載の電圧制御発振器。
8. The series resonance circuit is formed by connecting in parallel a resistance sufficiently larger than the equivalent series resistance of the variable capacitance element. Voltage controlled oscillator.
【請求項9】 同調回路についてさらに別途抵抗を直列
に接続し形成することを特徴とする請求項1、2、3、
4、5、6、7または8記載の電圧制御発振器。
9. The tuning circuit is further formed by additionally connecting resistors in series.
The voltage controlled oscillator according to 4, 5, 6, 7 or 8.
【請求項10】 中心周波数の異なる複数のインピーダ
ンス変成器の両端に第1と第2の切替器を設け、所望発
振周波数により当該インピーダンス変成器の1つを選択
することを特徴とする請求項1、2、3、4、5、6、
7、8または9記載の電圧制御発振器。
10. The first and second switching devices are provided at both ends of a plurality of impedance transformers having different center frequencies, and one of the impedance transformers is selected according to a desired oscillation frequency. 2, 3, 4, 5, 6,
7. The voltage controlled oscillator according to 7, 8, or 9.
【請求項11】 電圧制御発振器について当該発振素子
の2つの相異なる端子に対し第1と第2の同調回路を接
続し形成することを特徴とする請求項1、2、3、4、
5、6、7、8、9または10記載の電圧制御発振器。
11. The voltage controlled oscillator according to claim 1, wherein the first and second tuning circuits are connected to two different terminals of the oscillation element.
5. The voltage controlled oscillator according to 5, 6, 7, 8, 9 or 10.
【請求項12】 第1と第2の各同調回路について当該
インピーダンス変成器を所望発振周波数で概45度ない
し90度と概90度ないし135度の電気長をもつ伝送
線路で形成することを特徴とする請求項11記載の電圧
制御発振器。
12. The impedance transformer of each of the first and second tuning circuits is formed by a transmission line having an electrical length of approximately 45 to 90 degrees and approximately 90 to 135 degrees at a desired oscillation frequency. The voltage controlled oscillator according to claim 11.
【請求項13】 第1と第2の各同調回路について当該
直列共振回路に対し異なる可変容量素子印加直流電圧で
当該共振周波数を違えて形成することを特徴とする請求
項11記載の電圧制御発振器。
13. The voltage controlled oscillator according to claim 11, wherein the resonant frequencies of the first and second tuning circuits are formed differently for different DC voltages applied to the series resonant circuit. .
【請求項14】 電圧制御発振器について帰還キャパシ
タに代えて発振電力の一部を入力に帰還する可変容量素
子を設け、発振周波数に応じ当該容量を制御することを
特徴とする請求項1、2、3、4、5、6、7、8、
9、10、11、12または13記載の電圧制御発振
器。
14. A voltage-controlled oscillator, wherein a variable capacitance element for feeding back a part of oscillation power to an input is provided instead of the feedback capacitor, and the capacitance is controlled according to the oscillation frequency. 3, 4, 5, 6, 7, 8,
The voltage controlled oscillator according to 9, 10, 11, 12 or 13.
【請求項15】 電圧制御発振器について別途発振電力
を負荷に結合する可変容量素子を設け、発振周波数に応
じ当該容量を制御することを特徴とする請求項1、2、
3、4、5、6、7、8、9、10、11、12、13
または14記載の電圧制御発振器。
15. The voltage controlled oscillator according to claim 1, further comprising a variable capacitance element for separately coupling oscillation power to a load, and controlling the capacitance according to an oscillation frequency.
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
The voltage controlled oscillator according to 14 above.
【請求項16】 集積回路形成時、発振素子と可変容量
素子に直流電圧を供給する高インピーダンス線路のバイ
アス回路等または発振素子の整合回路等を形成する第1
の基板と低インピーダンスのインピーダンス変成器を形
成する第2の基板との誘電率または基板厚を違えること
を特徴とする請求項2、5、6、7、8、9、10、1
1、12、13、14または15記載の電圧制御発振
器。
16. A first circuit for forming a bias circuit or the like of a high impedance line for supplying a DC voltage to an oscillating element and a variable capacitance element or a matching circuit of an oscillating element when forming an integrated circuit
2. The dielectric constant or the thickness of the second substrate forming the low-impedance impedance transformer is different from that of the substrate of claim 2, 5, 6, 7, 8, 9, 10, 1.
The voltage controlled oscillator according to 1, 12, 13, 14 or 15.
【請求項17】 半導体発振素子と可変容量素子を備え
る電圧制御発振器において、集積回路形成時発振素子の
整合回路等を形成する第1の基板と可変容量素子の取付
パターン等を形成する第2の基板との誘電率または基板
厚を違えることを特徴とする電圧制御発振器。
17. A voltage controlled oscillator comprising a semiconductor oscillator and a variable capacitance element, wherein a first substrate for forming a matching circuit of the oscillation element and the like for forming an integrated circuit and a second pattern for forming a mounting pattern of the variable capacitance element and the like. A voltage-controlled oscillator characterized in that the dielectric constant or the thickness of the substrate is different.
【請求項18】 マイクロ波回路一般に適用する集積バ
イアス回路において、集積回路形成時整合回路等を形成
する第1の基板とスパイラルインダクタその他の高イン
ピーダンス線路のバイアス回路等を形成する第2の基板
との誘電率または基板厚を違えることを特徴とする集積
バイアス回路。
18. An integrated bias circuit generally applied to a microwave circuit, comprising: a first substrate for forming a matching circuit and the like at the time of forming an integrated circuit; and a second substrate for forming a bias circuit for a spiral inductor and other high impedance lines. An integrated bias circuit having different dielectric constants or substrate thicknesses.
【請求項19】 集積回路形成時、第1の基板上に第2
の基板を実装することを特徴とする請求項18記載の集
積バイアス回路。
19. When forming an integrated circuit, a second substrate is formed on the first substrate.
The integrated bias circuit according to claim 18, wherein the substrate is mounted.
【請求項20】 マイクロ波回路一般に適用する集積バ
イアス回路において、集積回路形成時ベースプレート上
に実装する基板上に形成する整合回路に対しベースプレ
ート上に実装する中継用キャパシタを介し、ワイアを空
中に張り直接接続し給電するインダクタを形成すること
を特徴とする集積バイアス回路。
20. In an integrated bias circuit generally applied to a microwave circuit, a wire is extended in the air through a relay capacitor mounted on a base plate to a matching circuit formed on a substrate mounted on the base plate when the integrated circuit is formed. An integrated bias circuit characterized by forming an inductor that is directly connected to supply power.
【請求項21】 集積回路形成時、基板上に設ける貫通
穴の上空を経由するように当該ワイアを空中に張ること
を特徴とする請求項20記載の集積バイアス回路。
21. The integrated bias circuit according to claim 20, wherein, when the integrated circuit is formed, the wire is stretched in the air so as to pass through the through hole provided on the substrate.
【請求項22】 集積回路形成時、ベースプレート上に
設ける段差の下段と上段に当該基板と中継用キャパシタ
を実装することを特徴とする請求項20記載の集積バイ
アス回路。
22. The integrated bias circuit according to claim 20, wherein the substrate and the relay capacitor are mounted on the lower and upper steps of the step provided on the base plate when the integrated circuit is formed.
【請求項23】 集積回路形成時、ベースプレート上に
実装する当該基板上に設ける段差の下段と上段に発振素
子の整合回路と中継用パターンを形成し、当該整合回路
に対し当該中継用パターンを介し当該ワイアを空中に張
ることを特徴とする請求項20記載の集積バイアス回
路。
23. When forming an integrated circuit, a matching circuit of an oscillating element and a relay pattern are formed on a lower stage and an upper stage of a step provided on the substrate to be mounted on a base plate, and the relay pattern is provided to the matching circuit. 21. The integrated bias circuit according to claim 20, wherein the wire is extended in the air.
【請求項24】 集積回路形成時、当該整合回路を形成
する同じ基板上に実装する当該中継用キャパシタを介す
ることを特徴とする請求項20記載の集積バイアス回
路。
24. The integrated bias circuit according to claim 20, wherein when the integrated circuit is formed, the relay capacitor mounted on the same substrate on which the matching circuit is formed is interposed.
【請求項25】 マイクロ波回路一般に適用する集積バ
イアス回路において、集積回路形成時基板上に形成する
伝送線路から垂直上方にワイアを空中に張り上方から給
電するインダクタを形成することを特徴とする集積バイ
アス回路。
25. An integrated bias circuit generally applied to microwave circuits, characterized in that an inductor is formed by vertically extending a wire in the air from a transmission line formed on a substrate at the time of forming the integrated circuit, and feeding the wire from above. Bias circuit.
JP14304695A 1995-06-09 1995-06-09 Voltage controlled oscillator and integrated bias circuit Expired - Fee Related JP3435901B2 (en)

Priority Applications (1)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003110359A (en) * 2001-09-28 2003-04-11 Mitsumi Electric Co Ltd Voltage-controlled oscillation circuit, and receiver using the same circuit
US6628174B2 (en) 2000-11-06 2003-09-30 Sanyo Electric Co., Ltd. Voltage-controlled oscillator and communication device
US6724274B2 (en) 1999-10-29 2004-04-20 Murata Manufacturing Co., Ltd. Frequency-switching oscillator and electronic device using the same
JP2007522769A (en) * 2004-02-10 2007-08-09 ビットウェーブ・セミコンダクター Programmable transceiver
JP2009147899A (en) * 2007-11-22 2009-07-02 Mitsubishi Electric Corp Voltage controlled oscillator
US7675376B2 (en) 2004-06-18 2010-03-09 Mitsubishi Electric Corporation Voltage-controlled oscillator
CN102655395A (en) * 2012-05-23 2012-09-05 中国电子科技集团公司第五十五研究所 Amplifier circuit with cross wiring of direct-current signals and microwave signals
CN107659267A (en) * 2017-10-18 2018-02-02 苏州云芯微电子科技有限公司 A kind of fully differential voltage controlled oscillator of tuning curve linearisation

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724274B2 (en) 1999-10-29 2004-04-20 Murata Manufacturing Co., Ltd. Frequency-switching oscillator and electronic device using the same
US6628174B2 (en) 2000-11-06 2003-09-30 Sanyo Electric Co., Ltd. Voltage-controlled oscillator and communication device
JP2003110359A (en) * 2001-09-28 2003-04-11 Mitsumi Electric Co Ltd Voltage-controlled oscillation circuit, and receiver using the same circuit
JP2007522769A (en) * 2004-02-10 2007-08-09 ビットウェーブ・セミコンダクター Programmable transceiver
US7675376B2 (en) 2004-06-18 2010-03-09 Mitsubishi Electric Corporation Voltage-controlled oscillator
JP2009147899A (en) * 2007-11-22 2009-07-02 Mitsubishi Electric Corp Voltage controlled oscillator
CN102655395A (en) * 2012-05-23 2012-09-05 中国电子科技集团公司第五十五研究所 Amplifier circuit with cross wiring of direct-current signals and microwave signals
CN107659267A (en) * 2017-10-18 2018-02-02 苏州云芯微电子科技有限公司 A kind of fully differential voltage controlled oscillator of tuning curve linearisation
CN107659267B (en) * 2017-10-18 2023-11-21 苏州云芯微电子科技有限公司 Full-differential voltage-controlled oscillator with tuning curve linearization

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