JPH08335629A - Interlayer insulation film forming method - Google Patents

Abstract

PURPOSE: To realize the forming of an interlayer insulation film superior in reliability and the flattening of the surface thereof at low cost. CONSTITUTION: On a substrate (semiconductor substrate 11 having an insulating film 12) a interconnection 14 is formed. A dummy pattern 15 is formed with the same interconnection forming layer 13 as that of the interconnection 14 on other region except an interconnection forming region 15, side wall insulation films 18 and 19 are formed on the side walls of the pattern 15 and interconnection 14, then only the pattern 15 is removed, and insulation film (third insulation film 21) which covers the interconnection 14 and the insulation films 18 and 19 and forms voids 22 inside the insulation film 19. Then the surface of the film 21 is flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film used in a semiconductor device, and more particularly, to forming an interlayer insulating film for flattening the surface, which is used for fine multi-layer wiring of submicron or less. It is about the method.

[0002]

2. Description of the Related Art As semiconductor devices are highly integrated, it is necessary to form fine wiring of submicron or smaller.
Therefore, it is desirable that the surface of the interlayer insulating film forming the wiring be as flat as possible.

[0003]

However, due to the miniaturization of wiring, the depth of focus of exposure in the photolithography process for forming wiring has become smaller. Therefore, the step difference of the interlayer insulating film on which the wiring is formed must be reduced. Further, since the wiring interval is narrowed due to the miniaturization, the inter-wiring capacitance is increased and the device performance (for example, delay time) is deteriorated.

Therefore, as the former measure, there is so-called global flattening for reducing the absolute step. For example, after forming a dummy pattern made of the same layer as the wiring in a region where the wiring space is wide, an interlayer insulating film is formed by a coating material such as SOG (Spin on glass) so that the surface becomes flat. With this method, the process cost can be suppressed to a low level, but since a dummy pattern formed in the same layer as the wiring remains outside the wiring region, there is a problem in that it is difficult to analyze the underlying layer.

As a measure against the latter, a method of forming an interlayer insulating film with a so-called low dielectric constant film (for example, SiOF, organic film) having a low dielectric constant has been adopted. Degassing of H ₂ O etc. occurs. for that reason,
The problem arises that the wiring is affected by those gases and the reliability deteriorates.

It is an object of the present invention to provide a method of forming an interlayer insulating film, which is low in cost and excellent in reliability and is formed flat.

[0007]

The present invention is a method for forming an interlayer insulating film, which has been made to achieve the above object. That is, when forming a wiring on the substrate, a dummy pattern is formed in the same wiring forming layer as this wiring in the area other than the wiring forming area where the wiring is provided (first step). Next, after forming a sidewall insulating film on each side wall of the wiring and the dummy pattern (second step), the dummy pattern is removed (third step). Then, an insulating film is formed so as to cover the wiring and the sidewall insulating film and form a cavity on the side of the sidewall insulating film from which the dummy pattern is removed, and then the surface of the insulating film is flattened (fourth step). To form an interlayer insulating film.

Alternatively, after performing the above first to third steps,
In the fourth step, after forming the insulating film so as to cover the wiring and the sidewall insulating film and fill the side of the sidewall insulating film from which the dummy pattern is removed,
In the fifth step, after the insulating film is etched back until the upper part of the wiring is exposed, another insulating film is formed on the entire surface on the insulating film side.

[0009]

In the method of forming an interlayer insulating film, a dummy pattern is formed in the same wiring forming layer as this wiring in a region other than the wiring forming region, and then a sidewall insulating film is formed on the side wall of the dummy pattern. Since the dummy pattern is removed, the sidewall insulating film functions as the conventional dummy pattern, and the conventional dummy pattern that interferes with the analysis of the base is removed. Therefore, the analysis of the base becomes easy.

Further, in the forming method in which the insulating film is formed in the state where the cavity is provided on the inner side of the sidewall insulating film, the cavity reduces the inter-wiring capacitance of the interlayer insulating film.

Further, in the forming method in which the sidewall insulating film is formed on the side wall of the wiring and the insulating film is etched back so that the upper portion of the wiring is exposed, even if the insulating film is formed of a low dielectric constant film, The wiring and the low dielectric constant film are formed in a separated state. Therefore, even if there is a degassing phenomenon such as fluorine or H ₂ O from the low dielectric constant film, the wiring is not affected. Further, since the sidewall insulating film is left in the region other than the wiring formation region, it is possible to prevent the third insulating film formed in the region covering the sidewall insulating film from being thinned.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. 1 and 2 (1) and 2).

As shown in FIG. 1A, in the first step, a semiconductor substrate 11 on which a semiconductor element (not shown) is formed.
A first insulating film 12 is formed on the upper surface of the first insulating film 12, for example, by chemical vapor deposition
By CVD, CVD is an abbreviation for Chemical Vapor Deposition.
G) or silicon oxide (SiO ₂ ) is, for example, 500 n
It is formed by depositing to a thickness of m.

Next, after a wiring forming layer made of an aluminum-based metal (for example, aluminum-copper alloy) is formed to a thickness of, for example, 500 nm by, for example, sputtering, a lithography technique (for example, resist coating, exposure, development, baking, etc.) is performed. And by etching
The portion of the wiring forming layer 13 indicated by the chain double-dashed line is removed, and the wiring 14 and the dummy pattern 15 are formed in the wiring forming layer 13. At this time, the wiring 13 is formed in the wiring forming area 16, and the dummy pattern 15 is formed in the entire area other than the wiring forming area 16. Further, it is desirable that the dummy patterns 15 having substantially uniform pattern sizes are formed at substantially uniform intervals for the purpose of so-called global flattening. Here, for example, the dummy pattern 15 is formed in a square pattern in which one side is a (for example, a = 0.3 μm), and is arranged at intervals of d (for example, d = 1.5 μm).

Then, a resist mask (not shown) formed by the above-mentioned lithography technique is ashed, for example.
It is removed by a wet process using a stripping solution.

Next, the second step shown in FIG. 1B is performed. In this step, for example, tetraethoxysilane (TE
The first insulating film 12 is formed by the CVD method using OS).
A second insulating film 17 that covers the wiring 14 is formed on the silicon oxide film having a thickness of 500 nm, for example. Thereafter, reactive ion etching (hereinafter referred to as RIE) is performed to etch back the portion of the second insulating film 17 indicated by the chain double-dashed line to form the sidewall insulating films 18 and 19 on the side walls of the wiring 14 and the dummy pattern 15. To form.

Then, a third step is performed as shown in FIG. In this step, lithography technology (for example,
Resist coating, exposure, development, baking, etc.)
After forming the etching mask 20 so as to cover the wiring 14, the dummy pattern 15 is formed by RIE, for example.
(The portion indicated by the chain double-dashed line) is removed. Then, the etching mask 20 is removed by, for example, ashing, a wet process using a stripping solution, or the like.

Thereafter, a fourth step is performed as shown in FIG. In this step, a third insulating film 21 that covers the wiring 14 and the sidewall insulating films 18 and 19 is formed on the first insulating film 12 by, for example, a CVD method using tetraethoxysilane (TEOS). Is 60
It is formed of a 0 nm silicon oxide film. At that time, the third insulating film 21 is formed in a state where the cavity 22 is formed on the inner side of the sidewall insulating film 19. The cavity 22 is formed by reducing the dimension of one side of the dummy pattern (15) by utilizing the fact that the film formation of the third insulating film 21 in the step portion is overhanging.

Then, a flattening film 23 having a thickness of, for example, 0.8 μm is formed on the third insulating film 21 by, for example, a coating method. The flattening film 23 is formed of, for example, an organic material (for example, resist) or an inorganic material [for example, SOG (Spin on).
glass)].

After that, the flattening film 23 and the third film are formed.
The flattening film 23 is formed by etching back the upper part of the insulating film 21.
Is removed. Further, the upper portion of the third insulating film 21 is etched back to flatten the surface of the third insulating film 21, as shown in FIG. This etching is performed under the condition that the etching rates of the flattening film 23 and the third insulating film 21 are almost the same. By performing the etch back under such etching conditions, the flatness of the surface of the flattening film 23 can be reflected on the surface of the third insulating film 21.

Then, in order to adjust the film thickness of the interlayer insulating film on the wiring 14, for example, tetraethoxysilane (T
The third insulating film 2 is formed by the CVD method using EOS).
A fourth insulating film 24 is formed of a silicon oxide film having a thickness of 500 nm, for example. Therefore, if the thickness of the third insulating film 21 on the wiring 14 is sufficient, it is not necessary to form the fourth insulating film 24. The interlayer insulating film 25 is formed as described above.

In the method for forming an interlayer insulating film of the first embodiment, the dummy pattern 15 is formed in the same wiring forming layer 13 as the wiring 14 in the area other than the wiring forming area 16, and the sidewall of the dummy pattern 15 is further formed. Sidewall insulation film 1
After forming 9, the dummy pattern 15 alone is removed, so that the wiring forming layer 13 made of a metal film does not remain on the region where the dummy pattern 15 is formed. In other words,
The pattern formed by the wiring forming layer 13 does not remain in the area other than the wiring forming area 16. Therefore, the wiring formation layer 1
Since 3 is not disturbed, the analysis of the base becomes easy. In addition, the cavity 2 is formed on the inner side of the sidewall insulating film 19.
Since the third insulating film 21 is formed in the state where 2 is formed, the inter-wiring capacitance of the interlayer insulating film 25 is reduced by the cavity 22.

Next, a second embodiment will be described with reference to the process chart of FIG. In the figure, the same components as those described with reference to FIGS. 1 and 2 are designated by the same reference numerals.

The same steps as the first to third steps shown in (1) to (3) of FIG. 1 of the first embodiment are carried out, and FIG.
(1), the wiring 14 and the sidewall insulating film 1 are formed on the first insulating film 12 formed on the semiconductor substrate 11.
8 and 19 are formed. At this time, for example, a dummy pattern (not shown) is formed as a square pattern with one side a (for example, a = 0.8 μm), and is formed as d (for example, d = 1.0).
μm). By forming the dummy pattern in this way, the sidewall insulating film 1 is formed later.
When the third insulating film is formed so as to cover 9 the cavities are not formed on the inner side of the sidewall insulating film 19.

Next, the fourth step shown in FIG. 3B is performed. In this step, a third dielectric film made of a low dielectric constant film is formed so as to cover the wiring 14 and the sidewall insulating films 18 and 19.
The insulating film 21 is formed. The low dielectric constant film is, for example, a coating film of an organic material such as organic SOG, for example, 0.8 μm.
It is formed to a thickness of about m. The third insulating film 21 is preferably a coating film that can be flattened because the surface flatness after etching back is good, but it is formed by a CVD method as another low dielectric constant film, for example. It may be formed of a silicon oxide (SiOF) film doped with fluorine.

Subsequently, the third insulating film 21 is etched back to expose the upper portion of the wiring 14 as shown in (3) of FIG. By doing so, the wiring 14 and the third insulating film 21 made of a low dielectric constant film containing water or the like are separated by the sidewall insulating film 18.

Then, the fifth step is performed. In this step, for example, CVD using tetraethoxysilane (TEOS)
By the method, the fourth insulating film 24 is formed on the entire surface on the side of the third insulating film 21 by a silicon oxide film having a thickness of 500 nm, for example. The fourth insulating film 24 is formed to have a film thickness that functions as an interlayer insulating film on the wiring 14. As described above, the interlayer insulating film 2 including the third and fourth insulating films 21 and 24
5 is formed.

In the method of forming the interlayer insulating film of the second embodiment, the dummy pattern is removed in the region where the wiring 14 is arranged in a rough state, and the sidewall insulating film 19 formed on the side wall of the dummy pattern remains. Therefore, the metal film that interferes with the analysis of the base is not formed. Therefore, the analysis of the base becomes easy.

Further, since the sidewall insulating film 18 is formed on the side wall of the wiring 14 and the third insulating film 21 is etched back so that the upper portion of the wiring 14 is exposed, the third insulating film 21 is formed into a low dielectric constant film. Even if the structure is formed by
The fourth insulating film 21 and the third insulating film 21 are separated by the sidewall insulating film 18. Therefore, even if there is a degassing phenomenon such as fluorine or H ₂ O from the low dielectric constant film forming the third insulating film 21, the wiring 14 is not affected.

Further, since the side wall insulating film 19 is left in the region where the wiring 14 is arranged in a rough state, the film thickness of the third insulating film 21 formed so as to cover the side wall insulating film 19 in that region becomes thin. Is prevented.

The forming methods of the first and second embodiments are based on a low cost technique such as a sidewall forming technique and a CVD method. Therefore, the manufacturing cost is low.

[0032]

As described above, according to the present invention,
After forming a dummy pattern formed in the same wiring formation layer as this wiring in a region where the wiring arrangement state is rough, and further forming a sidewall insulating film on the side wall of the dummy pattern,
Since only the dummy pattern is removed, the background can be easily analyzed.

Further, according to the forming method of forming the insulating film in the state where the cavity is formed on the inner side of the sidewall insulating film, the cavity can reduce the inter-wiring capacitance of the interlayer insulating film.

Further, in the forming method of forming the side wall insulating film on the side wall of the wiring and etching back the insulating film so that the upper portion of the wiring is exposed, even if the insulating film is formed of the low dielectric constant film, The wiring and the low dielectric constant film can be formed in a separated state. Therefore, even if there is a degassing phenomenon such as fluorine or H ₂ O from the low dielectric constant film, the wiring is not affected, so that the reliability of the wiring can be improved.

[Brief description of drawings]

FIG. 1 is a process diagram (part 1) of forming a first embodiment of the present invention.

FIG. 2 is a second manufacturing process diagram of the first embodiment of the present invention.

FIG. 3 is a process drawing of a second embodiment of the present invention.

[Explanation of symbols]

 11 Semiconductor Substrate 13 Wiring Forming Layer 14 Wiring 15 Dummy Pattern 16 Wiring Forming Area 18 Sidewall Insulating Film 19 Sidewall Insulating Film 21 Third Insulating Film 22 Cavity 25 Interlayer Insulating Film

Claims (2)

[Claims] 1. When forming a wiring on a substrate, a first step of forming a dummy pattern in the same wiring formation layer as the wiring in a region other than the wiring formation region in which the wiring is provided; And a second step of forming a side wall insulating film on each side wall of the dummy pattern, a third step of removing the dummy pattern, a step of covering the wiring and the side wall insulating film and the dummy in the side wall insulating film. And a fourth step of flattening the surface of the insulating film after forming the insulating film on the side where the pattern is removed to provide a cavity. 2. A first step of forming a dummy pattern in the same wiring forming layer as the wiring in a region other than the wiring forming region where the wiring is provided, when the wiring is formed on the substrate, and the wiring. And a second step of forming a side wall insulating film on each side wall of the dummy pattern, a third step of removing the dummy pattern, a step of covering the wiring and the side wall insulating film and the dummy in the side wall insulating film. Fourth step of forming an insulating film in a state where the side where the pattern is removed is buried, and after etching back the insulating film until the upper part of the wiring is exposed, another insulating film is formed on the entire surface of the insulating film side. And a fifth step of forming an interlayer insulating film.