JPH08335529A - Thin-film chip parts - Google Patents

Thin-film chip parts

Info

Publication number
JPH08335529A
JPH08335529A JP16692995A JP16692995A JPH08335529A JP H08335529 A JPH08335529 A JP H08335529A JP 16692995 A JP16692995 A JP 16692995A JP 16692995 A JP16692995 A JP 16692995A JP H08335529 A JPH08335529 A JP H08335529A
Authority
JP
Japan
Prior art keywords
layer
film chip
thin film
chip component
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16692995A
Other languages
Japanese (ja)
Inventor
Kenji Sato
健治 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP16692995A priority Critical patent/JPH08335529A/en
Publication of JPH08335529A publication Critical patent/JPH08335529A/en
Pending legal-status Critical Current

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  • Conductive Materials (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE: To provide a reliable and inexpensive thin-film chip part by preventing the fluctuation and scattering of, for example, resistance which is the characteristic failure and deterioration of, for example, disconnection and short-circuiting. CONSTITUTION: Thin-film chip parts are provided with a double-layer conductor layer 2 manufactured on a substrate 1 by sputtering and an external electrode 6 where Ni layer and further semiconductor layer film are formed on the upper layer of a terminal ground electrode 5 which is coated by the dip coating method, is tentatively dried, and is formed by heat treatment by the electroplating method using a conductive resin with a conductivity by mixing, for example, silver power, copper, and gold power to thermosetting epoxy or phenol resin which can be formed at 200 deg.C so that it is constituted of insulation layer 3 made of double-layer polyimide resin, is cut into a chip size, and is led from an end face part to an electrode part 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子装置の回路に使用
される表面実装部品である薄膜チップ部品の外部電極と
なる端子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal which is an external electrode of a thin film chip component which is a surface mount component used for a circuit of an electronic device.

【0002】[0002]

【従来の技術】従来の薄膜チップ部品は、図7に示すよ
うに、基板1b、導体層2b、絶縁層3b、電極部4
b、焼付銀あるいはスパッタリングによって形成された
端子下地電極5b、半田めっき(下地Niめっき)した
外部電極6bから構成される。
2. Description of the Related Art As shown in FIG. 7, a conventional thin film chip component has a substrate 1b, a conductor layer 2b, an insulating layer 3b, and an electrode portion 4.
b, a terminal base electrode 5b formed by baking silver or sputtering, and a solder-plated (base Ni-plated) external electrode 6b.

【0003】従来の技術として厚膜チップ部品の端子
は、ディップ塗布方法で前記端子下地電極をガラスフリ
ットを混合した、600℃以上の熱処理で焼き付けてい
た導電性材料によって形成する。
As a conventional technique, a terminal of a thick film chip component is formed by a dip coating method using a conductive material in which the terminal base electrode is mixed with glass frit and baked by a heat treatment at 600 ° C. or higher.

【0004】また、薄膜チップ部品の端子では、前記端
子下地電極をスパッタリングによって形成し、その上層
にNi層、半田層の膜を電気めっき法にて外部電極を形
成していた。
Further, in the terminal of the thin film chip component, the terminal base electrode is formed by sputtering, and the Ni layer and the solder layer are formed on the upper layer as the external electrode by electroplating.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
薄膜チップ部品では、400℃以上の温度で30分以上
処理すると、断線、短絡等の特性不良、あるいは特性劣
化としての抵抗値等の変動およびばらつきが増加するた
め、上記の特性不良、あるいは特性劣化としての抵抗値
等の変動およびばらつきが少ない、高い生産性を有する
ディップ塗布方式で、400℃以下の、望ましくは16
0〜240℃の温度で30分以下で処理できるようにし
たかった。しかしながら、従来の薄膜チップ部品では、
厚膜チップ部品と同様に、高い生産性のディップ塗布方
式にて焼付け可能な導電性材料を塗布し、厚膜チップ部
品の端子を形成する方法を利用しようとすると、600
℃以上の温度で焼付けしなければならないので、400
℃以下で処理する端子下地電極を形成することができな
いという課題があった。
However, in the conventional thin film chip component, when it is treated at a temperature of 400 ° C. or higher for 30 minutes or longer, characteristic defects such as disconnection and short circuit, or fluctuations and variations in resistance value or the like as characteristic deterioration. Therefore, it is a dip coating method with high productivity in which there is little fluctuation and variation in resistance value or the like as the above-mentioned characteristic defect or characteristic deterioration.
I wanted to be able to process at temperatures of 0-240 ° C. in less than 30 minutes. However, in the conventional thin film chip parts,
Similar to the thick film chip component, when a method of forming a terminal of the thick film chip component by applying a bakeable conductive material by a high productivity dip coating method is used, 600
Since it must be baked at a temperature of ℃ or higher, 400
There is a problem in that it is not possible to form a terminal base electrode that is processed at a temperature of not more than ° C.

【0006】また、前記端子下地電極をスパッタリング
で形成するには、高い真空雰囲気を必要とするので、設
備的に生産性が低く、かつ高額な設備であり、安価な薄
膜チップ部品を提供し難いという課題があった。
Further, since a high vacuum atmosphere is required to form the terminal base electrode by sputtering, the productivity is low and the equipment is expensive, and it is difficult to provide an inexpensive thin film chip component. There was a problem.

【0007】本発明の目的は、断線、短絡等の特性不良
及び特性劣化である抵抗値等の変動、ばらつきを少なく
し、生産性及び信頼性が高い、安価な薄膜チップ部品を
提供することにある。
An object of the present invention is to provide an inexpensive thin film chip component which has a high productivity and a high reliability, in which fluctuations and variations in resistance values, which are characteristic defects and characteristic deteriorations such as disconnection and short circuit, are reduced. is there.

【0008】[0008]

【課題を解決するための手段】本発明は、従来の技術の
欠点を解決すべく、基板上に少なくとも1層以上作製
した導体層と、絶縁層で構成された、外部電極を有する
薄膜チップ部品において、前記外部電極には、少なくと
も400℃以下の熱処理で形成可能な熱硬化樹脂に金属
粉を混入させ、導電性を具備した導電性材料によって形
成された端子下地電極を有することを特徴とする薄膜チ
ップ部品と、記載の前記端子下地電極は、厚膜技術
により前記導電性材料にて形成されたことを特徴とする
薄膜チップ部品とを提供するものである。
In order to solve the drawbacks of the prior art, the present invention is a thin film chip component having an external electrode, which is composed of at least one conductor layer formed on a substrate and an insulating layer. In the above-mentioned, the external electrode has a terminal base electrode formed of a conductive material having conductivity by mixing metal powder into a thermosetting resin that can be formed by a heat treatment of at least 400 ° C. or less. The present invention provides a thin film chip component and a thin film chip component characterized in that the terminal underlying electrode is formed of the conductive material by a thick film technique.

【0009】[0009]

【作用】ディップ塗布方式で、かつ400℃以下の、望
ましくは160〜240℃の温度で30分以下で熱硬化
エポキシ又はフェノール系樹脂に銀粉末、銅、金粉等の
金属粉を混合させ、導電性を有する導電性材料を前記端
子下地電極に使用することによって、製造工程内におけ
る断線、短絡等の特性不良、特性劣化である抵抗値等の
変動、ばらつきの増加を防ぐことができ、また薄膜チッ
プ部品として製品特性および信頼性が充分に満足でき、
かつ生産性が高く、安価な薄膜チップ部品を提供するこ
とが可能となる。
In the dip coating method, the thermosetting epoxy or phenolic resin is mixed with metal powder such as silver powder, copper or gold powder at a temperature of 400 ° C. or lower, preferably 160 to 240 ° C. for 30 minutes or less to conduct electricity. By using a conductive material having a property for the terminal base electrode, it is possible to prevent characteristic defects such as disconnection and short-circuiting in the manufacturing process, fluctuations in resistance value, which is characteristic deterioration, and increase in variations. As a chip component, we can fully satisfy the product characteristics and reliability,
Moreover, it becomes possible to provide a thin film chip component which has high productivity and is inexpensive.

【0010】[0010]

【実施例】以下、本発明による実施例について図面を用
いて説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0011】図1は、本発明の実施例である薄膜チップ
部品の断面図である。図2ないし図5は、本発明の薄膜
チップ部品の端子を形成する工程を示す説明図である。
図6は、本発明の実施例である薄膜チップ部品の斜視図
である。
FIG. 1 is a sectional view of a thin film chip component which is an embodiment of the present invention. 2 to 5 are explanatory views showing a process of forming terminals of the thin film chip component of the present invention.
FIG. 6 is a perspective view of a thin film chip component which is an embodiment of the present invention.

【0012】図1に示すように、本発明の薄膜チップ部
品は、基板1と、該基板1上にスパッタリングにて作製
した2層の導体層2と、ポリイミド樹脂の絶縁層3と、
電極部4とで構成し、チップサイズに切断を行い、得ら
れたチップの端面部から電極部4まで回り込むように、
200℃で形成可能な熱硬化エポキシ又はフェノール系
樹脂に銀粉末、他に銅、金粉等を混入させ導電性を有す
る導電性樹脂を用いて、ディップ塗布方法によって塗布
し、仮乾燥を行い、硬化するための熱処理によって形成
した端子下地電極5と、前記端子下地電極5の上層に電
気めっき法にてNi層、更に半田層の膜を形成した外部
電極6とをチップの両端に設けたものである。
As shown in FIG. 1, the thin film chip component of the present invention comprises a substrate 1, two conductor layers 2 formed on the substrate 1 by sputtering, and an insulating layer 3 of polyimide resin.
It is composed of the electrode part 4 and is cut into a chip size so as to wrap around from the end surface part of the obtained chip to the electrode part 4,
A thermosetting epoxy or phenolic resin that can be formed at 200 ° C is mixed with silver powder, copper, gold powder, etc., and a conductive conductive resin is used. The conductive resin is applied by the dip coating method, temporarily dried, and cured. A terminal underlayer electrode 5 formed by a heat treatment for heat treatment, and an external electrode 6 on which a Ni layer and a solder layer film are formed on the terminal underlayer electrode 5 by electroplating are provided at both ends of the chip. is there.

【0013】前記薄膜チップ部品は、図2に示すよう
に、矩形板状のチップ7からなる。図3は、図2に示す
チップサイズに切断された前記チップ7を、キャリア8
の挿入孔12に長手方向に挿入した状態を示す図であ
る。
As shown in FIG. 2, the thin film chip component comprises a rectangular plate-shaped chip 7. In FIG. 3, the chip 7 cut into the chip size shown in FIG.
It is a figure which shows the state inserted in the insertion hole 12 in the longitudinal direction.

【0014】前記チップ7は、前記の基板上にスパッタ
リングで作製した2層の導体層2と、ポリイミド樹脂の
絶縁層3と、電極部4とで構成され、所定のサイズに切
断される。
The chip 7 is composed of two conductor layers 2 formed on the substrate by sputtering, an insulating layer 3 of polyimide resin, and an electrode portion 4, and cut into a predetermined size.

【0015】前記チップ7は、図4(a)に示すよう
に、前記キャリア8の挿入孔12に挿入され、図4
(b)に示すように、一方の端面を面出しピン9によっ
て面出しを行う。更に、図5に示すように、前記チップ
7の端面部が定盤11上で定厚にのばした前記導電性樹
脂10に押圧され、その端面部に前記導電性樹脂10を
ディップ塗布するものである。
The chip 7 is inserted into the insertion hole 12 of the carrier 8 as shown in FIG.
As shown in (b), one end face is chamfered by the chamfer pin 9. Further, as shown in FIG. 5, the end face of the chip 7 is pressed by the conductive resin 10 having a constant thickness on the surface plate 11, and the conductive resin 10 is dip-coated on the end face. Is.

【0016】以上、述べたように、端面部に導電性樹脂
10をディップ塗布したチップを、120〜200℃の
雰囲気中で10〜30分間仮乾燥を行うことで、一方の
端子下地電極を形成する。
As described above, one of the terminal base electrodes is formed by temporarily drying the chip whose end face is coated with the conductive resin 10 in the atmosphere of 120 to 200 ° C. for 10 to 30 minutes. To do.

【0017】また、他方の端面も同様に、面出しピン9
によってチップ7の他方の端面部を面出しピン9によっ
て面出しを行い、定盤11上で定厚にのばした導電性樹
脂10を端面部にディップ塗布し、前記雰囲気中で仮乾
燥して他方の端子下地電極も形成する。
Similarly, the other end face also has a surfacing pin 9
The other end face of the chip 7 is faced by the face-up pin 9, and the conductive resin 10 spread to a constant thickness on the surface plate 11 is dip-coated on the end face and temporarily dried in the atmosphere. The other terminal base electrode is also formed.

【0018】そして、200〜250℃雰囲気中にて2
0〜30分間硬化するための熱処理を行うことで、チッ
プ7の長手方向の両端に、図1に示すような端子下地電
極5を形成する。
Then, in an atmosphere of 200 to 250 ° C., 2
By performing heat treatment for hardening for 0 to 30 minutes, the terminal base electrodes 5 as shown in FIG. 1 are formed on both ends of the chip 7 in the longitudinal direction.

【0019】図6は、上述した本発明による薄膜チップ
部品の端子を薄膜インダクタに適用した実施例を示すも
のである。
FIG. 6 shows an embodiment in which the terminals of the thin film chip component according to the present invention described above are applied to a thin film inductor.

【0020】薄膜チップ部品は、図6に示すように、基
板1a上にスパッタリングで作製した2層からなる導体
層2aと、ポリイミド樹脂による絶縁層3aと、電極部
とで構成されたチップに、前記端子下地電極を形成し、
その上層に電気めっき法にてNi層、更に半田層の膜を
形成した外部電極6aを施したものである。
As shown in FIG. 6, the thin film chip component is a chip composed of two conductor layers 2a formed by sputtering on a substrate 1a, an insulating layer 3a made of a polyimide resin, and an electrode portion. Forming the terminal base electrode,
An external electrode 6a having a Ni layer and a solder layer film formed thereon by an electroplating method is provided on the upper layer thereof.

【0021】なお、絶縁層であるポリイミド樹脂の代わ
りにSiO2等を使用してもよい。
Incidentally, SiO 2 or the like may be used instead of the polyimide resin which is the insulating layer.

【0022】また、導電性樹脂10を定厚にする方法
は、スキージングでもスクリーン版を使用しても、同様
の効果が得られ、また、ディップ塗布後にブロッテング
を行うことで、塗布量を、より安定できる。
The method of making the conductive resin 10 to a constant thickness has the same effect whether squeezing or a screen plate is used, and the amount of coating is changed by performing blotting after dip coating. Can be more stable.

【0023】[0023]

【発明の効果】以上の説明の通り、400℃以下の熱処
理で形成可能な導電性樹脂をチップの端面から電極部に
塗布し、仮乾燥の後、硬化のための熱処理によって端子
下地電極を形成することによって、断線、短絡等の特性
不良及び特性劣化である抵抗値等の変動、ばらつきを少
なくし、安定な製品特性と高い信頼性を充分に満足で
き、安価で生産性の高い薄膜チップ部品を提供すること
が可能となった。
As described above, the conductive resin which can be formed by the heat treatment at 400 ° C. or lower is applied to the electrode portion from the end face of the chip, and after the temporary drying, the terminal base electrode is formed by the heat treatment for curing. By doing so, it is possible to reduce fluctuations and variations in resistance values, which are characteristic defects and deteriorations such as disconnection and short circuit, and to fully satisfy stable product characteristics and high reliability, and are inexpensive and highly productive thin film chip components. It has become possible to provide.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例である薄膜チップ部品の断面図
である。
FIG. 1 is a cross-sectional view of a thin film chip component that is an embodiment of the present invention.

【図2】本発明の実施例の薄膜チップ部品に用いるチッ
プを示す斜視図である。
FIG. 2 is a perspective view showing a chip used in the thin film chip component of the embodiment of the present invention.

【図3】本発明の実施例を説明するキャリアにチップを
挿入する工程を示す斜視図である。
FIG. 3 is a perspective view showing a step of inserting a chip into a carrier for explaining an embodiment of the present invention.

【図4】本発明の実施例の薄膜チップ部品に用いるチッ
プの面出しの工程を示す説明図である。図4(a)は、
キャリアにチップを挿入した工程を示す断面図である。
図4(b)は、面出しピンでチップの端面を押し、面出
しした工程を示す断面図である。
FIG. 4 is an explanatory diagram showing a process of chamfering a chip used for a thin film chip component of an example of the present invention. Figure 4 (a)
It is sectional drawing which shows the process which inserted the chip in the carrier.
FIG. 4 (b) is a cross-sectional view showing a step of pushing the end face of the chip with the chamfering pin to perform chamfering.

【図5】本発明の実施例の薄膜チップ部品に用いるチッ
プをディップ塗布する工程を示す説明図である。
FIG. 5 is an explanatory diagram showing a step of dip-coating a chip used in the thin film chip component of the example of the present invention.

【図6】本発明の実施例である薄膜チップ部品の斜視図
である。
FIG. 6 is a perspective view of a thin film chip component that is an embodiment of the present invention.

【図7】従来の薄膜チップ部品の断面図である。FIG. 7 is a cross-sectional view of a conventional thin film chip component.

【符号の説明】[Explanation of symbols]

1,1a,1b 基板 2,2a,2b 導体層 3,3a,3b 絶縁層 4,4b 電極部 5 端子下地電極(導電性樹脂) 5b 端子下地電極(焼付け或はスパッタリング) 6,6a,6b 外部電極(Niめっき/半田めっ
き) 7 チップ 8 キャリア 9 面出しピン 10 導電性樹脂 11 定盤 12 挿入孔
1, 1a, 1b Substrate 2, 2a, 2b Conductor layer 3, 3a, 3b Insulating layer 4, 4b Electrode part 5 Terminal base electrode (conductive resin) 5b Terminal base electrode (baking or sputtering) 6, 6a, 6b External Electrode (Ni plating / solder plating) 7 Chip 8 Carrier 9 Chamfering pin 10 Conductive resin 11 Surface plate 12 Insertion hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に少なくとも1層以上作製した導
体層と、絶縁層で構成された外部電極を有する薄膜チッ
プ部品において、前記外部電極には、少なくとも400
℃以下の熱処理で形成可能な熱硬化樹脂に金属粉を混入
させ、導電性を具備した導電性材料によって形成された
端子下地電極を有することを特徴とする薄膜チップ部
品。
1. A thin film chip component having a conductor layer made of at least one layer on a substrate and an external electrode composed of an insulating layer, wherein the external electrode is at least 400.
A thin film chip component comprising a terminal base electrode formed of a conductive material having conductivity by mixing metal powder into a thermosetting resin that can be formed by heat treatment at a temperature of ℃ or less.
【請求項2】 請求項1記載の前記端子下地電極は、厚
膜技術により前記導電性材料にて形成されたことを特徴
とする薄膜チップ部品。
2. The thin film chip component according to claim 1, wherein the terminal base electrode is formed of the conductive material by a thick film technique.
JP16692995A 1995-06-07 1995-06-07 Thin-film chip parts Pending JPH08335529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16692995A JPH08335529A (en) 1995-06-07 1995-06-07 Thin-film chip parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16692995A JPH08335529A (en) 1995-06-07 1995-06-07 Thin-film chip parts

Publications (1)

Publication Number Publication Date
JPH08335529A true JPH08335529A (en) 1996-12-17

Family

ID=15840283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16692995A Pending JPH08335529A (en) 1995-06-07 1995-06-07 Thin-film chip parts

Country Status (1)

Country Link
JP (1) JPH08335529A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294722A (en) * 2005-04-07 2006-10-26 Matsushita Electric Ind Co Ltd Electronic component and its manufacturing method
WO2015186780A1 (en) * 2014-06-04 2015-12-10 株式会社村田製作所 Electronic component and method for producing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294722A (en) * 2005-04-07 2006-10-26 Matsushita Electric Ind Co Ltd Electronic component and its manufacturing method
WO2015186780A1 (en) * 2014-06-04 2015-12-10 株式会社村田製作所 Electronic component and method for producing same
CN105849831A (en) * 2014-06-04 2016-08-10 株式会社村田制作所 Electronic component and method for producing same
US20170032887A1 (en) * 2014-06-04 2017-02-02 Murata Manufacturing Co., Ltd. Electronic component and manufacturing method for the same
JPWO2015186780A1 (en) * 2014-06-04 2017-04-20 株式会社村田製作所 Electronic component and manufacturing method thereof
US11227715B2 (en) 2014-06-04 2022-01-18 Murata Manufacturing Co., Ltd. Electronic component

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