JPH0833436B2 - Integrated circuit test method - Google Patents

Integrated circuit test method

Info

Publication number
JPH0833436B2
JPH0833436B2 JP58109199A JP10919983A JPH0833436B2 JP H0833436 B2 JPH0833436 B2 JP H0833436B2 JP 58109199 A JP58109199 A JP 58109199A JP 10919983 A JP10919983 A JP 10919983A JP H0833436 B2 JPH0833436 B2 JP H0833436B2
Authority
JP
Japan
Prior art keywords
distribution
random number
test pattern
test
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58109199A
Other languages
Japanese (ja)
Other versions
JPS601578A (en
Inventor
昭光 立石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58109199A priority Critical patent/JPH0833436B2/en
Publication of JPS601578A publication Critical patent/JPS601578A/en
Publication of JPH0833436B2 publication Critical patent/JPH0833436B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、LSI等に適用可能な集積回路の試験方法に
関する。
Description: TECHNICAL FIELD The present invention relates to an integrated circuit test method applicable to an LSI or the like.

〔従来技術とその問題点〕[Prior art and its problems]

従来、種々のテストパターン発生装置が考案されてい
るが乱数入力の発生装置においては、発生乱数をそのま
ま入力、又は一様な変換により、テストパターンとして
発生させる装置が主に提案されている。例えば24入力の
回路の場合乱数をAD変換しテストパターンとして発生さ
せた場合、一組24個の“1"又は“0"が、一つのテストパ
ターンとして形成される。そこで、その一組中の“1"の
数(以後“重み”と略す)を横軸にとり、その“重み”
に対応する発生確率を、縦軸にとり、一様乱数発生装置
により、3000組のテストパターンを発生させた場合の分
布を第1図に示す。
Conventionally, various test pattern generators have been devised, but as a generator for random number input, a device for generating a test pattern by directly inputting a generated random number or by uniform conversion has been mainly proposed. For example, in the case of a circuit with 24 inputs, when a random number is AD-converted and generated as a test pattern, a set of 24 "1" s or "0" s is formed as one test pattern. Therefore, the number of "1" s in the set (hereinafter abbreviated as "weight") is taken on the horizontal axis, and the "weight"
FIG. 1 shows the distribution in the case where 3000 sets of test patterns are generated by the uniform random number generation device, with the vertical axis representing the occurrence probability corresponding to.

図より、入力が一様乱数である限り、その分布は2項
分布になる事がわかる。
From the figure, it can be seen that the distribution is a binomial distribution as long as the input is a uniform random number.

又、一様な変換すなわち“1",“0"の出現確率を単に
変化させた場合は、第1図の分布を横軸方向に移動させ
た分布に他ならない。
Further, when the uniform conversion, that is, the appearance probabilities of "1" and "0" are simply changed, it is nothing but the distribution obtained by moving the distribution in FIG. 1 in the horizontal axis direction.

しかしながら以上の方式ではその“重み”の分布が2
項分布である為、できるだけ少ないテストパターンを発
生させて試験する場合、種々の重みのパターンを発生さ
せたくても、確率分布として限定させたパターンでは、
発生しにくい物が多い。例えば“0"が20個、“1"が4個
のテストパターンは2項分布で発生した場合、約0.03%
の確率、すなわち、1万パターンに3回の割合で出現す
るにすぎない。
However, in the above method, the distribution of the "weight" is 2
Since it is a term distribution, if you want to generate as few test patterns as possible and test it, even if you want to generate patterns with various weights, with a pattern limited as a probability distribution,
There are many things that are difficult to generate. For example, if a test pattern with 20 "0" s and 4 "1" s occurs in a binomial distribution, it is approximately 0.03%.
, That is, it appears only three times in 10,000 patterns.

さらに一様な変換を加えた場合においても、平行移動
させた逆方向の“重み”については、同様の事が言え、
入力数が増すにつれこの傾向は顕著となる。例えばAND
ゲートとORゲートにより構成、かつその比が異なる場合
には従来は全く適用できない。
The same thing can be said about the “weight” in the reverse direction that is translated even if a uniform transformation is added.
This tendency becomes more remarkable as the number of inputs increases. For example AND
Conventionally, it cannot be applied to the case where the gate and the OR gate are configured and the ratios thereof are different.

〔発明の目的〕[Object of the Invention]

本発明はこの点を考慮し、回路データ等外部データに
より、テストパターンの重みを自由に制御し集積回路の
試験を容易にする事を目的とするものである。
In consideration of this point, the present invention has an object to freely control the weight of a test pattern by external data such as circuit data to facilitate testing of an integrated circuit.

〔発明の概要〕[Outline of Invention]

本発明は、一様乱数発生装置の後段に発生した乱数の
分布を制御する乱数分布変換装置を設け、更にこの乱数
分布に応じて特定の論理値を所定の確率で出力するテス
トパターン発生装置を設け、外部2値により前記論理値
の出現確率分布の重み軸方向への移動及びその形状変化
が制御されるようにした事を特徴とする。
The present invention provides a random number distribution conversion device that controls the distribution of random numbers generated in the subsequent stage of a uniform random number generation device, and further provides a test pattern generation device that outputs a specific logical value with a predetermined probability according to this random number distribution. It is characterized in that the movement of the logical value appearance probability distribution in the weight axis direction and its shape change are controlled by external binary values.

〔発明の効果〕〔The invention's effect〕

本発明によれば外部2値により前記確率分布の移動量
及び分布形状の変化を制御する事により、自由に“1"確
率分布が設定できるようになり、集積回路の試験時間が
大幅に短縮される。
According to the present invention, it is possible to freely set the "1" probability distribution by controlling the movement amount and the change of the distribution shape of the probability distribution by the external binary value, and the integrated circuit test time is greatly shortened. It

例えば、ANDゲート,ORゲートを所定の割合で含む集積
回路に対しては、両者の比に応じて重み軸両端の出現確
率の比を算出して重み軸方向への移動量を設定して前記
比に応じたバランスを取り、次いで分布形状を2項分布
から凹状に変化させる事により両端夫々について出現確
率の大きさを設定してこれを極めて短時間でテストを終
了させるテストパターンを発生させる事ができる。
For example, for an integrated circuit that includes AND gates and OR gates at a predetermined ratio, the ratio of the appearance probabilities at both ends of the weight axis is calculated according to the ratio of the two, and the amount of movement in the weight axis direction is set to Balance according to the ratio, and then change the distribution shape from the binomial distribution to concave shape to set the magnitude of the appearance probability at each end and generate a test pattern that finishes the test in an extremely short time. You can

〔発明の実施例〕Example of Invention

以下、本発明の一実施例を図面を用いて詳細に説明す
る。
An embodiment of the present invention will be described in detail below with reference to the drawings.

装置の概要を説明すると、まず変換関数を用意し、こ
れをG1(X)と定義する。ここでは具体的に とする。
The outline of the apparatus will be described. First, a conversion function is prepared, and this is defined as G 1 (X). Here specifically And

ここで−1から1の間で一様乱数を発生させ、(1)
式により変換し、これをPとする即ち発生させた乱数を
γとすると、 となる。これが基準値となる。
Here, a uniform random number is generated between -1 and 1, and (1)
Converting by the formula, and letting it be P, that is, the generated random number is γ 0 , Becomes This is the reference value.

さらに、変換関数として を定義し用意する。(α,βは制御パラメータ後述) そして続けて一様乱数によってテストパターン列を発
生させる。テストパター列の要素の数が24として発生さ
せた乱数をγ〜γ24変換したパターン要素Q1〜Q24
すると、 となる。
Furthermore, as a conversion function Define and prepare. (Α and β are control parameters described later) Then, a test pattern sequence is generated by uniform random numbers. If the random numbers generated with the number of elements of the test pattern sequence being 24 are γ 1 to γ 24 converted pattern elements Q 1 to Q 24 , Becomes

次に(2)に依り、決定したPと(4)により、決定
したQ1〜Q24からテストパターンを発生する。その方法
は、発生するテストパターンをT1〜T24とすると、 と定義する。この手法に従って(1)〜(5)を繰り返
すことにより、次々とテストパターンを発生する。
Next, according to (2), the test pattern is generated from the determined Q 1 to Q 24 by the determined P and (4). The method is that if the generated test patterns are T 1 to T 24 , Is defined. By repeating (1) to (5) according to this method, test patterns are generated one after another.

ここで(3)式で出てきた、α,βについての補足説
明を行なう。まずαであるが、簡単にいえば、これは第
1図における横軸方向、即ち、“重み”における確率分
布の左,右への平行移動を制御するパラメータである。
このパラメータの役目は前述の一様な変化を担うもので
ある。第2図はそのαを第2図はβ=5.0としてα=1.0
(a),α=1.0(b)としたものである。変化させた
例である。これにより重み中心(“1"出現確率12回)に
対する左右のバランスが決まる。次にβであるがこれは
分布形状を変化させるパラメータである。第3図はその
βを変化させた例である。図はα=0.0の時、β=10.0
(a),β=0.1(b)としたものである第3図を見て
わかる通り、分布形状を変化させることにより確率分布
の中心(ピーク部)と、両端部との大小関係及びその比
が制御される。第4図は装置例を示す。第4図では一様
乱数発生装置10から基本入力として入力せしめられた一
様乱数群γ0…γ24と外部データ入力回路11から入
力された外部パラメータα,βが乱数分布変換装置12に
入力し、さらにまず入力したγは式(1)型の変換関
数装置13により又、γ〜γ24は式(3)型の変換関数
装置14より各々変換され出力される。この出力された系
列P,Q1,Q2…,Q24を、さらにテストパターン発生装置15
に入力し、式(5)型の変換により最終のテストパター
ンT1〜T24を発生する。
Here, a supplementary explanation will be given regarding α and β which have been expressed by the equation (3). First of all, α is a parameter for controlling the parallel shift of the probability distribution in the horizontal axis direction in FIG. 1, that is, the “weight”, to the left and right.
The role of this parameter is to carry out the above-mentioned uniform change. Fig. 2 shows that α is β = 5.0 and Fig. 2 is α = 1.0.
(A) and α = 1.0 (b). This is an example of changing. This determines the left-right balance with respect to the center of weight (12 occurrences of "1"). Next, β is a parameter that changes the distribution shape. FIG. 3 shows an example in which β is changed. In the figure, when α = 0.0, β = 10.0
As can be seen from Fig. 3 where (a) and β = 0.1 (b), the size relationship between the center (peak part) of the probability distribution and both ends by changing the distribution shape, and the ratio Is controlled. FIG. 4 shows an example of the apparatus. In FIG. 4, a uniform random number group γ 0 , γ 1 ... γ 24 input as basic inputs from the uniform random number generator 10 and external parameters α, β input from the external data input circuit 11 are random number distribution converters. type 12, further initially entered gamma 0 also the conversion function device 13 of the formula (1) type, gamma 1 to? 24 are output are respectively converted from the conversion function 14 of the formula (3) type. This output sequence P, Q 1 , Q 2 ..., Q 24 is further added to the test pattern generator 15
And the final test patterns T 1 to T 24 are generated by the conversion of the formula (5) type.

以上のフローチャートを第5図に示す。 The above flow chart is shown in FIG.

更に、テストパターンT1〜T24は被験回路16に入力さ
れる。PI1,PI2……,PInはその入力端子である。被験回
路がAND,ORゲートである場合には次の様にすれば良い。
Furthermore, the test patterns T 1 to T 24 are input to the test circuit 16. PI 1 , PI 2 ..., PIn are the input terminals. If the circuit under test is an AND, OR gate, do the following.

事前に2入力ANDゲートを説明すると、入力が“00",
“01",“10"の3パターンに対し出力は“0"となる。そ
して入力“11"のみ出力が“1"となる。即ち、3/4の確率
で出力“0"が現われる。又、2入力ORゲートの場合、逆
に入力“00"のみ出力が“1"となる。
Explaining the 2-input AND gate beforehand, the input is "00",
The output is "0" for the three patterns "01" and "10". And the output becomes "1" only for the input "11". That is, the output "0" appears with a probability of 3/4. In the case of a 2-input OR gate, on the contrary, only the input "00" outputs "1".

従って上記被検回路が主にAND系及びOR系の論理回路
から構成される場合、AND系とOR系の入力ピン比からα
を決定し、前入力ピンに対するAND系及びOR系の占有率
からβを決定する。そして第3図のβ=0.1の如き“1"
出現確率分布でテストパターンを発生させれば、被験回
路を効率よく試験する事ができ、極めて短時間で試験が
終了する。
Therefore, if the circuit under test is mainly composed of AND and OR logic circuits,
Is determined, and β is determined from the occupancy ratio of the AND system and the OR system with respect to the previous input pin. And "1" such as β = 0.1 in Fig. 3
If the test pattern is generated with the appearance probability distribution, the test circuit can be efficiently tested, and the test is completed in an extremely short time.

尚、本発明は上記実施例に限定される事なく、例えば
前記変換関数も種々のものを用いる事ができる。又、乱
数も、−1から1を数値として発生するものに限らず、
論理“1"をランダムな短時間隔で発生し、その時間間隔
を乱数に対応させるようにしても良い。
The present invention is not limited to the above embodiment, and various conversion functions can be used, for example. Also, the random numbers are not limited to those that generate -1 to 1 as numerical values,
The logic "1" may be generated at random short time intervals, and the time intervals may correspond to random numbers.

【図面の簡単な説明】[Brief description of drawings]

第1図は横軸は重み、縦軸は確率、パターン要素
(“1",“0"の総数)は24の一様乱数によって発生させ
たテストパターンの“重み”−確率分布曲線を示す図、
第2図はαのみを変化させ、発生させたテストパターン
の“重み”−確率分布曲線を示す図、第3図はβのみを
変化させた図、第4図は本発明の装置構成図、第5図は
本発明のフローチャート図である。
Fig. 1 shows the weight on the horizontal axis, the probability on the vertical axis, and the "weight" -probability distribution curve of the test pattern generated by 24 uniform random numbers for pattern elements (the total number of "1" s and "0" s). ,
FIG. 2 is a diagram showing a “weight” -probability distribution curve of a test pattern generated by changing only α, FIG. 3 is a diagram in which only β is changed, FIG. 4 is a device configuration diagram of the present invention, FIG. 5 is a flow chart of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】乱数発生装置と、所定の論理値の発生回数
及びその発生確率分布の包絡線形状とをパラメータとす
る変換関数に基づいて発生した乱数の分布を制御する乱
数分布変換装置と、この乱数分布に応じて特定の論理値
を所定の確率で出力するテストパターン発生装置とを備
え、前記2つのパラメータを変化させることにより前記
発生回数の中心値に対する前記発生確率分布の包絡線の
中心の移動及びその包絡線形状を制御したテストパター
ンを発生させ、集積回路に入力することを特徴とする集
積回路の試験方法。
1. A random number generator and a random number distribution converter for controlling the distribution of random numbers generated based on a conversion function having the number of occurrences of a predetermined logical value and the envelope shape of its occurrence probability distribution as parameters. A test pattern generator for outputting a specific logical value with a predetermined probability according to the random number distribution, and by changing the two parameters, the center of the envelope of the occurrence probability distribution with respect to the central value of the number of occurrences. Test method for an integrated circuit, which comprises generating a test pattern in which the movement of the pattern and its envelope shape are controlled and inputting the test pattern into the integrated circuit.
JP58109199A 1983-06-20 1983-06-20 Integrated circuit test method Expired - Lifetime JPH0833436B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58109199A JPH0833436B2 (en) 1983-06-20 1983-06-20 Integrated circuit test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58109199A JPH0833436B2 (en) 1983-06-20 1983-06-20 Integrated circuit test method

Publications (2)

Publication Number Publication Date
JPS601578A JPS601578A (en) 1985-01-07
JPH0833436B2 true JPH0833436B2 (en) 1996-03-29

Family

ID=14504123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58109199A Expired - Lifetime JPH0833436B2 (en) 1983-06-20 1983-06-20 Integrated circuit test method

Country Status (1)

Country Link
JP (1) JPH0833436B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0499671B1 (en) * 1991-02-21 1997-05-21 International Business Machines Corporation Integrated circuit chip with built-in self-test for logic fault detection
US5394405A (en) * 1992-04-24 1995-02-28 International Business Machines Corporation Universal weight generator
JP4228061B2 (en) 2000-12-07 2009-02-25 富士通マイクロエレクトロニクス株式会社 Integrated circuit test apparatus and test method
JP5179861B2 (en) * 2007-12-27 2013-04-10 株式会社日立製作所 Semiconductor device

Also Published As

Publication number Publication date
JPS601578A (en) 1985-01-07

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