JPS601578A - Tester for integrated circuit - Google Patents

Tester for integrated circuit

Info

Publication number
JPS601578A
JPS601578A JP58109199A JP10919983A JPS601578A JP S601578 A JPS601578 A JP S601578A JP 58109199 A JP58109199 A JP 58109199A JP 10919983 A JP10919983 A JP 10919983A JP S601578 A JPS601578 A JP S601578A
Authority
JP
Japan
Prior art keywords
random number
distribution
test
probability
test pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58109199A
Other languages
Japanese (ja)
Other versions
JPH0833436B2 (en
Inventor
Akimitsu Tateishi
立石 昭光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58109199A priority Critical patent/JPH0833436B2/en
Publication of JPS601578A publication Critical patent/JPS601578A/en
Publication of JPH0833436B2 publication Critical patent/JPH0833436B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]

Abstract

PURPOSE:To test an integrated circuit easily and quickly with free control of the weight or the like of a test pattern by controlling a random number distribution converter for controlling the random number responding to a random number generator with an external binary digit. CONSTITUTION:The distribution of a uniform random number of a fundamental input from a uniform random number generator 10 is controlled with a random number distribution converter 12 according to binary digits alpha and beta from an external unit 11. With the value alpha, the right and left movement of the probability distribution varies with a conversion function unit 13 of an equipment 12 to determine the right and left balance with respect to the weight center while with the value beta, the geometry of the distribution changes through a conversion function unit 14 to control the ratio of magnitude between the center peak of the probability distribution and both ends thereof. A test pattern is outputted from a test pattern generator 15 responding to the equipment 12 to test a 2 input AND gate with the probability of 3/4 for the appearance of 0, for instance, by a pattern of the corresponding appearance probability thereby enable the testing of an integrated circuit easily and quickly.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明はLSI等に試験用として適用可能な集積回路試
験装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an integrated circuit testing device applicable to testing LSIs and the like.

〔従来技術とその問題点〕[Prior art and its problems]

従来、種々のテストパターン発生装置が考案されている
が乱数入力の発生装置においては、発生乱数をそのまま
入力、又は一様な変換により、テストパターンとして発
生させる装置が主に提案されている。例えば24人力の
回路の:l易合舌り数をAD変換しテストパターンとし
て発生させた場合、−組24個の11“又は′O“が、
一つのテストノくターンとして形成される。そこで、そ
の−組中のTL 1 //の数(以後1重み“と略す)
を横軸にとり、その1屯み“に対応する発生確率金1縦
帽にとり、一様乱数発生装置により、3000組のテス
トノ(ターンを発生させた場合の分布金第11閾に示す
Conventionally, various test pattern generation devices have been devised, but among random number input generation devices, devices that generate test patterns by inputting generated random numbers as they are or by uniformly converting them have been mainly proposed. For example, if the :l easy matching number of 24 human-powered circuits is AD converted and generated as a test pattern, 24 - sets of 11" or 'O" will be
It is formed as one test turn. Therefore, the number of TL 1 // in the - set (hereinafter abbreviated as "1 weight")
is plotted on the horizontal axis, and the probability of occurrence corresponding to that 1 turn is plotted in 1 vertical column.The distribution of 3000 sets of test turns is shown in the 11th threshold using a uniform random number generator.

図より、へ力が一様乱数である限り、その分布は2項分
布になる事がわかる。
From the figure, it can be seen that as long as the force is a uniform random number, its distribution becomes a binomial distribution.

又、一様な変換すなわちV″1″*0/lの出現6;’
+f率を単に変化させた場合は、第1図の分布金横東り
方向に移動させた分布に他ならな(,1゜しかしながら
以上の方式ではその′l工み“の分布が2項分布である
為、できるだけ少な(1)テストパターンを発生させて
試験する場合、種々の重みのパターンを発生させたくて
も、確率分XUとして限定させたパターンでは、発生し
に(し)1勿75;多1.)。
Also, the uniform transformation, ie the appearance of V″1″*0/l6;'
If the +f ratio is simply changed, the distribution shown in Figure 1 is nothing but the distribution shifted horizontally to the east (1 degree). However, in the above method, the 'l' distribution becomes a binomial distribution. Therefore, when testing by generating as few (1) test patterns as possible, even if you want to generate patterns with various weights, the patterns limited to the probability portion XU will not occur (1). ; Many 1.).

例えば10′′が20個、′1“が4〈固のテストノく
ターンは2項分布で発生した場合、約0.03%の確率
、すなわち、1万バダーンに3回の割合で出現するにす
ぎない。
For example, if there are 20 10'' and 4 ``1'' test turns, the probability is approximately 0.03%, that is, they will appear 3 times in 10,000 badans. Only.

さらに一様な変換を加えた場合においても、平行移動さ
せた逆方向の′重み“につぃては、同様の事が言え、入
力数が増すにつれこの傾向は顕著となる。例えばAND
ゲートとORゲートにより構成、かつその比が異なる場
合には従来は全く適用できない。
Even when further uniform transformation is applied, the same thing can be said for the 'weights' in the opposite direction that are translated in parallel, and this tendency becomes more pronounced as the number of inputs increases.For example, AND
The conventional method cannot be applied at all when the structure is composed of a gate and an OR gate and the ratios thereof are different.

〔発明の目的〕[Purpose of the invention]

本発明はこの点を考Hし、回路データ等外部データによ
、す、テストパターンの重みを自由に制御・し集積回路
の試験を容易にする事を目的とするものである。
The present invention takes this point into consideration and aims to facilitate testing of integrated circuits by freely controlling the weights of test patterns using external data such as circuit data.

〔発明の概要〕[Summary of the invention]

本発明は、一様乱数発生装置の後段に発生した乱数の分
布を制御する乱数分布変換装置を設け、更にこの乱数分
布に応じて特定の論理値を所定の確率で出力するテスト
パターン発生装置を設け、外部2値により前記論理値の
出現確率分布の重み軸方向への移動及びその形状変化が
制御されるよ〔発明の効果〕 本発明によれば外部2値によフ前記羅率分布の移動量及
び分布形状の変化全制御する事により、自由に′1″確
率分布が設定できるようになり、集積回路の試験時間が
大幅に短縮される。
The present invention provides a random number distribution conversion device that controls the distribution of random numbers generated after a uniform random number generator, and further includes a test pattern generator that outputs a specific logical value with a predetermined probability according to this random number distribution. According to the present invention, the external binary values control the movement of the appearance probability distribution of the logical values in the weight axis direction and the change in shape thereof. [Effects of the Invention] According to the present invention, the external binary values By fully controlling the amount of movement and changes in the distribution shape, it becomes possible to freely set the ``1'' probability distribution, and the test time for integrated circuits is greatly shortened.

例えば、ANDゲー1− 、 ORゲートy、所定の割
合で含む集積回路に対しては、両者の比に応じて沖、み
軸側端の出現確率の比を算出して重み軸方向への移動量
を設定して前記比に応じたバランスを取、す、次いで分
布形状を2項分布から凹状に変化させる事によシ両端夫
々について出現確率の大きさを設定してこれ’t−極め
て短時間でテストを終了させるテストパターンを発生さ
せる事ができる。
For example, for an integrated circuit that includes an AND gate 1 and an OR gate y at a predetermined ratio, the ratio of the appearance probabilities of the edges on the axis is calculated according to the ratio of the two, and the shift in the weight axis direction is performed. The quantity is set to achieve a balance according to the ratio, and then by changing the distribution shape from a binomial distribution to a concave shape, the size of the appearance probability is set at each end, and this is extremely short. It is possible to generate a test pattern that completes the test in time.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面を用いて詳細に説明する
Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

装置の概要を説明すると、まず変換関数を用意し、これ
k G t (xi と定義する。ここでは具体的にQ
 1 (xl−tan 二X ・・・・・・・・・・・
・(1)とする。
To explain the outline of the device, first, a conversion function is prepared, and this is defined as k G t (xi. Here, specifically, Q
1 (xl-tan 2X ・・・・・・・・・・・・
・Set as (1).

ここで−1から1の間で一様乱数ヲ発生させ、(11式
によシ変換し、これ’tPとする即ち発生させた乱数を
fo・とすると、 P = tan−γ。 ・・・・・・・・・・・・・・
・(2)となる。これが茄準値となる。
Here, a uniform random number between -1 and 1 is generated and transformed according to equation 11, and if this is 'tP, that is, the generated random number is fo, then P = tan-γ.・・・・・・・・・・・・
・(2) becomes. This is the standard value.

さらに変換関数として G 鵞(xi = α+β tan −x ・・・・・
・・・・・・・・・・ [31を定催し用意する。(α
、βは制御パラメータ後述) そして続けて一様乱数によってテストパターン列を発生
させる。テストパターン列の要素の数が24として発生
させた乱数全γ、〜γ24変換したパターン要素Q、〜
Q24 とすると、 Qk =α十βtan−;rk(k = 1 、2、−
・・24)”−・441となる。
Furthermore, as a conversion function, G (xi = α+β tan −x...
・・・・・・・・・ [31 will be held regularly and prepared. (α
, β are control parameters described below) Then, a test pattern sequence is generated using uniform random numbers. All random numbers γ generated assuming that the number of elements in the test pattern sequence is 24, ~γ24-converted pattern element Q, ~
Q24, then Qk = α + β tan -; rk (k = 1, 2, -
...24)"--441.

仄に(2)に依ジ、決定したPと(4)により、決定し
たQ、〜Q24 からテストパターンを発生する。その
方法は、発生するテストパターンをT、〜T24とする
と、 と定義する。この手法に従って(1)〜(5)ヲ繰り返
すことにより、次々とテストパターンを発生する。
Depending on (2), a test pattern is generated from the determined P and (4) determined Q, ~Q24. The method is defined as follows, where the generated test pattern is T, ~T24. By repeating steps (1) to (5) according to this method, test patterns are generated one after another.

ここで(3)式で出てきた、α、βについての補足説明
を行なう。kずαであるが、簡単にいえば、これは第1
図における横軸方向、即ち、1重み′における確率分布
の左、右への平行移l1TtIヲ制御するパラメータで
ある。このパラメータの役目は前述の一様な変化を担う
ものである。第2図はそのαを第2図t・tβ=5.0
としてα= 1. O(at 、α=−1,0(blと
したものである。変化させた例である。これにより重み
中心(″IN出現確率12回)に対する左右のバランス
が決まる。次にβであるがごれは分布形状全変化させる
パラメータである。第3図はそのβを変化させた例であ
る。図はα=0.0の時、β−10,0(at 、β=
 o、 i tb+としたものである第3図を見てわか
る通り、分布形状全変化させることにより確率分布の中
心(ピーク部)と、両端部との大小関係及びその比が制
御される。第4図は装置例を示す。第4図では一様乱数
発生装置lOから基本人力として入力せしめられた一様
乱数群γ。、γ1・・・γ1.と外部データ入力回路1
1から入力された外部パラメータα、βが乱数分布変!
装置tTt12に入力し、さらにまず入力しだγ。は式
fil型の変換関数装置13により又srl〜γ24は
式(3)型の変4典関数装置14により各々変換され出
力される。この出力された系列P 、Qt −Qt、・
・・、Q□金、さらにテストパターン発生装置15に入
力し、式(5)型の変換によ、り最終のテストパターン
T、〜T、、’を発生する。
Here, a supplementary explanation will be given regarding α and β that appeared in equation (3). kzuα, but to put it simply, this is the first
This is a parameter that controls the horizontal axis direction in the figure, that is, the parallel shift l1TtI to the left and right of the probability distribution at 1 weight'. The role of this parameter is to carry out the uniform change described above. Figure 2 shows that α as Figure 2 t・tβ=5.0
As α=1. O(at, α=-1,0 (bl). This is an example of changing. This determines the left and right balance with respect to the weight center ("IN appearance probability 12 times). Next, β Dirt is a parameter that changes the entire distribution shape. Figure 3 shows an example of changing β. The figure shows that when α = 0.0, β - 10,0 (at, β =
o, i tb+ As can be seen from FIG. 3, by completely changing the distribution shape, the magnitude relationship between the center (peak portion) and both ends of the probability distribution and the ratio thereof are controlled. FIG. 4 shows an example of the device. In FIG. 4, a uniform random number group γ is input as basic human input from a uniform random number generator IO. , γ1...γ1. and external data input circuit 1
The external parameters α and β input from 1 are random number distribution changes!
Input it into the device tTt12, and then first input γ. are converted and outputted by the conversion function device 13 of the formula fil type, and srl to γ24 are respectively converted by the inflection function device 14 of the formula (3) type. This output sequence P , Qt −Qt,・
. . , Q□F are further input to the test pattern generator 15, and the final test patterns T, ˜T, , ' are generated by conversion of the equation (5) type.

以上のフローチャート全第5図に示す。The entire flowchart described above is shown in FIG.

更に、テストパターンT1〜T24は被験回路16に入
力される。PI、、PI、・・・・・・、PInはその
入力端子である。被験回路がAND 、ORゲートであ
る場合には次の様にすれば良い。
Furthermore, test patterns T1 to T24 are input to the circuit under test 16. PI, PI, . . . , PIn are its input terminals. If the circuit under test is an AND or OR gate, the following procedure may be used.

事前に2人力ANDゲートを説明すると、入力が’00
′′、’01”、10″の3パターンに対し出力はゝ0
“となる。ぞして入力′ll′のみ出力が′1“となる
。即ち、3/4 の確率で出力″″0″が現われる。又
、2人力ORゲートの場合、逆に入力′00”のみ出力
が11“となる。
If you explain the two-man AND gate in advance, the input will be '00'.
The output is 0 for the 3 patterns of '', '01'', and 10''.
Therefore, the output of only the input 'll' becomes '1'. That is, the output ``0'' appears with a probability of 3/4. In the case of a two-man OR gate, conversely, only the input ``00'' results in an output 11''.

従って上記被験回路が主にAND系及びOR系の論理回
路から構成される場合、AND系とOR系の入力ピン比
からαを決定し、全入力ビンに対するNND系及びOR
系の占有率からβを決定する。そして第3図のβ=0.
lの如き11′出現確率分布でテストパターンを7発生
させれば、被験回路を効率よく試験する事ができ、極め
て短時間で試験が終了する。
Therefore, if the circuit under test is mainly composed of AND system and OR system logic circuits, α is determined from the input pin ratio of AND system and OR system, and NND system and OR system for all input bins are determined.
Determine β from the system occupancy. And β=0 in Fig. 3.
If seven test patterns are generated with an 11' appearance probability distribution such as 1, the circuit under test can be efficiently tested and the test can be completed in an extremely short time.

尚、本発明は上記実施例に限定される事なく、例えば前
記変換関数も種々のもの金柑いる事ができる。又、乱数
も、−’Iから1全数値として発生するものに限らず、
論理’x’wランダムな時゛間間隔で発生し、その時間
間隔を乱数に対応させるようにしても良い。
It should be noted that the present invention is not limited to the above-mentioned embodiments, and various types of conversion functions may be used, for example. In addition, random numbers are not limited to those generated as a complete number of 1 from -'I,
The logic 'x'w may be generated at random time intervals, and the time intervals may be made to correspond to random numbers.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は横軸は重み、縦軸は確率、パターン要素(11
′′、′0“の総数)は24の一様乱数によって発生さ
せたテストパターンの′重み“−確率分布曲線を示す図
、第2図はαのみを変化させ、発生させたテストパター
ンの1京み“−確率分布曲i’i?J k示す図、第3
図はβのみを変化させた図、第4図は本発明の装置構成
図、第5図は本発明のフローチャート図である。 代理人弁理士 則 近 憲 佑(ほか1名)第8図 →會す 第4図
In Figure 1, the horizontal axis is the weight, the vertical axis is the probability, and the pattern elements (11
``, total number of ``0'') is a diagram showing the ``weight''-probability distribution curve of the test pattern generated by 24 uniform random numbers. Figure 2 shows the ``weight'' - probability distribution curve of the test pattern generated by changing only α. Kyomi "-probability distribution song i'i?J k diagram, 3rd
The figure is a diagram in which only β is changed, FIG. 4 is a configuration diagram of an apparatus according to the present invention, and FIG. 5 is a flowchart diagram of the present invention. Representative Patent Attorney Noriyuki Chika (and 1 other person) Figure 8 → Meeting Figure 4

Claims (1)

【特許請求の範囲】[Claims] 乱数発生装置と、発生した乱数の分布を制御する乱数分
布変換装置と、この乱数分布に応じて特定の論理値を所
定の確率で出力するテストパターン発生装置とを備え、
外部2値により前記論理値の出現確率分布の重み軸方向
への移動及びその形状変化全制御する様にした事を特徴
とする集積回路試験装置。
A random number generation device, a random number distribution conversion device that controls the distribution of the generated random numbers, and a test pattern generation device that outputs a specific logical value with a predetermined probability according to the random number distribution,
An integrated circuit testing device characterized in that the movement of the appearance probability distribution of the logical value in the weight axis direction and the shape change thereof are completely controlled by external binary values.
JP58109199A 1983-06-20 1983-06-20 Integrated circuit test method Expired - Lifetime JPH0833436B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58109199A JPH0833436B2 (en) 1983-06-20 1983-06-20 Integrated circuit test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58109199A JPH0833436B2 (en) 1983-06-20 1983-06-20 Integrated circuit test method

Publications (2)

Publication Number Publication Date
JPS601578A true JPS601578A (en) 1985-01-07
JPH0833436B2 JPH0833436B2 (en) 1996-03-29

Family

ID=14504123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58109199A Expired - Lifetime JPH0833436B2 (en) 1983-06-20 1983-06-20 Integrated circuit test method

Country Status (1)

Country Link
JP (1) JPH0833436B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239262A (en) * 1991-02-21 1993-08-24 International Business Machines Corporation Integrated circuit chip with built-in self-test for logic fault detection
JPH0682528A (en) * 1992-04-24 1994-03-22 Internatl Business Mach Corp <Ibm> Circuit for generating binary sequence having controllable weight
JP2009156761A (en) * 2007-12-27 2009-07-16 Hitachi Ltd Semiconductor device
US7734973B2 (en) 2000-12-07 2010-06-08 Fujitsu Microelectronics Limited Testing apparatus and testing method for an integrated circuit, and integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239262A (en) * 1991-02-21 1993-08-24 International Business Machines Corporation Integrated circuit chip with built-in self-test for logic fault detection
JPH0682528A (en) * 1992-04-24 1994-03-22 Internatl Business Mach Corp <Ibm> Circuit for generating binary sequence having controllable weight
US7734973B2 (en) 2000-12-07 2010-06-08 Fujitsu Microelectronics Limited Testing apparatus and testing method for an integrated circuit, and integrated circuit
JP2009156761A (en) * 2007-12-27 2009-07-16 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH0833436B2 (en) 1996-03-29

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