JPH08331886A - Motor driver - Google Patents

Abstract

PURPOSE: To detect the abnormalities of Hall elements securely by a simple circuit. CONSTITUTION: The outputs of three-phase Hall elements H1, H2 and H3 are converted into signals A1, A2 and A3 whose levels are H or L by Hall amplifiers 12, 14 and 16. The H's and/or L's of the signals A1, A2 and A3 are supplied to a Hall element abnormality detection unit 30 through a logic unit 20. As the phases of the output waveforms of the three-phase Hall elements are different from each other by 120 deg., if the signals A1, A2 and A3 show H, H and H or L, L and L, the abnormalities of the Hall elements can be detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor drive circuit for controlling a motor drive current according to signals from three-phase Hall elements.

[0002]

2. Description of the Related Art Conventionally, a three-phase brushless motor using a hall element has been used as a fan motor or the like. In this three-phase brushless motor, the position of the rotor is detected by a three-phase Hall element that outputs AC signals having phases different from each other by 120 °, and the motor drive current is supplied to the stator coil according to the output of the three-phase Hall element. Control.

In such a motor, if the hall element fails, the detection signal becomes abnormal. Therefore, the control of the motor drive current according to the detection signal is hindered, and desired rotation cannot be performed. Therefore, it is preferable to detect the failure of the Hall element. Usually, the failure detection of the Hall element is performed by comparing the output from the separately provided rotation detection unit with the output from each Hall element.

[0004]

However, if a circuit is provided for each output of each Hall element, the circuit becomes large accordingly. Therefore, it has been desired to detect the abnormality of the Hall element with a simpler circuit.

The present invention has been made in view of the above problems, and an object thereof is to provide a motor drive circuit capable of detecting an abnormality of a Hall element with a simple circuit.

[0006]

SUMMARY OF THE INVENTION The present invention provides 120 to each other.
A motor drive circuit that controls a motor drive current in accordance with signals from three-phase Hall elements that output AC signals having different phases, wherein the signal levels of the output signals from the three-phase Hall elements are binary. A binarization unit that digitizes, and an abnormality detection unit that detects an abnormality by logical operation of the output of the binarization circuit,
It is characterized by having.

A low-pass filter circuit that integrates the output of the abnormality detection unit to remove noise by charging and discharging the capacitor, and a latch circuit that latches the output of this low-pass filter circuit and outputs an abnormality signal are provided. It is characterized by further having.

Further, the present invention is a motor drive circuit for controlling a motor drive current in accordance with a signal from a three-phase Hall element that outputs alternating current signals whose phases are different from each other by 120 °. A binarization unit that binarizes the signal level of the output signal from the element, an abnormality detection unit that detects an abnormality by the logical operation of the output of the binarization circuit, and a rotation corresponding to the output signal from the Hall element. A rotation detection unit that generates a charging / discharging current to the capacitor in response to the pulse and that detects that the number of rotations of the motor has dropped below a predetermined value depending on the charging / discharging state of the capacitor, and the abnormality detection unit The above-mentioned capacitor is charged and discharged in accordance with the output abnormality detection signal, so that the rotation detector detects a decrease in the rotation speed of the motor and an abnormality in the hall element. .

[0009]

As described above, according to the present invention, the signal is binarized from the three-phase Hall element in the binarizing unit. Then, the abnormality detection unit detects the abnormality by the logical operation of the output of the binarization unit.

The output from the abnormality detecting section is filtered by a low-pass filter circuit to remove noise, and this output is latched by a latch circuit.

Further, according to the present invention, in the rotation detecting section, a capacitor charged and discharged according to the rotation pulse is used to detect a decrease in the motor rotation speed, and the capacitor detects the abnormality detection signal from the abnormality detecting section. Filter the output.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the configuration of the first embodiment, in which a motor drive circuit is formed in one semiconductor integrated circuit (IC) 100. The motor M is provided with three Hall elements H1, H2, H3 in order to detect the position of its rotor. In the figure, Hall elements H1, H2, H3 are motor M
Although it is shown as separated from, it is actually provided in the motor M. Then, in the Hall elements H1, H2, H3, as shown in FIG.
The Hall output waveform of the phase is obtained. Here, Hall element H
The output of 1 is IN1, the output of the hall element H2 is IN2, the output of the hall element H3 is IN3, and these IN1, I
N2 and IN3 are Hall elements H1, H2 and H3, respectively.
Of the voltage between both ends (difference between INn + and INn−: n = 1,
2, 3).

The three Hall elements H1, H2, H3 are
Hall amplifiers 12, 14, and 16 in the IC 100 are connected to each other. This hall amplifier 12, 14, 16
Are outputs IN1 and IN of the Hall elements H1, H2, and H3.
2 and IN3 are amplified with a large gain and binarized. That is, when the outputs IN1, IN2, IN3 are positive, H is output, and when they are negative, L is output. In addition, hall amplifier 1
The outputs of 2, 14, and 16 are A1, A2, and A3, respectively.

The output sides of the Hall amplifiers 12, 14 and 16 are connected to the logic section 20.
Are supplied with signals A1, A2, A3. Logic part 20
An output unit 22 is connected to the output terminal 22, and a motor M outside the IC 100 is connected to the output unit 22. The output unit 22 has a plurality of output transistors built therein. By turning the output transistors ON and OFF, the field current in the motor M is controlled according to the rotor position of the motor M to rotate the rotor. That is, the logic unit 20
Detects the rotor position according to the statuses of H and L of the supplied signals A1, A2, A3, and outputs the output unit 22 accordingly.
The ON / OFF of the output transistor of is controlled to control the field current so that a rotational force is generated in the rotor.

Here, in this embodiment, the hall element abnormality detecting section 30 is connected to the logic section 20, and the hall element H is detected depending on the state of the signal in the logic section 20.
Detect an abnormality of 1, H2, H3. That is, the outputs A1, A2, A3 of the Hall amplifiers 12, 14, 16 are as shown in FIG.
As shown in, the phase shifts by 120 ° and H and L respectively.
repeat. Therefore, the binarized signals A1, A2,
As shown in FIG. 4, all of A3 are never H or L. Therefore, the hall element abnormality detection unit 30
Determines the state of H or L of the signals A1, A2, A3, detects that all of them are H or L, and detects an abnormality of the Hall elements H1, H2, H3.

A low-pass filter 32 is connected to the Hall element abnormality detecting section 30. The low-pass filter 32 removes noise in the output of the Hall element abnormality detecting section 30. That is, in the low-pass filter 32,
A capacitor C outside the IC 100 is connected and integrates the output of the Hall element abnormality detection unit 30. As a result, the instantaneous H in the output of the Hall element detector 30 is removed.

A latch 34 is connected to the low-pass filter 32, and when the signal passed through the low-pass filter 32 is H, it holds information that the Hall element is abnormal. Then, the output regarding the abnormality of the Hall element appears at the terminal 36. In addition, the hall element abnormality detection unit 34 receives signals A1, A2, A through the logic unit 20.
Although 3 is accepted, it may be accepted directly without going through the logic unit 20.

As described above, according to the present embodiment, the Hall element abnormality detecting section 30 performs the logical operation of the output signals of the Hall amplifiers 12, 14, 16 to determine the Hall elements H1, H2, H.
Detect 3 abnormalities. Therefore, the circuit is very simple and reliable detection can be performed. When an abnormality is detected, the detection signal (appears at the terminal 36) is used to stop the power supply to the motor M or display that the hall element is abnormal.

[Structure of Logic Unit 20] FIG. 5 shows the structure of the logic unit 20. Transistors Q1, Q2, Q5, Q6, Q9, Q are connected to the power supply (5V) through resistors, respectively.
Ten emitters are connected. The bases of the transistors Q1 and Q2 are connected to each other, and the transistor Q1
5, the bases of Q6 are connected to each other, and the transistors Q9,
The bases of Q10 are connected to each other. Further, the bases and collectors of the transistors Q2, Q6, and Q10 are short-circuited. Therefore, these transistors Q1 and Q
Two current mirror circuits are constituted by 2, Q5, Q6, Q9 and Q10. Therefore, a current corresponding to the current flowing through the transistor Q2 is output from the collector of the transistor Q1, a current corresponding to the current flowing through the transistor Q6 is output from the collector of the transistor Q5, and a current corresponding to the current flowing through the transistor Q10 is generated. It is output from the collector of Q9. The collectors of the transistors Q1, Q5, Q9 are connected to the output section 22. Therefore, these transistors Q
The outputs of 1, Q2 and Q3 are supplied to the output unit 22.

The collector of the transistor Q2 is connected to the collectors of the transistor Q3 and the transistor Q8. The collector of the transistor Q6 is connected to the collectors of the transistor Q7 and the transistor Q12. Further, the collector of the transistor Q10 is connected to the collectors of the transistor Q4 and the transistor Q11. The emitters of the transistors Q3 and Q4 are connected to the ground via the constant current source I1.
The emitters of the transistors Q7 and Q8 are the constant current source I2.
Is connected to the ground through the transistor Q11 and Q
The 12 emitters are connected to ground via a constant current source I3.

Then, the transistors Q3, Q7, Q11
A predetermined reference voltage Vref is input to the base of the transistor Q4, a signal A3 is input to the base of the transistor Q4, a signal A2 is input to the base of the transistor Q8, and a signal A1 is input to the base of the transistor Q12. There is.
The common base of the transistors Q1 and Q2, the common base of the transistors Q5 and Q6, and the transistor Q
The common base of 9 and Q10 is the Hall element abnormality detection unit 30.
The state of these bases is input to the Hall element abnormality detection unit 30. The transistor Q1,
Q2, Q5, Q6, Q9 and Q10 are PNP type,
Transistors Q3, Q4, Q7, Q8, Q11, Q12
Is an NPN type.

In such a circuit, when the signal A1 is H, the transistor Q12 is turned on, which causes a current to flow in the transistor Q6. Therefore, a predetermined output current flows from the transistor Q5 to the output unit 22, the common base of the transistors Q5 and Q6 becomes L, and S2 becomes L. Similarly, when the signal A2 is H, the transistor Q8 is turned on, this current flows through the transistors Q2 and Q1, and S3 becomes L. Further, when the signal A3 is H, the transistor Q4 is turned on,
A current flows through the transistors Q10 and Q9, and S1 becomes L. Therefore, when the signals A1, A2 and A3 are all H, the outputs S1, S2 and S3 are all L.

On the other hand, when the signal A1 is L, the transistor Q11 is turned on, a current flows through the transistor Q10, and S1 becomes L. Similarly, when the signal A2 is L, current flows through the transistor Q7 and current flows through the transistor Q6, and S2 becomes L. Further, if the signal A3 is L, a current flows through the transistor Q3 and a current also flows through the transistor Q2, and S3 becomes L. Therefore, the signals A1, A2,
Even when all of A3 are L, S1, S2, and S3 are all L.

The signals A1, A2 and A3 are all H,
Or if all are not L, transistors Q2, Q
Any one of 6 and Q10 passes a current of 2I, and any one transistor is turned off. Therefore, in this state, any one of S1, S2, and S3 becomes H.

Therefore, when all of the signals A1, A2, A3 become H or L due to the failure of the Hall element,
All of the transistors Q2, Q6 and Q10 carry the current I, and all of S1, S2 and S3 become L. Therefore, in the logic unit 20, the state in which the signals A1, A2 and A3 are all H or all L is converted into the signal in which S1, S2 and S3 are all L.

[Configuration of Hall Element Abnormality Detection Unit 30] Next, FIG. 6 shows the configuration of the Hall element abnormality detection unit 30. The emitter of the transistor Q13 is connected to the power supply (5V) via a resistor, and the collector of the transistor Q13 is connected to the ground via the resistor. The base of the transistor Q14 is connected to the collector of the transistor Q13, the collector of the transistor Q14 is connected to the power supply via a resistor, and the emitter thereof is connected to the ground. The base of the transistor Q15 is connected to the collector of the transistor Q14, and the collector of the transistor Q15 is connected to the base of the output transistor Q22. The output S3 of the logic section 20 is supplied to the base of the transistor Q13. Similarly, a transistor Q16 having an emitter connected to a power source via a resistor and a collector connected to the ground via a resistor,
The transistor Q16 has a collector connected to the base, a collector connected to a power source via a resistor, and an emitter connected to the ground, and a transistor Q17 having a collector connected to the base and an emitter connected to the ground. The output S2 is supplied to the base of the transistor Q16, and the collector of the transistor Q18 is connected to the base of the transistor Q22. Further, Q19, Q20, and Q21 having the same configuration are provided, the output S1 is supplied to the base of Q19, and the collector of the transistor Q21 is connected to the base of the output transistor Q22. The base of the transistor Q22 is connected to the power supply via the resistor R. The transistors Q13, Q16, Q19 are of PNP type, and the transistors Q14, Q15, Q17, Q18, Q20,
Q21 and Q22 are NPN type.

In such a circuit, when the output S3 is L, the transistor Q13 is turned on, which turns on the transistor Q14 and turns off the transistor Q15. On the other hand, if the signal S3 is H, the transistor Q1
3 turns off, the transistor Q14 also turns off, and the transistor Q15 turns on. Similarly, when S2 is L, the transistor Q18 is OFF, when S2 is H, the transistor Q18 is ON, when signal S1 is L, the transistor Q21 is OFF, and when signal S1 is H, the transistor Q21 is ON. To do.

The transistors Q15, Q18, Q
If any one of them is turned on, the transistor Q22 is turned off. Also, the transistor Q1
If any one of 5, Q18 and Q21 is ON, the resistance R
A current flows through the transistor Q22 and the base of the transistor Q22 becomes L, so the transistor Q22 is OFF. However, when all of the outputs S1, S2, S3 are L,
All the transistors Q15, Q18 and Q21 are turned off, the base of the transistor Q22 is set to H, and this transistor Q22 is turned on.

As described above, the output S of the logic unit 20
All of 1, S2 and S3 become L because signals A1 and A
This is the case where 2, A3 all become H or all L, that is, when any of the Hall elements H1, H2, H3 fails. Therefore, in the Hall element abnormality detection unit 30, when the Hall element fails, the transistor Q22 is turned on.

"Low-pass filter 32 and latch 34
Next, FIG. 7 shows the configurations of the low-pass filter 32 and the latch 34. The latch 34 has two resistors and an NP.
It is composed of an N-type transistor Q23 and an external capacitor C. The base of the transistor Q23 is connected to the power supply via a resistor, and the collector of the transistor Q23 is connected to the power supply via another resistor. Further, the emitter of the transistor Q23 is connected to the ground. The collector of the transistor Q23 is connected to the capacitor C. The other end of the capacitor C is connected to the ground. The collector of the transistor Q22, which is the output of the Hall element abnormality detection unit 30, is connected to the base of the transistor Q23, and the collector of the transistor Q23 is the output.

In this circuit, when the transistor Q22 is turned on, the base of the transistor Q23 is L.
And this transistor Q23 turns off. As a result, the charging current flows through the capacitor C1 through the resistor,
The collector voltage of the transistor Q23 rises. Therefore, the collector of the transistor Q23 has a sufficiently high voltage only when the output transistor Q22 of the Hall element abnormality detecting section 30 is turned on for a predetermined time or longer.

The latch circuit 34 includes five resistors, three NPN type transistors Q24, Q25 and Q26, and two resistors.
It consists of two diodes D1 and D2. The output of the filter circuit 32 is supplied to the base of a transistor Q24, the emitter of the transistor Q24 is connected to the ground, and the collector is connected to the power supply via a resistor. The collector of the transistor Q24 is connected to the collector of a transistor Q25 whose emitter is connected to the ground, and the base of a transistor Q26 whose emitter is connected to the ground is connected via a resistor. The base of the transistor Q25 is connected to the collector of the transistor Q26 via a resistor. Further, the collector of the transistor Q26 has a resistor and a transistor Q26.
It is connected to the power supply via two series-connected diodes D1 and D2 that allow a current to flow toward 26. The collector of the transistor Q26 is connected to the base of the output transistor Q28 via a resistor, and the transistor Q2
The emitter of 8 is connected to the ground, and the collector is the output of the latch. Therefore, the transistor Q24
If it is FF, the transistor Q26 turns on,
The transistor Q25 is OFF, the base of the transistor Q28 is L, and the transistor Q28 is OFF. On the other hand, when the transistor Q24 turns on, the transistor Q26 turns off and the transistor Q25 turns off.
N. As a result, the base of the transistor Q28 becomes H and the transistor Q28 is turned on. And
Even when the transistor Q24 is turned off,
Since the transistor Q25 is ON, the base of the transistor Q26 is L and the transistor Q28 is ON.
It will remain. Therefore, when the transistor Q24 is turned on, the latch that turns on the transistor Q28 functions. In the initial state, since the capacitor C1 is not charged, the transistor Q24 is always OFF and the transistor Q28 is OFF.

As described above, according to this embodiment, the output signals A1, A2, A of the Hall amplifiers H1, H2, H3 are obtained.
When any of 3 becomes H or L, this can be detected to obtain a signal regarding abnormality in the latch output. In addition, in this embodiment, since the outputs S1, S2, and S3 are obtained by using a part of the circuit in the logic unit 20, the configuration of the Hall element abnormality detection unit 30 can be further simplified.

[Second Embodiment] FIG. 8 shows the structure of the second embodiment. The filter 32 and the latch 3 of the first embodiment are shown in FIG.
Instead of 4, the rotation detection circuit 40 is provided. The other structure is the same as that of the first embodiment.

This rotation detection circuit 40 is used in the hall amplifier 1
6 is a circuit for detecting the rotation state of the motor from the state of A3 which is the output signal of 6. That is, when the signal A3 repeats H and L, it is determined to be normal, but the signal A3 is H.
Alternatively, it is detected when it is fixed to one of L, that is, when it is not rotated. Further, a condenser is also required when detecting this non-rotation state. In this embodiment, the rotation detection circuit 40 filters the output of the Hall element abnormality detection unit 30.
It is also used by the capacitor C2. Therefore, one of the external capacitors can be omitted, and the number of terminals of the IC 100 can be reduced by one.

[Structure of Rotation Detecting Section 40] FIG. 9 shows the circuit structure of the rotation detecting circuit 40. The collector of the transistor Q66 to which the rotation pulse, that is, the output signal A3 of the Hall amplifier 16 is input is connected to the power supply via the resistor R1, and the emitter is connected to the ground.
The collector of the transistor Q66 is connected via a resistor R3 to the base of a PNP transistor Q51 whose emitter is connected to the power supply. The collector of the transistor Q51 is connected to the ground via the constant current source I51. The collector of the transistor Q51 is connected to the base of the transistor Q52 whose emitter is connected to the power supply. The collector of the transistor Q52 is connected to the ground through the constant current source I52 and the resistor R
It is connected to the power source through 4. Also, the transistor Q
The collector of 66 is connected via a resistor R2 to the base of a transistor Q63 whose emitter is connected to the power supply,
The collector of this transistor Q53 is the transistor Q5.
It is connected to 2 collectors. Further, the collector of the transistor Q53 is connected to the base of the transistor Q54, the emitter of the transistor Q54 is connected to the power supply, and the collector is connected to the MARK terminal. The collector of the transistor Q51 is connected to the C terminal, and the C terminal is connected to the external capacitor C1 having the other end connected to the power supply. The transistors Q51, Q52, Q53, Q54 are all PNP.
It is a type.

When a rotation pulse is input in such a circuit, its H causes the transistor Q66 to turn ON.
To do. As a result, a current flows through the resistor R1 and the collector of the transistor Q66 becomes L. Therefore, the transistor Q
51 and Q53 turn on. On the other hand, since there is a capacitor C1 between the C terminal and the power supply, in this state C
The terminal is H. Therefore, the transistor Q52 is also off. On the other hand, when the rotation pulse becomes L,
Transistor Q66 turns off and transistor Q5
1, Q53 is turned off. But transistor Q52
Is OFF until the potential of the C terminal drops 0.7V from H. The potential of the C terminal gradually decreases due to the current of the constant current source I51. Thus, the transistor Q53 is OFF and the transistor Q53
When 52 is OFF, the transistor Q52 is ON. The collector of this Q54 is connected to the MARK terminal, and the external capacitor C2 is connected to this MARK terminal. Then, when the transistor Q54 is turned on, the capacitor C2 is discharged. When the transistor Q54 is OFF, the capacitor 2 is charged by the resistor R20 that connects the MARK terminal and the ground, and the voltage at the MARK terminal decreases. When the voltage at the C terminal drops by 0.7 V or more with respect to the power supply, the transistor Q52 turns on and the transistor Q54 turns off. As a result, the voltage at the MARK terminal drops.

That is, as shown in FIG. 10, when H is input as a rotation pulse, the C terminal becomes H by this, and when the rotation pulse is turned OFF, the transistor Q54 turns ON and the MARK terminal becomes H. Then, when the voltage at the C terminal drops by 0.7 V, the transistor Q54 turns off, whereby the voltage at the MARK terminal begins to gradually decrease. Then, when the rotation pulse periodically becomes H, the same operation is repeated, and the MARK terminal repeats up and down between predetermined potentials.

On the other hand, the base of a transistor Q55, whose emitter is connected to a power source via a constant current source I53 via a resistor R5, is connected to the MARK terminal. The collector of the transistor Q55 is connected to the collector of the transistor Q57 whose emitter is connected to the ground.
The emitter of a transistor Q56 is connected to the constant current source I53, and the collector of the transistor Q56 has a collector and a base short-circuited to each other.
Is connected to ground via. Also, Q57 and Q5
The bases of 8 are commonly connected. The base of the transistor Q56 is connected to the predetermined reference potential Vr via the resistor R6.
ef has been entered. The collector of the transistor Q57 is connected to the base of the transistor Q59 whose emitter is connected to the ground. The transistors Q55, Q56 are PNP type, and the transistors Q57, Q58, Q59 are NPN type.

Therefore, when the voltage of the MARK terminal is equal to or higher than the reference voltage Vref, the transistor Q55 tends to have less current flowing than the transistor Q56, and the transistor Q59 is off. On the other hand, when the voltage of the MARK terminal becomes lower than the reference voltage Vref, the transistor Q
55 makes it easier for a current to flow than the transistor Q56, which raises the base potential of the transistor Q59 and turns on the transistor Q59. Therefore, the transistor Q59 is turned on when the rotation pulse is not input for a predetermined time. The transistor Q59 corresponds to the transistor Q24 in FIG. 6, and the latch circuit to which the collector of the transistor Q59 is connected is exactly the same as the latch circuit 34 in FIG. The collector of the latch circuit Q28 has a resistor R1.
1 is connected to the power source through the transistor Q
It is connected to the base of 63. This transistor Q6
9 has an emitter connected to the ground and a collector connected to a power supply via a resistor R62. The collector of the transistor Q63 is connected to the base of the transistor Q65 via the resistor R63 and to the base of the transistor Q64 via the resistor 64. The emitter of the transistor Q64 is connected to ground,
The collector outputs an abnormality detection signal. The emitter of the transistor Q65 is connected to the ground, and the collector thereof is connected to the output section 22. The transistors Q63, Q64, Q65 are NPN type.

The output transistor Q of the latch circuit
When 28 turns on, the transistor Q63 turns off and the transistors Q64 and Q65 turn on. Therefore, Q64
By turning on, the motor non-rotation signal can be output. Further, by turning on the transistor Q65, it is possible to stop the motor rotation by stopping the output of the motor drive signal from the output unit 22.

In the present embodiment, the collector of the transistor Q22 in FIG. 6 is C via the resistor R30.
It is connected to the ORK terminal. Therefore, when the Hall element abnormality detection unit 30 detects a failure of the Hall element and the transistor Q22 is turned on, this causes the capacitor C2 to be discharged, and the potential of the MARK terminal is lowered. Then, when the voltage at the MARK terminal falls below the reference voltage Vref, the abnormality detection signal is latched in the latch circuit as in the rotation stop, and the transistors Q64 and Q65 are turned on.
To do.

[0044]

As described above, according to the present invention,
The abnormality detection unit detects an abnormality by a logical operation of the output of the binarization unit. Therefore, the abnormality of the Hall element can be accurately detected with a relatively simple circuit.

The output from the abnormality detecting section is filtered by a low pass filter circuit to remove noise, and this output is latched by a latch circuit. Therefore, malfunction can be prevented and the abnormality detection signal can be held.

Further, the external capacitor can be reduced by one by using the capacitor used for detecting the decrease in the motor rotation speed in the rotation detecting unit for filtering the output of the abnormality detecting unit.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment.

FIG. 2 is a waveform diagram showing the output of a Hall element.

FIG. 3 is a waveform diagram showing an output of a hall amplifier.

FIG. 4 is a diagram showing an output of a hall amplifier.

5 is a circuit diagram showing a configuration of a logic unit 20. FIG.

FIG. 6 is a circuit diagram showing a configuration of a Hall element abnormality detection unit 30.

FIG. 7 is a circuit diagram showing configurations of a low-pass filter circuit 32 and a latch circuit 34.

FIG. 8 is a circuit diagram showing a configuration of a second embodiment.

FIG. 9 is a circuit diagram showing a configuration of a rotation detection circuit 40.

FIG. 10 is a waveform diagram showing the potential of each part.

[Explanation of symbols]

12, 14, 16 Hall amplifier, 20 Logic part,
22 output section, 30 hall element abnormality detection section, 32 low pass filter circuit, 34 latch circuit, 40 rotation detection circuit.

Claims (3)

[Claims] 1. A motor drive circuit for controlling a motor drive current in accordance with a signal from a three-phase Hall element that outputs alternating current signals that are 120 ° out of phase with each other, and an output from the three-phase Hall element. The signal level of the signal is 2
A motor drive circuit comprising: a binarizing unit for binarizing; and an abnormality detecting unit for detecting an abnormality by a logical operation of an output of the binarizing circuit. 2. The circuit according to claim 1, further comprising: a low-pass filter circuit that integrates the output of the abnormality detection unit to remove noise by charging and discharging the capacitor, and latches the output of this low-pass filter circuit. And a latch circuit that outputs an abnormal signal, and a motor drive circuit. 3. A motor drive circuit for controlling a motor drive current in accordance with a signal from a three-phase hall element that outputs alternating current signals that are 120 ° out of phase with each other, and an output from the three-phase hall element. The signal level of the signal is 2
A binarization unit for binarization, an abnormality detection unit for detecting an abnormality by logical operation of the output of the binarization circuit, and charging / discharging of a capacitor according to a rotation pulse corresponding to the output signal from the Hall element. Generate current and
A rotation detection unit that detects that the number of rotations of the motor has become less than or equal to a predetermined value depending on the charging / discharging state of the capacitor, and
A motor drive circuit characterized in that, by charging / discharging the above-mentioned capacitor, a decrease in the number of rotations of the motor and an abnormality in the Hall element are detected together in a rotation detection unit.