JPH08331133A - Atm switch - Google Patents

Abstract

PURPOSE: To set the copying order of a cell according to the priority order of cell transfer by constituting a copy trunk of a queue buffer which accumulates transiently by discriminating an arriving cell is sequence of arrival and a means which executes the processing of a cell accumulated in the queue buffer in high priority order. CONSTITUTION: VPI/VCI read from the header part of the cell arriving at the copy trunk 30 is compared with VPI/VCI stored in a header conversion stable in advance, and the cell is copied on it according to the priority order. The queue buffer is provided at every priority order class, and the cell is accumulated in each of plural queue buffers, respectively. Those information are read out from the queue buffer according to the priority order, and new VIP/VCI is read out according to the header conversion table, and moreover, pay-loads by copy number are read out from a ray-load buffer, and they are coupled again, and outputted to a transmission line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an asynchronous transfer mode (AT
M: Asynchronous Transfer Mode) Used for communication. In particular, it relates to a cell copying technique in which delay quality is taken into consideration.

[0002]

2. Description of the Related Art In communication in an asynchronous transfer mode (hereinafter referred to as ATM), information is transmitted and received using fixed length packets called cells. An ATM switch is a device for switching and connecting this cell according to the destination information written in its header. This conventional example will be described with reference to FIGS. FIG. 8 is an overall configuration diagram of a conventional ATM switch. FIG. 9 is a block diagram of a conventional copy trunk. FIG. 10 is a diagram showing a relationship between an arrival cell and an output cell in the conventional example.

A processing procedure for distributing input information to a plurality of destinations by using a conventional ATM switch will be described. 8, reference numerals 101 to 103 are incoming lines, reference numeral 20 is a phase adjusting circuit, reference numeral 30 is a copy trunk, reference numerals 401 to 404 are switch input lines, reference numeral 300 is a phase adjustment timing signal, reference numeral 10 is a switching element, reference numerals 201 to 201. Reference numeral 204 represents a switch output line. As shown in FIG. 8, incoming lines 101-103
The phase of the cell input from is adjusted by the phase adjustment circuit 20 and output to the switch input lines 401 to 403.

One cell β (destination # 0) input via the switch input line 402 is exchange-connected by the switch element 10 and the switch output line 20 addressed to # 0.
It is output to 1. Cell α (destination # 1 and # 2) and cell γ (destination # 0 and #) that need to be distributed to multiple destinations
1) is temporarily output to the switch output line 204 for the copy trunk via the switch element 10, and is output to the copy trunk 3
Copy processing is performed with 0.

Here, the copy numbers of the cell α and the cell γ are “2” and “3”, and the copy processing is sequentially performed according to the arrival order of the cells. The two cells copied by the copy trunk 30 are again the switching elements 1
It is output to the switch output line 202 addressed to # 1 and the switch output line 203 addressed to # 2 via 0. As shown in FIG. 9, the cells transferred to the copy trunk 30 are temporarily stored in the FIFO type copy process waiting buffer 70, and the waiting of the copy process is performed. The service processing circuit 72 performs a copy process of the cell being processed according to the read timing. The service processing circuit 72 is a copy number counter 7 as a means for counting the number of times the copy process is performed.
4 and the value written in the copy number counter 74 and the cell identification information (VPI / VCI) in the cell are used to retrieve the route tag (RB) and new cell identification information from the table 76, and the result is obtained. Then, the root tag is added and the cell identification information (new VPI / VCI) is replaced and output. After performing the copy process, the value of the copy number counter 74 is increased, and as a result, when it is determined that the requested number of cell copy processes are completed, the process waiting buffer 7
The next cell stored in 0 is transferred to the service processing circuit 72.
Transfer to.

FIG. 10 shows an example of the relationship between the arriving cell and the cell output after the copy processing is performed in this way. This is because cells γ, β, and α arrive at times t1, t2, and t3, the respective copy numbers are “3”, “2”, and “2”, and the delay priority is “L”, “L”, “ H ″.

[0007]

As is apparent from this example, according to the conventional technique, since the copy processing is performed according to the arrival order of cells, the delay characteristic of the output cell and the like are taken into consideration. However, there is a problem that the desired service quality cannot be satisfied.

The present invention has been made in view of such a background, and an object thereof is to provide an ATM switch in which a cell copy order is set in accordance with a cell transfer priority order. An object of the present invention is to provide an ATM switch capable of providing a cell copy transfer service in which service quality is taken into consideration for cells having different quality of service requirements.

[0009]

SUMMARY OF THE INVENTION The present invention is most characterized by performing cell copying processing divided according to the priority of cell transfer. That is, the present invention includes a switch element that connects a plurality of input lines and a plurality of output lines in a one-to-one relationship, and a copy trunk that generates cells having the same content, and the switch element is provided at the input end of the copy trunk. This is an ATM switch in which an output line is connected and the input line of the switch element is connected to the output end of this copy trunk.

Here, the feature of the present invention resides in that the copy trunk has a queue buffer for temporarily accumulating arrival cells by identifying the arrival order and a cell having a high priority for the cells accumulated in the queue buffer. And means for executing the process with priority.

As a result, for example, even if a cell having the highest priority arrives at the copy trunk after the cell having the lowest priority, the cell having the highest priority precedes the cell having the lowest priority regardless of the order of arrival. By copying the cells, it is possible to copy the cells in consideration of the priority order.

It is preferable that the queue buffer is provided for each cell transfer priority.

It is preferable that the queue buffer stores information other than the payload portion of the cell, and that the queue buffer further comprises another payload buffer. As a result, the amount of information accumulated in the queue buffer can be reduced and the capacity of the queue buffer can be reduced.

It is desirable to provide a means for adding address information, copy number information and priority information of the payload buffer storing the payload to the header information of the cell stored in the queue buffer.

As a result, it is possible to provide a cell copy transfer service in which service quality is taken into consideration for cells having different service quality requirements.

[0016]

The VPI / VCI read from the header portion of the cell arriving at the copy trunk is compared with the VPI / VCI stored in advance in the header conversion table, and the priority order is searched. According to this priority
The cell is copied. A queue buffer may be provided for each priority class, and cells may be accumulated in each of the plurality of queue buffers. Furthermore, the header part and the payload part are separated so that the payload part is
You may make it store in a buffer and accumulate only a header part in a queue buffer. At this time, in addition to the VPI / VCI information previously inserted in the header part, the copy number information of the cell having this VPI / VCI, priority information, and this V stored in the payload buffer.
Address information of the payload of a cell having PI / VCI may be added.

These pieces of information are read from the queue buffer according to the priority order, new VPI / VCI are read according to the header conversion table, and further,
The number of copies of the payload is read from the payload buffer, and these are recombined and output to the transmission path.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an overall configuration diagram of an embodiment of the present invention. FIG. 2 is a block diagram of the switch. FIG. 3 is a block diagram of the copy trunk. FIG. 4 is a block diagram of the read control circuit.

According to the present invention, the switch element 1 for connecting the input lines 401 to 404 and the output lines 201 to 204 in a one-to-one relationship.
0 and a copy trunk 30 for generating cells having the same content, and the output line 204 of the switch element 10 is connected to the input end of this copy trunk 30.
It is an ATM switch in which the input line 404 of the switch element 10 is connected to the output terminal of 0.

Here, the feature of the present invention is that the copy trunk 30, as shown in FIG. 4, identifies "H" class address queue buffer 64 and "L" for temporarily accumulating arrival cells by identifying the arrival order. The read control circuit 50 having the class address queue buffer 66 and the cells accumulated in the “H” class address queue buffer 64 and the “L” class address queue buffer 66 are processed with priority given to the cells having higher priorities. It includes the controller 32 shown in FIG. 3 as a means for executing.

"H" class address queue buffer 64
The "L" class address queue buffer 66 is provided for each cell transfer priority.

"H" class address queue buffer 64
The "L" class address queue buffer 66 stores information other than the payload portion of the cell, and is provided with another payload buffer 40 that stores this payload portion.

"H" class address queue buffer 64
And a means for adding the address information (MA) of the payload buffer 40 accumulating the payload, the copy number information and the priority information (DP) to the header information of the cell accumulated in the “L” class address queue buffer 66. The MA addition circuit 54 is provided.

Next, the operation of the embodiment of the present invention will be described. As shown in FIG. 1, the cells input from the incoming lines 101 to 103 have their phases adjusted by the phase adjustment circuit 20 and are output to the switch input lines 401 to 403. Switch input line 4
One cell β (destination # 0) input via 02 is switched and connected by the switch element 10 and output to the switch output line 201 addressed to the destination # 0. The cells α (destinations # 1 and # 2) and the cells γ (destinations # 0 and # 1) that need to be distributed to a plurality of destinations are once transmitted via the switch element 10 to the switch output line 2 for the copy trunk.
It is output to 04.

At this time, in the embodiment of the present invention, the copying process is performed in consideration of the cell quality ranking. In this example,
The cell α whose delay quality is “H” is copied by the copy trunk 30 before the cell γ which arrived first. In this copy trunk 30, the two cells generated by the copy processing are the switch input line 40.
4 is sent to the switch element 10, and after the switch element 10 is exchange-connected, the switch output line 20
2 and 203.

FIG. 2 shows a configuration example of the switch element 10,
The state where cells input via the switch input lines 401 to 404 are exchange-connected to the switch output lines 201 to 204 is shown. FIG. 2 shows an example in which the input cell β from the switch input line 402 is output to the switch output line 201.

A route tag (RB) is attached to the input cell β as a destination index and is input to the switch element 10.
The input cell is sent to all routes and passed through the filter 12. The filter 12 refers to the route tag and determines whether to pass or discard. The passed cells are temporarily stored in the FIFO type output waiting buffer 14 and sequentially output.

An example of copy processing performed by the copy trunk 30 according to the embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 3, the header separating unit 31 receives the payload and VPI / VCI from the input cell to the copy trunk 30.
Information is taken out and the VPI / VCI information is stored in the controller 3
2 via the signal line 501, the payload is transferred to the payload buffer 40 via the signal line 502,
The data is stored in the address designated by the write address designating circuit 52 via the signal line 503. This controller 32
Then, based on the transferred VPI / VCI information, the header conversion table 34 is referred to via the signal line 504, and the number of copies and the quality priority information (here, the delay priority information) from the preset header conversion table 34. Via the signal line 505, and the MA (Memory Address) adding circuit 54 adds the in-buffer accumulated address information MA of the payload given from the write address designating circuit 52 via the signal line 506 to the read control circuit 50. Forward. In accordance with the quality priority information, the read control circuit 50 selects one of the “H” class address queue buffer 64 and the “L” class address queue buffer 66, which are provided in the read control circuit 50 and are divided into quality classes. Select and New V
The PI / VCI information, the copy number information, and the buffer storage address information MA of this payload are stored as information for executing copying. FIG. 3 shows a processing example of delay 2 quality.

When the read timing comes from the signal line 600, if the "H" class address queue buffer 64 in the read control circuit 50 has processing waiting information, the "H" class is selected, and the "H" class is processed waiting information. If there is not, the next “L” class address queue buffer 66 is selected,
The VPI / recorded at the head of the “H” class or “L” class address queue buffer 64 or 66.
The VCI information, copy number information, and buffer storage address information MA are read. Stored address information in buffer M
A is transferred to the payload buffer 40 via the signal line 508, and the copy number information and VPI / VCI information are transferred to the header conversion table 34 via the signal line 509. The header conversion table 34 searches for new VPI / VCI information and a root tag based on the transferred copy number information and VPI / VCI information, and outputs the new VPI / VCI information and the route tag to the header adding unit 36 via the signal line 510. On the other hand, the payload information is read from the payload buffer 40 via the signal line 511 according to the buffer storage address information MA of the signal line 505, and the header adding unit 36 adds a new VP to the payload.
The I / VCI information and the route tag are added and output.

FIG. 5 is a flow chart for explaining the operation of the read control circuit 50. The copy number is controlled by the subtractor 51. This subtracter 51 has an “H” class or “L” class address queue buffer 64 or 6
After the content of 6 is read (S1), the content of the copy number is decremented by 1 (S2). When the copy number becomes "0", the copy processing of the first cell is completed,
The information accumulated at the head of the "H" class or "L" class address queue buffer 64 or 66 is discarded (S3), and the second and subsequent addresses are moved to the previous one (S4). That is, the second cell is the next copy processing target with the first cell as the head.

6 and 7 show examples of the relationship between the cells that have arrived and the cells that have been output when the copy processing is performed in this way.
Will be described with reference to. FIG. 6 is a diagram showing a cell sequence in which the priority order is held, and FIG. 7 is a diagram showing the cell accumulation state of the “H” class and “L” class address queue buffer 64 or 66. 6 and 7 are times t1, t2, and t.
3, the copy numbers of cells γ, β, and α are “3”,
“2”, “2”, delay priority is “L”,
This is an example of the case where cells of "L" and "H" arrive,
FIG. 6 shows input cells and output cells, and FIG. 7 conceptually shows the transition of information accumulated in the “H” class and “L” class address queue buffers 64 and 66. As is clear from this, it is understood that the delay priority control based on the delay priority order is performed.

[0032]

As described above, according to the present invention,
The cell copy order is set according to the priority order of cell transfer. Therefore, it is possible to provide a cell copy transfer service in which service quality is taken into consideration for cells having different quality of service requirements.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a switch element.

FIG. 3 is a block configuration diagram of a copy trunk.

FIG. 4 is a block configuration diagram of a read control circuit.

FIG. 5 is a flowchart for explaining the operation of the read control circuit.

FIG. 6 is a diagram showing a cell string in which priority levels are held.

FIG. 7 is a diagram showing a cell accumulation state of “H” class and “L” class address queue buffers.

FIG. 8 is an overall configuration diagram of a conventional ATM switch.

FIG. 9 is a block configuration diagram of a conventional copy trunk.

FIG. 10 is a diagram showing a relationship between an arrival cell and an output cell in a conventional example.

[Explanation of symbols]

 10 switch element 12 filter 14 output waiting buffer 20 phase adjustment circuit 30 copy trunk 31 header separation unit 32 controller 34 header conversion table 36 header addition unit 40 payload buffer 50 read control circuit 52 write address designation circuit 54 MA addition circuit 64 "H ”Class address queue buffer 66“ L ”class address queue buffer 70 Processing wait buffer 72 Service processing circuit 74 Copy number counter 76 Table 101 to 103 Incoming line 201 to 204 Switch output line 300 Phase adjustment timing signal 401 to 404 Switch input line 501 To 511, 601 to 608 signal line 600 read timing signal MA buffer accumulated address information RB route tag

Claims (4)

[Claims] 1. A switch element for connecting a plurality of input lines and a plurality of output lines in a one-to-one relationship, and a copy trunk for generating cells having the same contents, and an output of the switch element at an input end of the copy trunk. In an ATM switch in which a line is connected and an output line of the copy trunk is connected to an input line of the switch element, the copy trunk stores in the queue buffer a queue buffer that temporarily stores arrival cells by identifying the arrival order and a queue buffer. An ATM switch, comprising means for executing processing by giving priority to accumulated cells with higher priority. 2. The ATM switch according to claim 1, wherein the queue buffer is provided for each priority of cell transfer. 3. The ATM switch according to claim 1, wherein the queue buffer stores information excluding a payload portion of a cell, and another payload buffer for storing the payload portion is provided. 4. The ATM switch according to claim 3, further comprising: means for adding address information, copy number information, and priority information of a payload buffer storing the payload to header information of a cell stored in the queue buffer. .