JPH08228193A - Cell exchanging device - Google Patents

Abstract

PURPOSE: To provide a cell exchanging device capable of minimizing the abandonment of cells even when the cells are concentratively inputted to a specified outgoing line and address management ability in a buffer control circuit goes over. CONSTITUTION: The buffer control circuit 15 selectively connects an incoming line space switch 13 to buffer memories 111 -11p or external FIFO memories 211 -21L by the address storage states of address queues 181 -18m and controls the write of the cells. Further, the address of the written cell is stored in the address queue for the respective outgoing lines. Then, an outgoing line space switch 14 is selectively connected to the buffer memories 111 -11p or the external FIFO memories 211 -21L, the cell is read to sent out the cell from the corresponding outgoing line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell switching device and a cell switching system for switching at high speed a cell in which various kinds of multimedia information such as voice, data and images are blocked.

[0002]

2. Description of the Related Art FIG.
FIG. 6 is a block diagram showing a conventional cell exchange apparatus disclosed in Japanese Patent Publication No.

In the figure, 1 ₁ to 1 _n are n (n ≧ 2) incoming lines into which cells consisting of a header part including an outgoing line number as destination information and a data part are input, and 2 ₁ to 2 _m are the above-mentioned The cells are m (m ≧ 2) output lines that are output according to the destination specified in the header part.

10a _{1 to} 10a _n are the input lines 1 ₁ to 1 _n
Is a header processing circuit which is provided corresponding to each of the _above and detects the destination outgoing lines 2 ₁ to 2 _m from the header part of the cell input from the incoming lines 1 ₁ to 1 _n .

In addition, 11 _{1 to} 11 _p store the cells at designated addresses, and by designating the addresses, the stored cells can be read out regardless of the order of writing p (p It is possible to store a plurality of cells in one buffer memory 11 _{1 to} 11 _p with (≧ n) buffer memories.

Reference numerals 12 _{1 to} 12 _p denote the buffer memory 11
It is provided corresponding to each of _{1 to} 11 _P , for example, a FIFO
This is a storage control circuit that manages an empty address using a memory of a type and gives a read address and a write address to the associated buffer memories 11 _{1 to} 11 _P.

Reference numeral 13 denotes the header processing circuits 10a ₁ to 10
An input space switch for selectively connecting a _n to predetermined buffer memories 11 _{1 to} 11 _p. Reference numeral 14 denotes an output for selectively connecting the buffer memories 11 _{1 to} 11 _p to predetermined output lines 2 ₁ to 2 _m. It is a line space switch.

23 ₁ to 23 _m are provided corresponding to the respective outgoing lines 2 ₁ to 2 _m, and are connected to predetermined buffer memories 11 _{1 to} 11 _p by the outgoing line space switch 14 so that the buffer memories 11 ₁ to R times the linear velocity from 11 _p (2 ≦ r <
This is an output line speed adjustment buffer for accumulating cells read out at a speed of (the number of output lines) and outputting to the output lines 2 ₁ to 2 _m associated with the output line speed.

Further, 15 is a write buffer selection circuit 1
6, address exchange circuit 17, address queue 18 ₁ ~
18 _m , and a read buffer selection circuit 19,
The switching of the incoming line space switch 13 is controlled to select the buffers 11 _{1 to} 11 _p to which the cells are written, and the buffer memories 11 _{1 to} 11 of the written cells are selected.
Addresses on _p are managed for each destination of the cell, and the cells are read from the buffer memories 11 _{1 to} 11 _{p in} a predetermined order at a speed r times the output line speed (2 ≦ r <number of output lines). Output line 2 in which the relevant cell is specified in the header part
By controlling the outgoing line space switch 14 to be output to ₁ to 2 _{m, 1} corresponding outgoing line speed adjustment buffers 23 ~ 23 _m
Is a buffer control circuit for writing the data to the corresponding output lines 2 ₁ to 2 _m and reading the data according to the output line speed.

Further, in the buffer control circuit 15, the 16 cell arrives to the input lines ₁ 1 to 1 _n, the header processing circuits 10a ₁ associated with its incoming lines ₁ 1 to 1 _n
Receives the outgoing line number of the cell detected by the 10 A _n, a buffer memory 11 for storing the cell ₁ to 11 _p
And the corresponding header processing circuits 10a ₁ to 1
A write buffer selection circuit for controlling switching of the input line space switch 13 for connecting to 0a _n .

Reference numeral 17 refers to the outgoing line number detected by the buffer selection circuit 16 to refer to the arriving cell as the outgoing line 2 ₁ of the destination.
To 2 _m divided separately, the write address of the cell written buffer memory 11 on ₁ to 11 _p, storage control circuits 12 ₁ to corresponding to the buffer memory 11 ₁ to 11 _p
It is an address exchange circuit which is obtained from 12 _p and writes it in the address queue described later.

Numerals 18 ₁ to 18 _m are address queues thereof, which are constituted by a FIFO type memory and are provided corresponding to the respective outgoing lines 2 ₁ to 2 _m . This address queue 18 ₁ ~ 18 _m, it is the outgoing lines 2 ₁ each to 2 _m associated, the output line 2 ₁ to 2 _m the _first buffer memory 11 which cell is accumulated destined ~ write address on 11 _p is written by the address exchange circuit 17 in arriving order.

Numeral 19 designates this address queue 18 ₁ to 18
_The cells to be read from the buffer memories 11 _{1 to} 11 _p are determined with reference to _m , and their address queues 18 ₁ to 18 _m are determined.
As a read address read out address from and sends the associated to the memory control circuit 12 ₁ to 12 _p in the appropriate buffer memory 11 ₁ to 11 _p, by controlling the switching of the outgoing line space switch 14, the buffer memory 11 is a read buffer selection circuit connected to outgoing lines 2 ₁ to 2 _m to the appropriate ₁ to 11 _p.

Next, the operation will be described. Here, FIG.
7 to FIG. 29 is a time chart showing the timings of the respective parts of the signal, the incoming line ₁ 1 to 1 _n number n and outgoing lines 2 ₁ to
Number m with 2 _m of each present 4, the buffer memory 11 ₁
The flow of control when the number p of 11 _p is 10 is shown.

The cells handled here are fixed-length and randomly input, and the cell input phase is adjusted before being input to the input lines 1 ₁ to 1 _n , so that the cell input from all lines is the same. Shall be supplied in the phase.

In the figure, (a) to (d) are input lines 1 ₁ to 1
₄ is an example of cells input to ₄ , ₄ , (e) to (f) are examples of accumulation of cells in the buffer memories 11 _{1 to} 11 _{10 in} that case, and (y) to (so) are output lines 2 ₁ to 2 An example of cells output from ₄ is shown. Here, it is assumed that all circuits are synchronized and one cell can be input and output in one time slot.

[0017] When a cell is input to the input line ₁ 1 to 1 _4, the header processing circuits 10a provided corresponding to each incoming line ₁ 1 to 1 _4
1 10 A ₄ detects the outgoing line number from the header portion of the input cell. The write buffer selection circuit 16 of the buffer control circuit 15, the header processing circuits 10a ₁ to 10
Referring to a _4, the incoming line space switch 13, an instruction to connect the buffer memory 11 ₁ to 11 ₁₀ selected for storing arriving incoming lines 1 ₁ to 1 ₄ and the cell of the cell individually.

Here, various ways of connecting the incoming line space switch 13 are conceivable, but the cells are buffer memories 11 _1- .
Since it is not desirable that two or more cells to be read are stored in the same buffer memory 11 _{1 to} 11 ₁₀ when they are stored in 11 ₁₀ and read later, a large number of cells are stored in the buffer memory 11 _{1 to} 11 11 to prevent this. _The method of dispersing in ₁₀ is preferable.

To this end, the buffer memories 11 ₁ to ₁ 1
1 ₁₀ not enough as many incoming 1 ₁ to 1 _4, in order to solve the above problem, the Write as many buffer memories 11 ₁ to 11 ₁₀ becomes easy to control. Alternatively, separately from the above, as a simpler control example, a method of writing cells by selecting the buffer memories 11 _{1 to} 11 ₁₀ with the least cell retention residue can be considered. That is, x at the same time
When the number of cells arrives, the x number of buffer memories 11 _{1 to} 11 ₁₀ with the smallest cell remaining amount are selected and the incoming line 1 ₁
A buffer memory 11 ₁ to 11 ₁₀ selected ~ 1 ₄ is a method for spatially connected.

In this example, as a simpler control example, a method of sequentially selecting the buffer memories 11 _{1 to} 11 ₁₀ and writing the arrived cells is shown. That is, the buffer memories 11 ₁ , 11 ₂ , 11 _3, ... 11 ₁₀ are selected in this order,
The cells that have arrived are written in.

In the time slot 1, the first F1 cell of the signal f from the incoming line 1 ₁ (hereinafter, the cell is called the F1 cell because it is the first cell of the signal f. The same applies to other cells). , Incoming line 1 ₂ to signal g G1 cell, incoming line 1
The I1 cell of the signal i is input from ₄ . In the header portion of each cell, the destination outgoing line number, that is, O ₁ designating outgoing line 2 ₁ for F1 cell and O ₄ designating outgoing line 2 ₄ for cell G ₁ are assigned to I1 cell. O ₃ to specify the outgoing line 2 ₃
Are written respectively.

In the time slot 2, the incoming line space switch 13 has the incoming line 1 ₁ and the buffer memory 11 ₁ , the incoming line 1 ₂ and the buffer memory 11 ₂ , and the incoming line 1 ₄ and the buffer memory 11.
Connect ₃ respectively. Therefore, these cells are accumulated at the addresses designated by the storage control circuits 12 _{1 to} 12 ₃ of the buffer memories 11 _{1 to} 11 _{3 in} the time lot 2.

At this time, the write addresses of the buffer memories 11 _{1 to} 11 ₃ are sent from the storage control circuits 12 _{1 to} 12 _P to the address exchange circuit 17. The write address is selected from among the addresses each storage control circuit 12 ₁ to 12 ₃ are respectively managed as an empty address.

The address exchange circuit 17 divides each input cell by destination main line with reference to the write buffer selection circuit 16, and the write address of the buffer memory 11 ₁ is stored in the address queue 18 ₁ and the line address of the buffer memory 11 ₂ . To the address queue 18 ₄ and the write address of the buffer memory 11 ₃ to the address queue 18 _3.
Write at the end of each.

Next, in the time slot 3, the read buffer selection circuit 19 has the address queue 18
_The addresses stored therein are taken out from ₁ to 18 ₄ and sent to the storage control circuits 12 _{1 to} 12 ₃ corresponding to the corresponding buffer memories 11 _{1 to} 11 ₃ and the buffer space 11 ₁ is sent to the output line space switch 14. ~ 11 ₃ and outgoing line 2
Instruct to connect ₁ , 2 ₃ and 2 ₄ individually. As a result, the output line space switch 14 connects the buffer memory 11 ₁ and the output line 2 ₁ , the buffer memory 11 ₂ and the output line 2 ₄ , and the buffer memory 11 ₃ and the output line 2 ₃ respectively in this time lot 3.

Each of the storage control circuits 12 _{1 to} 12 ₃ has a buffer memory 11 ₁ to ₁ 1 associated with the received address.
Feed 1 ₃ as a read address, hereinafter, it manages the addresses as an empty address. Each buffer memory 11
Cell read from ₁ to 11 ₃ is outputted to the outgoing line 2 _1, 2 ₄ and 2 ₃ of the destination specified in each header.

In the above example, the destination cells of the input cells are all different, but the cells input in time slot 2 have the same destination node. F2 cell, G2 cell entered in the time slot 2, H1 cell is respectively written into the buffer memory 11 _4, 11 ₅ and 11 ₆ In the same manner, the header portion of the three cell,
All are O ₄ is marked to specify the same outgoing line 2 _4.

[0028] In the example of FIGS. 27 29 Yes with a priority of young numbered order input line performs queuing of cells, the buffer memory 11 in the time slot 4, 5, 6 _4, 11
_The F2, G2, and H1 cells are read out in the order of ₅ , 11 ₆ and sent to the outgoing line 3 ₄ . Hereinafter, cell exchange is performed in this procedure.

In time slot 8, buffer memory 1
I2 cell and H6 cell are stored in 1 ₃ . Here, although the destinations of these two cells are the same as the outgoing line 2 _{2 for the} I2 cell and the outgoing line 2 _{3 for the} H6 cell, they are the same as the outgoing line speeds of the outgoing lines 2 ₁ to 2 _4. Even if they are read at a speed of 1, they cannot be taken out at the same time because they are stored in the same buffer memory 11 ₃ .

30 to 31 are time charts showing enlarged portions of the time slots 6 to 13 in FIGS. 27 to 29. In FIGS. 30 to 31, the buffer memories 11 ₁ to 1
Shows the case of performing 1 ₁₀ read at three times the speed of the outgoing velocity outgoing lines 2 ₁ to 2 _4. (E) to (f) in the figure
The accumulation example of a cell of the buffer memory 11 ₁ to 11 _10,
(Tsu) - (La) is the outgoing line speed adjustment buffer 23 _{1-23 4}
The writing status of the cell to (Yo) to (So) is the outgoing line 2 ₁
Shows an example of a cell output from 21 to _24, respectively.

[0031] Here, a cell destined to a different destination than the I2 cell and H6 cell in the buffer memory 11 ₃ in the time slot 8, be read at three times the speed of the outgoing line speed from the buffer memory 11 _3, Both cells can be output simultaneously to the corresponding outgoing lines 2 ₂ and 2 ₃ . That is, read out at three times the speed of the outgoing line speed from the buffer memory 11 ₁ to 11 _10, up to three in the same buffer memory 11 ₁ to 11 _10, can be tolerated duplicate read cell in the same time slot become.

Although such a thing also occurs in the other time slots 9, 10, and 15, in any case, the cell does not wait due to the collision.

Although a case has been described in which the read speed of the buffer memories 11 _{1 to} 11 ₁₀ is set to three times the output line speed, it is generally possible to set the read speed to 2 times or more and less than the output line number, r times.
Further, it is assumed the use of the dual-port memory as respective buffer memories 11 ₁ to 11 ₁₀ may also be implemented in operable single port memory with more speed.

Further, when the number of cells to be read from the same buffer memories 11 _{1 to} 11 _p in one time slot exceeds r, a fixed number or a random number is used to correspond to the outgoing lines 2 ₁ to 2 _m . Collision can be avoided by assigning a priority order that changes every time and extracting only r cells and waiting for other cells.

[0035]

Since the conventional cell switching apparatus is configured as described above, when cells concentrate on one outgoing line, the ratio of the cells addressed to that outgoing line to the buffer memory is high. Higher, resulting in more cell discards.

The present invention has been made in order to solve the above problems, and provides a cell exchange apparatus which can perform switching without discarding cells even if cells are concentrated on one outgoing line. With the goal. Another object of the present invention is to obtain a cell exchange device capable of changing the size of the buffer memory. Another object of the present invention is to provide a cell switching device in which a new address queue is provided to increase the number of addresses that can be stored.

[0037]

According to a first aspect of the present invention, a plurality of incoming lines into which a cell consisting of a data section and a header section containing its destination information is input, and the cells are designated by the header section. Multiple outgoing lines that are output according to the destination
Provided corresponding to each of the incoming lines, from the header portion of the cell input from the incoming line, a header processing circuit for detecting the outgoing line of the destination, the cell is written by specifying the address, Further, a plurality of buffer memories capable of reading the cells regardless of the order of writing by designating an address, and an input line space switch for selectively connecting the header processing circuit to a predetermined buffer memory. An output line space switch for selectively connecting the buffer memory to a predetermined output line and an input line space switch to select a buffer memory in which the cell is written, and An address in the buffer memory is managed for each destination of the cell, and the output line space switch is controlled based on the address to control the cell. In a cell switching device having a buffer control circuit for outputting in a predetermined order to the output line specified by the header section of the The feature is that the above expansion memory can be arranged.

A second aspect of the invention is characterized in that the buffer control circuit controls writing and reading of cells using the buffer memory and the extension memory.

A third aspect of the invention is characterized in that the cell exchange apparatus further comprises address management means for managing the address of the cell stored in either the buffer memory or the extension memory. .

Further, in a fourth invention, the expansion memory is
It is characterized by storing a cell of a specific destination.

A fifth aspect of the present invention provides the above expansion memory,
It is characterized by a first-in first-out memory.

[0042]

In the present invention, since one or more expansion memories can be arranged between the incoming line space switch and the outgoing line space switch, the expansion memory can be connected in the same manner as the buffer memory which has been conventionally used in the cell switching apparatus. It is possible to increase the capacity of the memory for storing cells and reduce the cell discard rate.

Further, in the second invention, the buffer control circuit controls the writing and reading of the cells by using the buffer memory and the extension memory. Therefore, when cells are intensively input to a specific outgoing line, conventionally, the buffer control circuit cannot manage the addresses of the cells stored in the buffer memory and discards the cells. However, by storing the cells in the extended memory, the cell discard rate can be reduced.

Further, in the third invention, since the address management means manages the address of the cell stored in either the buffer memory or the extension memory, more cells are stored than in the second invention. It is possible to further reduce the cell discard rate.

Further, in the fourth aspect of the invention, since the expansion memory stores the cell of the specific destination, the output space designated by the cell header is controlled by controlling the output space switch as in the conventional cell switching apparatus. You can output cells to lines.

Further, in the fifth aspect of the invention, since the expansion memory is composed of the first-in first-out memory, it becomes unnecessary for the buffer control circuit or the address management means to manage the addresses stored in the cells in the expansion memory. For this reason,
This facilitates the management method of the buffer control circuit or the address management means. Further, since the first-in first-out memory is currently on the market in general, it is possible to expand the memory capacity at low cost, and it is possible to easily realize a cell exchange device equipped with the expanded memory.

[0047]

【Example】

Example 1. In this embodiment, in the cell switching apparatus described in the conventional example, when a cell addressed to the outgoing line # 1 is intensively input, a cell switching apparatus newly provided with an expansion memory to prevent the cells from being discarded. The description will be given below. The external FIFO memory described below is an extended memory.

FIG. 1 is a block diagram showing a cell switching apparatus according to an embodiment of the present invention. FIG. 2 is a table provided in the write buffer selection circuit and is a table showing a storage destination of a cell for an output line. FIG.
FIG. 6 is a table provided in the write buffer selection circuit and showing the number of addresses stored in an address queue. FIG. 4 is a flow chart showing a cell writing procedure in a cell exchange apparatus having an external FIFO memory. FIG. 5 is a diagram showing the structure of the cell. FIG. 6 is a diagram for explaining the structure of the address queue. FIG. 7 is a diagram showing an address queue when cells are concentrated on the outgoing line # 1. FIG. 8 is a diagram for explaining the timing of starting to use the external FIFO memory. FIG. 9 is a flow chart showing a procedure for reading a cell in the read buffer selection circuit.
6 is a flowchart showing a procedure of reading a cell from an FO memory. FIG. 10 is a diagram for explaining the timing of restarting the cell storage operation in the buffer memory. FIG. 11 is a state transition diagram for explaining whether writing and reading of a cell are performed with respect to the buffer memory or the external FIFO memory.

In FIG. 1, reference numeral 20 denotes a burst judgment circuit, which judges the address storage status of the address queues 18 ₁ to 18 _m and judges whether to discard the cells input from the input lines 1 ₁ to 1 _n . The judgment result is notified to the write buffer selection circuit 16. 21 _{1 to} 21 _L are external F
The IFO memory is L (L ≧ 1) first-in / first-out memory capable of accumulating cells and reading the accumulated cells similarly to the buffer memories 11 _{1 to} 11 _p . A plurality of cells can be stored in one external FIFO memory 21 _{1 to} 21 _L. Since the other reference numerals are the same as those in the conventional example, the description thereof will be omitted here.

However, the incoming line space switch 13 includes an external FIFO memory 21 ₁ in addition to the buffer memories 11 _{1 to} 11 _p.
~ 21 _L can be selectively connected. Further, the output line space switch 14 includes an external F in addition to the buffer memories 11 _{1 to} 11 _p.
Connect the IFO memories 21 _{1 to} 21 _L to the specified output lines 2 ₁ to 2 _m.
Can be connected to. In addition to the buffer memories 11 _{1 to} 11 _p , the write buffer selection circuit 16 also has an external F
The IFO memories 21 _{1 to} 21 _L can be selected and controlled to store cells. Similarly, the read buffer selection circuit 19 can control the cell read from the external FIFO memories 21 _{1 to} 21 _L in addition to the buffer memories 11 _{1 to} 11 _p . In addition, the address queue 18
₁ to 18 _m can write the addresses of the cells stored in the external FIFO memories 21 _{1 to} 21 _L.

In FIG. 2, table A is a table provided in the write buffer selection circuit 16 and indicates whether the storage destination of the input cell is a buffer memory or an external FIFO memory for each output line. If the usage status shown and the storage destination is an external FIFO memory, the external FIFO memory
The memory number (any of # 0, # 1, ... #L) is stored.

In FIG. 3, table B is a table provided in the write buffer selection circuit 16 and shows the number of addresses stored in each address queue.

Next, referring to FIG. 4 and FIG.
A cell writing / reading procedure will be described with reference to FIG. As in the conventional example, the cell exchange apparatus in this embodiment is supplied with a cell including a header section including an outgoing line number as destination information as shown in FIG. 5 and a data section. The cells handled here are randomly input with a fixed length, and the cell input phase is adjusted before they are input to the incoming lines 1 ₁ to 1 _{n so} that the cell input from the front line has the same phase. Shall be supplied. Further, in order to simply explain the description of the embodiment, the number of incoming lines is n and the number of outgoing lines is m, and the buffer memories are 11 _{1 to} 11 11.
And eight to _8, up to 40 in one buffer memory
It is assumed that 96 cells can be written. Further, the external FIFO memory, and eight to 21 ₁ to 21 _8, the one external FIFO memories, and those capable of storing up to 8192 cells. Further, here, it is assumed that cell discard due to the shortage of the address queues 18 ₁ to 18 _m does not occur.

First, the cell writing procedure will be described with reference to the flowchart of FIG. When incoming cells 1 ₁ to 1 _n are input, the header processing circuits 10a ₁ 10 A _n provided in correspondence with the incoming line 1 ₁ to 1 _n, the detection of the outgoing line number from the header portion of the input cell Yes (S1). The write buffer selection circuit 16 of the buffer control circuit 15 refers to the table A of FIG. 2 and confirms whether the usage status corresponding to the outgoing line number detected in S1 is “0” or “1”. Perform (S2). When the usage status is "0", the write buffer selection circuit 16 further refers to the table B in FIG. 3 to confirm the current number of stored addresses in the address queue corresponding to the outgoing line number (S3). If the confirmed address storage number is smaller than the predetermined threshold value d1, it is confirmed whether or not there is a writable buffer memory (S5). Although not particularly shown in the figure, since a maximum of 4096 cells can be stored in each buffer memory in this embodiment, each buffer memory 11 _{1 to} 11 can be stored.
_If the number of cells stored in ₈ is held as a table, it is possible to easily check whether there is a writable buffer memory. If writable buffer memory is present in the above S5, with reference to the header processing circuits 10a ₁ 10 A _n, the incoming line space switch 13, for storing arriving incoming lines 1 ₁ to 1 _n and the cells of the cell Instruct to connect with the selected buffer memory. After connection, the cell is stored at the address specified by the storage control circuit of the buffer memory.

At this time, the write addresses of the buffer memories 11 _{1 to} 11 ₈ are sent from the storage control circuits 12 _{1 to} 12 ₈ to the address exchange circuit 17. This write address is selected from the addresses managed by the respective storage control circuits 12 _{1 to} 12 ₈ as free addresses.

The address exchange circuit 17 divides each input cell by destination output line while referring to the write buffer selection circuit 16, and outputs the write address of the buffer memory of the cell destined to the output line 2 ₁ to the address queue 18 ₁ To the address queue 18 ₂ for the write address of the buffer memory of the cell destined to the outgoing line 2 ₂ and to the end of the address queue 18 ₃ for the write address of the buffer memory of the cell destined for the outgoing line 2 _3. Write each (S8).

At this time, the write buffer selection circuit 16
Increments the value of the address queue in which the writing of the cell of table B of FIG. 3 is performed. If there is no writable buffer memory in the check of S5, the input cell is discarded (S7).

As described above, cells are written in the buffer memories 11 _{1 to} 11 ₈ as in the conventional example. If the cells addressed to the outgoing line 2 ₁ are intensively input, the addresses are not taken out and accumulated in the address queue 18 ₁ as shown in FIG. If the threshold value d1 is set to "10" here, when there are 10 or more addresses in the address queue 18 ₁ , one of the external FIFO memories 21 _{1 to} 21 _{8 is used} as a cell for the outgoing line 2 ₁ . As the external FIFO memory (in this example, the external FIFO memory 21 ₁ is used for the outgoing line 2 ₁ ), and then the cell is written to the selected external FIFO memory (S9).

However, the external FIFO memories 21 _{1 to} 21
_Since the number of ₈ (maximum 8 in this example) is also finite, the write buffer selection circuit 16 refers to the address of the external FIFO memory in table A of FIG. 2 and there is an external FIFO memory that is not used yet. It is checked (S6). If there is no unused external FIFO memory, it is confirmed whether or not there is a writable buffer memory (S5). If there is a writable buffer memory, the cell is written to that buffer memory and its write address. Is stored in the corresponding address queue (S8). If there is no writable buffer memory, the cell is discarded (S7).

If there is an unused external FIFO memory in the check of S6, the unused external FIFO memory is used.
The O memory is set as an external FIFO memory for a specific outgoing line (S9). With this setting, the write buffer selection circuit 16 updates the usage status of the outgoing line 2 ₁ (outgoing line # 1) of the table A to “1”, and the number # of the external FIFO memory 21 ₁ is changed.
This is done by storing 0. Thus, the external F
It is necessary to know which external FIFO memory of the IFO memories 21 _{1 to} 21 ₈ corresponds to which output line.

[0061] When writing cells to the external FIFO memory 21 _{and a} buffer selection circuit 16, the address exchange circuit 1 that writing the cell to the external FIFO memory 21 ₁
7, the address exchange circuit 17 notifies the address queue 18 ₁ of the address of the external FIFO memory 21 ₁ . The address queue 18 ₁ stores the notification address (S10).

In S2, the cell storage unit is set to the external FIF.
If it is the O memory, that is, if the usage status of the outgoing line 2 ₁ (outgoing line # 1) is “1” in the table A, it is determined whether the corresponding external FIFO memory is writable (S4). ). Since the access speed to the external FIFO memory is limited, the external FI can be stored in one cell slot.
The number of cells writable in the FO memory is limited. If a cell input from another input line has already been processed to be written to the external FIFO memory and the maximum number of times of writing has been reached, the external FIFO memory cannot be written. Further, even when the external FIFO memory is full, it is not possible to write to the external FIFO memory. If the result of determination in S4 is that writing is possible, the same processing as in S10 above is performed, and if writing is not possible, the processing proceeds to the processing in S5 and above.

Here, the structure of the address queue will be described with reference to FIG. In this embodiment, the number of buffer memories is eight, and the number of cells that can be stored in one buffer memory is 4096. Therefore, the address for one cell is: Two bytes are required as explained below. The address structure is described in FIG. 6 (A). Figure 6
According to (A), the lower 3 bits are used for the buffer memory 11 ₁ ...
11 represents the ₈ addresses, representing that the internal memory (buffer memory) or external memory (external FIFO memory) in the fourth bit. In the case of the internal memory, the bit is "0", and in the case of the external memory, the bit is "1". The remaining 12 bits are used to represent addresses 0 to 4095 inside the buffer memory. External FI
When a cell is written in the FO memory, the address becomes 1 byte. External FIFO memory 21 ₁ with lower 3 bits
To 21 representing the ₈ address. The 4th bit is '1'. The 5th to 8th bits are unused.

When cells are written in the buffer memory as described above, the buffer memory numbers (# 0, #
1 ,. ． ． ) And its address in the buffer memory are required to store 2 bytes of memory.
When written in the memory, a 1-byte address is required because it is sufficient to store the numbers (# 0, # 1, ...) Of the external FIFO memory. In this way, the external FIF
Only the O memory number need be stored because the FIFO memory has a function of first-in first-out data transfer.
This is because it is not necessary to be aware of the address in the IFO memory.

The address of the cell written in the buffer memory and the external FIFO are stored in one address queue.
Addresses of cells written in the memory can be mixed and stored. For example, according to FIG. 6B, at the head of the address queue, the outgoing line 2 ₁ (outgoing line # 1) stored at address 0 of the buffer memory 11 ₁ (buffer memory # 0) is stored.
The second is the address of the cell addressed to the output cell, and the second is the address of the cell addressed to the output line 2 ₁ (output line # 1) stored in the address 5 of the buffer memory 11 ₂ (buffer memory # 1). Further, some times after that, the address of the cell addressed to the outgoing line 2 ₁ (outgoing line # 1) stored in the external FIFO memory 21 ₁ (external FIFO memory # 0) is stored, and the next address is also externally stored. FIFO memory 21 ₁ (external FIFO
The address of the cell destined for the outgoing line 2 ₁ (outgoing line # 1) stored in the memory # 0) is stored. In this case, the cell address is simply the external FIFO memory number (# 0, #
1 ,. ． ． ) Is only remembered. In this way, when storing the address of the cell stored in the buffer memory, the number of the buffer memory and the address in the buffer memory must be stored at the same time, but in the case of the cell stored in the external FIFO memory, Only the external FIFO memory number. Since the first-in first-out memory constitutes the external FIFO memory, the system automatically determines where the cells are stored and outputs the data in order, so there is no need to manage the addresses.

FIG. 7 shows the status of addresses stored in the address queue when cells are concentrated on the outgoing line 2 ₁ (outgoing line # 1). According to FIG. 7, since the threshold value d1 is 10, the address of the cell written in the buffer memory is 2 per cell from the first address to 10.
It is stored in bytes. Since the eleventh and subsequent cells from the beginning are written in the external FIFO memory, the address is stored in 1 byte per cell. The write destination address described in FIG. 6 is represented by a binary number, but in FIG. 7, the address is represented by a hexadecimal number. External FIFO memory 21 ₁ (external FIFO memory # 0)
Is set for the outgoing line 2 _1, so cells for other outgoing lines cannot be stored. Therefore, FIG. 6 (A)
The address queue stores the address of the cell written in the external FIFO memory by using the lower 3 bits. By referring to Table A in FIG. 2, it is confirmed which external FIFO memory the cell is written in. can do. Therefore, it is possible to set only the lower 4th bit of the address of the cell written in the external FIFO memory and determine which external FIFO memory should take out the cell even if the lower 3bit is set to "0". Become. This is the end of the description of the cell writing process procedure.

Next, referring to the flow chart of FIG.
The cell reading procedure will be described below with reference to FIG. First, the read buffer selection circuit 19 takes out the stored addresses from the address queues 18 ₁ to 18 _m (S11). When the address is taken out, the read buffer selection circuit 19 confirms the flag of the lower 4th bit because the structure of the address stored in the address queue is as shown in FIG. 6 (A). When the flag is "0", the cell is written in any of the buffer memories 11 _{1 to} 11 ₈ , and the 2-byte address is fetched. If the lower 4th bit is “1”, the cell is the external FIFO memory 21.
₁ to 21 taken out 1-byte address because it is written to one of the _8. In S12, when the cell is written in the buffer memory, the storage control circuits 12 ₁ to 12 ₁ corresponding to the corresponding buffer memories 11 _{1 to} 11 ₈
The fetched address is sent to 12 ₈ and the output line space switch 14 is instructed to individually connect the buffer memories 11 _{1 to} 11 ₈ and the output lines 2 ₁ to 2 _m . As a result, the output line space switch 14 connects the corresponding buffer memories 11 _{1 to} 11 ₈ and the output lines 2 ₁ to 2 _m , respectively. Each of the storage control circuits 12 _{1 to} 12 ₈ sends the received address to the associated buffer memories 11 _{1 to} 11 ₈ as a read address, and thereafter manages the address as a free address. Each buffer memory 11 ₁ to 1
The cells read from 1 ₈ are output to the outgoing lines 2 ₁ to 2 _m of the destination designated by the respective headers (S1
3).

When the read buffer selection circuit 19 fetches an address, the address queues 18 ₁ to 18 _m notify the write buffer selection circuit 16 that the address has been fetched (S14). The write buffer selection circuit 1 which has received the notification of address fetching
6 is decremented by 1 from the number of addresses stored for each address queue in table B of FIG. As a result, the latest number of addresses for each address queue is stored in the table B (S19).

If the fetched address indicates the external FIFO memory in S12, the read buffer selection circuit 19 instructs the corresponding external FIFO memories 21 _{1 to} 21 ₈ to fetch the cell. Then, the output line space switch 14 is instructed to individually connect the external FIFO memories 21 _{1 to} 21 ₈ and the output lines 2 ₁ to 2 _m . This allows the outgoing line space switch 14
Connects the corresponding external FIFO memories 21 _{1 to} 21 ₈ and the output lines 2 ₁ to 2 _m , respectively. External FIFO memory 21 ₁
~ 21 cell read than ₈ is outputted to the outgoing line 2 ₁ to 2 _m of the destination specified in each header section (S1
5).

As described above, the address queue 18 ₁
Address fetched from ~ 18 _m is shows the external FIFO memory, the relevant external FIFO memory 21 ₂₁ to
When a cell is taken out from 1 ₈ , the address queue 18 ₁ ~
The number of addresses stored in 18 _m will decrease by one. In this embodiment, when the number of addresses stored in the address queue exceeds the threshold value 10 in the above description of the write procedure, cells are written to the external FIFO memory thereafter. However, if the cells are taken out from the buffer memory or the external FIFO memory and output from the corresponding output lines as described above, the number of addresses stored in the address queue is decreased by one and an empty area is generated in the buffer memory. Here, a threshold value d2 is further provided, and when the number of addresses stored in the address queue becomes smaller than the threshold value d2, the cell write destination is changed from the external FIFO memory to the buffer memory. Therefore, the external F
After taking out the cells from the IFO memories 21 _{1 to} 21 ₈ and outputting the cells to the corresponding outgoing lines 2 ₁ to 2 _m , the address queues 18 ₁ to 18 _m notify the write buffer selecting circuit 16 of the taking out of the addresses (S16). ). The write buffer selection circuit 16 refers to the table B of FIG. 3 to check whether the number of addresses stored in each queue is equal to or less than the threshold value d2 (S17). The write buffer selection circuit 16 changes the usage status of the corresponding output line in the table A of FIG.
It is changed to 0 ', and the number of the external FIFO memory is cleared (S18). Then, the write buffer selection circuit 16
Is subtracted from the number of addresses stored for each address queue in table B of FIG. 3 (S19).

The relationship between the number of addresses stored in each address queue and the threshold value d2 will be described with reference to FIG. The address queue 18 ₁ is initially shown in FIG.
, The number of addresses was stored at the threshold value d1 or more, but each time the cell was taken out, the number of addresses was decreased by _one and stored in the address queue 18 ₁ as shown in FIG. The number of addresses being set is up to the threshold value d2. At this time, the write buffer selection circuit 16
The usage status of the outgoing line 2 ₁ (outgoing line # 1) of the table A in FIG. 2 is changed to “0” (“0” indicates that the cell write destination is the buffer memory), and the external FIF
The number # 1 in the O memory 21 ₁ is cleared. As a result, the destination of the cell to be input next is output line 2 ₁ (output line #
1), the cells are buffer memories 11 _{1 to} 11 ₈
Will be written in either.

Taking the address stored in the address queue 18 ₁ for the outgoing line # 1 (outgoing line 2 ₁ ) in FIG. 7 as an example,
A procedure for taking out the cell of FIG. 9 will be described. Here, the threshold value d2 will be described as "5". Address queue 18
_When a cell is read in a state where 12 addresses are stored in ₁ , the address extraction starts from the rightmost address. The rightmost address indicates that the cell is written in the address "0" of the buffer memory 11 ₁ (buffer memory # 0).
The read buffer selection circuit 19 uses the buffer memory 11
₁ sends a fetched address to the storage control circuit 12 ₁ (buffer memory # 0) for the address of the memory control circuit 12 ₁ buffer memory 11 ₁ (buffer memory # 0) '
It is instructed to read cells from 0 '. The read cell is sent to the output line space switch 14, and the cell is output from the output line 2 ₁ (output line # 1). Then, the write buffer selection circuit 16 uses the address queue 1 of the table B of FIG.
-1 from the number of addresses in 8 ₁ (address queue # 1)
Therefore, it is updated to "11". Note that each time one address stored in the address queue is taken out, the address stored in the address queue is shifted to the right.

Next, the second address from the right of the address queue in FIG. 7 is fetched. (In FIG. 7, it is the second from the right, but it is actually shifted to the right, so the rightmost address is taken out.) This address also indicates that a cell is stored in the buffer memory, so the read buffer selection circuit 19 fetches a 2-byte address. The read buffer selection circuit 19 analyzes the address and sends the address to the storage control circuit 12 ₂ for the buffer memory 11 ₂ (buffer memory # 1). Storage control circuit 12 _2,
Buffer memory 11 so that the cell at address 5 is read
₂ Instruct (buffer memory # 1). The taken out cell is sent to the outgoing line space switch 14 and output from the outgoing line 2 ₁ (outgoing line # 1). Then, the write buffer selection circuit 16 uses the address queue 18 ₁ of the table B of FIG.
-1 from the number of addresses in (Address Queue # 1),
The number of addresses is updated to “10”.

As described above, the read buffer selection circuit 19 takes out the address queues of FIG. 7 in order, reads out whether the cells are stored in the buffer memory or the external FIFO memory, and confirms them. Get the address. When the write buffer selection circuit 16 confirms that the number of addresses in the address queue 18 ₁ (address queue # 1) of the table B of FIG.
The usage status flag of the outgoing line 2 ₁ (outgoing line # 1) of the table A is changed from "1" to "0". However, table A
The address of the external FIFO memory is
It is not cleared until all the cells stored in the memory have been read. When the write buffer selection circuit 16 detects that there are no cells stored in the external FIFO memory, the external FIFO addressed to the output line is read from the table A.
Clear the memory address. Then, the cell to be input next is written again in any of the buffer memories 11 _{1 to} 11 ₈ .

As described above, this embodiment writes cells into the internal buffer memory until the number of addresses stored in the address queue exceeds the threshold value d1 as shown in the state transition diagram of FIG. , Cells are read from the internal buffer memory (S20). When the number of addresses in the address queue exceeds the threshold value d1, the cells input thereafter are preferentially written in the external FIFO memory, and the reading is performed by the internal buffer memory (S21). Then, in the address queue, the address of the cell written in the internal buffer memory and the external F
Since the addresses of the cells stored in the IFO memory are mixed, the reading of the cells is performed from the external FIFO memory and the internal buffer memory, and the writing is preferentially written in the external FIFO memory.
Further, the number of addresses in the address queue is a threshold d.
When it becomes smaller than 2, the cell is again written to the internal buffer memory, and the reading is performed from the external FIFO memory and the internal buffer memory (S23). As described above, by providing the external FIFO memory capable of writing cells, the threshold d1 and the threshold d2 are set in consideration of the frequency of cell input and the frequency of concentration on a specific output line. With this setting, even if cells are temporarily concentrated on a specific outgoing line, it is possible to prevent cells from being discarded more than before.

Example 2. In the first embodiment, in the procedure of writing a cell in the buffer memory or the external FIFO memory (flow chart in FIG. 4), the cell write destination is the external FIFO.
If it is an O memory (S2 in FIG. 4), its external FIFO
Confirm whether the cell can be written in the memory (Fig. 4
S4), it was attempting to write to the buffer memory when writing was impossible (S5 in FIG. 4). When writing cells in this way, one external FIFO
When the memory overflows, the data is written in the buffer memory, so that one external FIFO memory corresponds to one output line. However, if a plurality of external FIFO memories are associated with one outgoing line, more cells can be written in the external FIFO memory than in the first embodiment when a certain number of cells addressed to the outgoing line are concentrated. Since it becomes possible, the probability of the cell being discarded can be reduced. In this embodiment, a case where a plurality of external FIFO memories are associated with one outgoing line will be described below. It should be noted that, in one external FIFO memory, cells addressed to the same outgoing line are not written, and cells addressed to different outgoing lines are never written together.

FIG. 12 is a flow chart showing a cell writing procedure in a cell exchange apparatus having an external FIFO memory, which is a processing procedure when a plurality of external FIFO memories are associated with one outgoing line. FIG. 12 shows the first embodiment described above.
The procedure is the same as that of the flow chart of FIG.
Check whether writing of the cell is possible to the external FIFO memory of, and when writing is not possible, an unused external FI
Check if the FO memory exists (S6), and if it exists,
A feature is that cells are written in the external FIFO memory (S10).

At this time, the write buffer selection circuit 16
Since it is necessary to manage a plurality of external FIFO memories for one output line, the table A having three or more dimensions is provided as shown in FIG. Table A in FIG.
Is the external FIFO memory 2 for outgoing line 2 ₁ (outgoing line # 1).
The case where 1 ₁ (external FIFO memory # 0) and external FIFO memory 21 ₃ (external FIFO memory # 2) are used is shown. As described above, when there are a plurality of external FIFO memories in which cells are written to one output line, the write buffer selection circuit 16 uses the external FIFO memory having a higher dimension when the usage status of the table in FIG. 13 is "1". Write cells. That is, the cell addressed to the outgoing line 2 ₁ (outgoing line # 1) in the table A of FIG. 13 is written in the external FIFO memory 21 ₃ .

Further, the cell is read out and the external FIF is
When all the cells written in the O memory have been read out, the external FIFO memory is released from the allocation for the specific output line. That is, table A in FIG.
At, the external FIFO memory 21 ₁ (external FIFO memory # 0) is cleared and the external FIFO memory 21 ₃ (external FIFO memory # 2) is shifted to a lower dimension.
When the number of addresses stored in the address queue becomes equal to or less than the threshold value d2, writing of cells into the buffer memory is started again. For example, table A in FIG.
Then, when the number of addresses stored in the address queue 18 ₁ of the outgoing line 2 ₁ becomes equal to or less than the threshold value d2, the write buffer selection circuit 16 determines that the outgoing line 2 ₁ (outgoing line # 1) is in the usage state of '1. It is changed from "0" to "0". However, outside F
Since the unread cells remain in the IFO memory 21 ₁ (external FIFO memory # 0) and the external FIFO memory 21 ₃ (external FIFO memory # 2), the outgoing line 2 ₁ (outgoing line # The number of the external FIFO memory for 1) is not cleared but stored as it is.

When a plurality of external FIFO memories can be used for one output line as described above, the capacity in which cells can be written increases, and the cell discard rate can be further reduced.

Example 3. In this embodiment, the conventional cell exchange apparatus is provided with an external FIFO memory capable of writing cells, and further, the address of the cell written in the external FIFO memory and the address of the cell written in the buffer memory are provided. An example with an address queue that can be stored separately will be described.

FIG. 14 is a block diagram showing an embodiment of the cell exchange apparatus. In the figure, 22 _{1 to} 22 _L are external FIs
It is an address queue for the FO memory and has a one-to-one correspondence with the external FIFO memories 21 _{1 to} 21 _L. However, the external FIFO memory address queues 22 _{1 to} 22
_L can also store the address of the cell written in the buffer memory. The external FIFO memory address queue is composed of a readable / writable volatile memory such as a RAM (random access memory). Since other reference numerals are the same as those in FIG. 1 described in the first embodiment, the description thereof will be omitted.

FIG. 15 shows the write buffer selection circuit 16
FIG. 6 is a diagram of a table showing the number of addresses stored in an external FIFO memory address queue included in FIG. Table C in FIG. 15 shows the number of stored addresses for each external address queue. External FI
When cells are written in the FO memories 21 _{1 to} 21 _L , the write buffer selection circuit 16 increments the number of addresses in the corresponding external address queue of table C by +1. On the other hand, the read buffer selection circuit 19 causes the external FIFO
When the address of the memory address queue is fetched, the write buffer selection circuit 16 is notified of the fetch from the address queue from which the address is fetched,
The write buffer selection circuit 16 subtracts one from the number of addresses in the corresponding external FIFO memory address queue of the table C.

FIG. 16 shows an external FIFO memory and an external FI.
6 is a flowchart showing a cell writing procedure in a cell exchange apparatus including an FO memory address queue. FIG. 17
FIG. 17 is a flowchart showing a cell writing procedure following FIG. 16. FIG. 18 is a diagram showing an address queue when cells are concentrated on the outgoing line # 1. FIG. 18A shows the outgoing line 2 ₁ (outgoing line # 1) stored in the address queue 18 _1.
It shows the address of the addressed cell. FIG. 18B shows the address of the cell addressed to the outgoing line 2 ₁ (outgoing line # 1) stored in the external memory address queue 22 ₁ .
The addresses shown in FIGS. 18A and 18B are expressed in hexadecimal.

When cells are intensively input to the outgoing line 2 ₁ (outgoing line # 1), the cells written in the buffer memory cannot be read in time, and the address queue 18 as shown in FIG. 10 addresses are accumulated in ₁ . In this embodiment, the threshold value d1 is set to "10" as in the first embodiment. Therefore, outgoing line 2 ₁ (outgoing line # 1)
When the eleventh cell is input to the destination, the write buffer selection circuit 16 searches for an unused one from the external FIFO memories 21 _{1 to} 21 _L and writes the cell in the external FIFO memory. At this time, the address of the written cell is stored in the external FIFO memory address queue corresponding to the external FIFO memory in which the cell was written. In the example of FIG. 18B, the external FIFO memory 21 ₁
Addresses of cells written in (external FIFO memory # 0) are stored in order from the right end. In the example of FIG. 18B, the address of the cell written in the address 5 of the buffer memory 11 ₅ (buffer memory # 4) is stored at the 257th position, but as described above, the external FI
This is because the FO memories 21 _{1 to} 21 _L also store the addresses of the cells written in the buffer memory.

Next, the timing for starting to use the external FIFO memory will be described. FIG. 19 shows an external FIFO
It is a figure explaining the timing which starts using a memory. In FIG. 19, cells addressed to the outgoing line 2 ₁ are intensively input, and the cells are not output to the address queue 18 ₁ (the address queue 18 ₁ corresponds to the outgoing line 2 ₁ ) as a buffer memory. The case where the cell addresses stored in 11 _{1 to} 11 _p are stored is shown. Also in this embodiment, if the threshold value d1 is set to "10" as in the first embodiment, if the number of cells stored in the address queue 18 ₁ becomes 10 or more, the eleventh and subsequent cells will be External FIF
O memory 21 ₁ (External FIFO memory 21 ₁ is output line 2 ₁
(Allocated as the write destination of the cell for writing) is preferentially written, and the address at this time is stored in the address queue 22 ₁ for the external FIFO memory. That is, when cells addressed to a specific outgoing line are intensively input and the number of addresses in the address queue corresponding to the specific outgoing line is accumulated over the threshold value d1, the external FIFO from the next input cell is input.
It is written in the O memory, and the address at this time is the external F
It is stored in the external FIFO memory address queue corresponding to the IFO memory. Further, assuming that the external FIFO memory is composed of a high-speed memory, and the external FIFO memory can be written k times during a period of one cell slot,
Up to k cells can be written in the external FIFO memory in one cell slot. If more than k cells addressed to the same outgoing line arrive at the same time, more than k cells are written in the buffer memory. However,
The address of the buffer memory is stored in the external FIFO memory address queue.

A cell writing procedure will be described below with reference to FIGS. 14, 15, and 18 according to the flowcharts of FIGS. In this embodiment, it is assumed that the number of incoming and outgoing lines is 8 and the buffer memory also has 8. All buffer memories shall be shared by all incoming lines and all outgoing lines. When the buffer capacity per one buffer memory is B cells, the total buffer capacity is 8 B cells. It is assumed that writing to the buffer memory can be performed once and reading can be performed three times in one cell slot. It is assumed that the address queue has a memory capacity of 8 B cells corresponding to each outgoing line. Therefore, although cell discard may occur due to lack of buffer memory, cell discard does not occur due to insufficient memory capacity of the address queue. Further, there are eight external FIFO memories, and the buffer capacity per external FIFO memory is 256 cells. Further, although reading from the external FIFO memory in one cell slot is performed once, writing can be performed k times. The address queue for the external FIFO memory is used to store the write destination of the cell when the external FIFO memory is used.

The processing of S1 to S3, S5, and S7 to S8 of FIG. 16 is processing for writing a cell because there is a free area in the buffer memory and storing the cell address in the address queue. This is the same as the processing of S1 to S3, S5, and S7 to S8 of FIG. 4 described in the first embodiment.

In the process of S3, cells addressed to the outgoing line 2 ₁ (outgoing line # 1) are intensively input as shown in FIG.
When the number of addresses stored in the address queue 18 ₁ is equal to or greater than the threshold value d1 (10), the write buffer selection circuit 16 causes the external FIFO memories 21 _{1 to} 21 _{8 to} operate.
To search for unused external FIFO memory. That is, the write buffer selection circuit 16 refers to the table A of FIG. 2 described in the first embodiment and searches for an external FIFO memory that is not registered in the external FIFO memory (S6). For example, external FIFO memory 21 ₁
Is unused, the write buffer selection circuit 16
The number "# 0" of the external FIFO memory 21 ₁ is registered as the external FIFO memory for the outgoing line 2 ₁ (outgoing line # 1) of the table A in FIG. 2 (S9a). Then, the write buffer selection circuit 16 sets the incoming line space switch 13 to the external FIFO.
Connect to the O memory 21 ₁ and connect the cell to the external FIFO memory 2
Writing to 1 _1, the external FIFO memory 21 ₁ transmits an address written cell the address exchange circuit 17,
The address exchange circuit 17 uses the received address as shown in FIG.
As shown at the right end of (B), "08" (indicating the address of the cell written in the external FIFO memory 21 ₁ (external FIFO memory # 0)) is notified to the address exchange circuit 17, and the address exchange circuit 17 is notified. Stores the address in the external FIFO memory address queue 22 ₁ (S10a). Further, the write buffer selection circuit 16
Adds 1 to the number of addresses in the external FIFO memory address queue 22 ₁ (external address queue # 0) in table C of FIG.

In the process of S2, the write buffer selection circuit 16 checks whether or not the write destination for the destination of the input cell is the external FIFO memory by referring to the table A in FIG. For example, when the cell is addressed to the outgoing line 2 ₁ (exit line # 1), the usage status is “1” according to the table A of FIG.
The input cell is written in the memory. External FI
If the cell can be written in the FO memory 21 ₁ (external FIFO memory # 0) (S4), the input cell is written in the external FIFO memory 2 ₁ and the address in which the cell is written is notified to the address exchange circuit 17. Then, the address exchange circuit 17 stores the address in the external FIFO memory address queue 21 ₁ (S10a).

For example, as shown in FIG.
The cell input to the outgoing line 2 ₁ (outgoing line # 1) is written in the external FIFO memory 21 ₁ (external FIFO memory # 0), and the address “08” is stored in the external FIFO memory address queue 22 ₁ Memorized in. If the external FIF
If the cell cannot be written to the O memory (S
4) It is checked whether or not there is a writable buffer memory (S21), and if there is a writable buffer memory, the cell is written in the buffer memory, and the written address is stored in the address exchange circuit by the storage control circuit 12 _1. 17 is sent to the address exchange circuit 17
Is the corresponding external FIFO memory address queue 2
The address is stored in 2 ₁ . For example, FIG. 18 (B)
According to the above, since the external FIFO memory can store 256 cells and cannot store any more cells, the cells are stored in the buffer memory 11 ₅ (buffer memory #
4) Write to address 5 and set the cell address to 257
Remember the second. In this way, both the address of the cell written in the external FIFO memory 21 _{1 to} 21 _L and the address of the cell written in the buffer memory 11 _{1 to} 11 _p are stored in the external FIFO memory address queues 22 _{1 to} 22 _L. Can be mixed and stored. Note that S20
If there is no writable buffer memory in, the cell is discarded (S22).

Further, in the check of S3, the number of addresses stored in the address queue is the threshold value d1.
Even if the above is the case, if all the external FIFO memories are already used by the destinations other than the destination of the cell to be written, the cell is written in the buffer memory. If writing is not possible, the cell is discarded here (S7).

In the above description, when the cell is written to the buffer memory or the external FIFO memory, the write buffer selection circuit 16 selects the table B (FIG. 3) or the table C (FIG. 15). Add 1 to the number of addresses in the corresponding address queue. This is the end of the description of the write procedure in the cell exchange apparatus including the external FIFO memory and the address queue for the external FIFO memory.

Next, the external FIFO memory and the external FIFO
The reading procedure in the cell switching apparatus having the memory address queue will be described below. 20
6 is a flowchart showing a cell extracting procedure in a cell switching apparatus including an external FIFO memory and an address queue for the external FIFO memory. FIG. 21 is a diagram of a table showing the read destinations included in the read buffer selection circuit. Table D in FIG. 21 shows an address queue in which the read buffer selection circuit 19 takes out cells. In other words, the address queues 18 ₁ to 18 ₁
Address queue 22 ₁ for 18 _m and external FIFO memory
There are two types of ~22 _L, it indicates how extract the address from either the address queue. An output line whose read status is "1" from the table D fetches an address from the designated external FIFO memory address queue. For example, in the table D of FIG. 21, the cell addressed to the outgoing line 2 ₁ (outgoing line # 1) is the address queue 22 for the external FIFO memory.
_{1 Take} out address from external FIFO memory address queue # 0.

FIG. 22 is a diagram for explaining the timing of resuming cell storage in the buffer memory. As described above, when cells destined for the outgoing line 2 ₁ are concentrated and the number of addresses stored in the address queue 18 ₁ becomes equal to or greater than the threshold value d1, the external FIFO memory 21 ₁ (external FIFO memory The cell is written in the memory # 0) and the write address is written to the address queue 22 for the external FIFO memory.
₁ (External FIFO memory address queue # 0). After that, all the addresses stored in the address queue 18 ₁ are fetched by the read buffer selection circuit 19, and subsequently, the stored addresses are fetched from the external FIFO memory address queue 22 ₁ . When the concentration of cells destined to the outgoing line 2 ₁ is stopped and the number of addresses in the external FIFO memory 22 ₁ becomes smaller than the threshold value d2, the arriving cells destined to the outgoing line 2 _{1 are transferred} to the external FIFO memory 21 ₁ (external FIFO memory). #
0) instead of 0). Also, the write address is written to the normal address queue 18 ₁ . For example, if the threshold value d2 is set to "5" here, writing of cells to the buffer memory is restarted when the external FIFO memory address queue becomes smaller than 5 in FIG.

Next, referring to the flow chart of FIG.
The cell reading procedure will be described with reference to FIG.
First, the read buffer selection circuit 19 refers to the table B of FIG. 21 to specify the address queue for each outgoing line (S30). For example, according to the table B of FIG. 21, the read status of the outgoing line 2 ₁ (outgoing line # 1) is “1”. As a result, the cell addressed to the outgoing line 2 ₁ fetches the head address from the external FIFO memory address queue 22 ₁ (external FIFO memory address queue # 0). At this time, the read buffer selection circuit 19 refers to the table C (FIG. 15) of the write buffer selection circuit 16 and confirms whether or not the number of addresses stored in the external FIFO memory address queue 22 ₁ is zero. Perform (S33). If the number of addresses is not 0, external FIFO
The leading address of the O memory address queue 22 ₁ (external FIFO memory address queue # 0) is taken out. Then, the cell is read from the external FIFO memory indicated by the address (S37). For example, FIG. 18 (B)
If an address such as is stored in the external FIFO memory address queue 22 ₁ , the _first address is the external FIFO memory 21 ₁ (external FIFO memory #
0) indicates that the cell is written,
The read buffer selection circuit 19 uses the output line space switch 1
4 is connected to the external FIFO memory 21 ₁ , the cell is read, and the read cell is output from the output line 2 ₁ (output line # 1) (S37).

Although not shown in the flowchart of FIG. 20, the external FIFO memory address queue 22 ₁ notifies the write buffer selection circuit 16 that the address has been fetched by the read buffer selection circuit 19. . Upon receiving this notification, the write buffer selection circuit 16 subtracts 1 from the number of addresses in the corresponding external FIFO memory address queue from the table C in FIG. Then, when the result obtained by subtracting 1 from the number of addresses is smaller than the threshold value d2 (S38), the write buffer selection circuit 16 writes subsequent input cells into the buffer memories 11 _{1 to} 11 ₈ . The usage status corresponding to the corresponding outgoing line in Table A is changed to "0" (S39). However, even if the usage status is changed to "0", the number of the external FIFO memory is not cleared until all the addresses written in the external FIFO memory are taken out.

In the check of S38, the external FI
If the number of addresses stored in the FO memory address queue is greater than or equal to the threshold value d2, the external FIFO is used as it is.
The cell is preferentially written to the O memory, and its address is stored in the address queue for the external FIFO memory. For example, in FIG. 18B, 258 addresses are external
O cell outgoing lines 2 ₁ addressed to since they are stored in the memory address queue number of addresses stored becomes the threshold d2 = 5 preferentially written to the external FIFO memory 21 _1.

If read is set in the address queue in the check of S30, that is, the read status of the cell addressed to the output line 2 ₁ (output line # 1) of the table D in FIG. 21 is selected as the read buffer. If the result confirmed by the circuit 19 is “0”, the read buffer selection circuit 19 further determines the write buffer selection circuit 1
Referring to the table A of FIG.
It is confirmed whether or not the write destination of the cell input to ₁ (outline # 1) is the external FIFO memory. External FIFO
If the memory is the write destination, the usage status is'
It is 1 '(S31). If the check result is "1", the table B of FIG. 3 is checked whether the number of addresses stored in the address queue 18 ₁ is 0 or more (S35). If the number of addresses stored in the address queue 18 ₁ (address queue # 0) of Table B in FIG. 3 is 0 or more, the read buffer selection circuit 19 takes out the head address of the address queue and indicates the address. Buffer memory 11 ₁ ~
An instruction to take out a cell and an address are given to 11 ₈ , and the storage control circuits 12 _{1 to} 12 ₈ read cells from the buffer memories 11 _{1 to} 11 ₈ based on the address. Read cell passes through the outgoing line space switch the read buffer selection circuit 19 is connected, output from the outgoing line 2 ₁ ~2 ₈ (S32). For example, the head address “0000” of the address queue of FIG. 18A is read out and taken out from the buffer selection circuit 19. Since this address indicates the buffer memory 11 ₁ (buffer memory # 0),
The read buffer selection circuit 19 passes this address to the storage control circuit 12 ₁ . The storage control circuit 12 ₁ analyzes this address and extracts a cell from the address 0 of the buffer memory 11 ₁ (buffer memory # 0). The taken out cell is passed to the incoming line space switch 14 and output from the outgoing line 2 ₁ .

If the number of addresses stored in the address queue 18 ₁ is 0 in the check of S35, the read destination of the cell to be subsequently output to the outgoing line 2 ₁ (outgoing line # 1) is the external FIFO memory. It is set in the dedicated address queue (S36). The setting is the read buffer selection circuit 1
6 is equipped with the outgoing line 2 ₁ of table D in FIG.
This is performed by changing the reading status of 1) from "0" to "1". Further, the read buffer selection circuit 1
2 is provided in the write buffer selection circuit 16.
21 is referred to, the number of the external FIFO memory in which the cell input to the outgoing line 2 ₁ (outgoing line # 1) is written is referred to, and this number is taken to the outgoing line 2 of the table D in FIG.
_It is stored as the number of the address queue for the external FIFO memory of ₁ (outline # 1). The subsequent processing is the same as the processing in S37 to S39 described above.

In the check of S31, the read buffer selection circuit 19 refers to the table A of FIG. 2 provided in the read buffer selection circuit 16, and if the cell write destination is not the external FIFO memory (cell write If the destination is not the external FIFO memory, the use status is set to '0'), the head address of the address queue is read and the address fetched by the buffer selection circuit 19 is set as described in S32 above. Originally, the address is passed to the storage control circuits 12 _{1 to} 12 ₈ ,
The storage control circuits 12 _{1 to} 12 ₈ take out cells from the buffer memories 11 _{1 to} 11 ₈ based on the addresses, and output lines 2 ₁ to from the output line space switch 14 connected from the read buffer selection circuit 19 The cell is output from 2 ₈ .

When the number of addresses stored in the address queue for the external FIFO memory from which the cell is to be taken out is 0 in the check in S33, the read buffer selection circuit 19 uses the table D in FIG.
The read status for the corresponding outgoing line is changed to the address queue, that is, '0', and the same processing as S32 is performed.

As described above, a state transition diagram is provided in which the address queue for the external FIFO memory is provided and either the buffer memory or the external FIFO memory is selected as the cell write destination by using the threshold values d1 and d2. The result is shown in FIG.

When cells are not concentrated on a specific output line, the input cell is written in the buffer memory and the written address is stored in the address queue, as in S35. When the cell is read, the address is read from the address queue, and the cell indicated by the address is also stored in the buffer memory. Therefore, the cell is read from the buffer memory and output from the corresponding output line.

When cells are intensively input to a specific outgoing line, addresses are not taken out to the address queue and are gradually accumulated, and the threshold value d1 set by the system is exceeded. In S36 in such a state,
The cells are preferentially written to the external FIFO memory. The address of the cell written in the external FIFO memory is written in the external FIFO memory address queue. To read a cell, the cell written in the buffer memory must be read first. Therefore, the address is fetched from the address queue, and the cell indicated by the address is the buffer memory. Read out Output from the corresponding output line.

In the state of S36, the address is not newly stored in the address queue, and the address is preferentially fetched. Therefore, the address stored in the address queue becomes empty. Occurs.
In this state of S37, the input cell is
It is preferentially written in the external FIFO memory, and the address at this time is also written in the external FIFO memory address queue. And the address is fetched by external FIFO
It is performed from the memory address queue, but since the fetched address may indicate the external FIFO memory or the buffer memory, the cell is read from either the external FIFO memory or the buffer memory. Output from the corresponding outgoing line.

When addresses are fetched from the external FIFO memory address queue in this way, a state occurs in which the number of stored addresses becomes less than or equal to the threshold value d2 set in advance by the system. In S38 in such a state, the input cell is written in the buffer memory again, and the address at this time is also written in the address queue. The address preferentially fetched from the address queue for the external FIFO memory may indicate the external FIFO memory or the buffer memory. Therefore, the cell is read from the external FIFO memory or the buffer memory and the corresponding output is read. Output from the line. Then, when the addresses are further taken out from the external FIFO memory address queue, a state occurs in which the addresses stored in the external FIFO memory address queue become empty. In this state, the state again transits to the state of S35 as described above. In this way, the probability of discarding cells is made smaller than in the past while transitioning to four states based on the number of addresses stored in the address queue and the address queue for the external FIFO memory.

Example 4. In the write procedure of FIGS. 16 to 17 described in the third embodiment, the cell write destination is designated to the external FIFO memory (S
2) There is no free space in the external FIFO memory, or n or more writable cells are input to the external FIFO memory in one cell slot and writing cannot be performed (S4). If there is no memory (S20), the cell has been discarded (S22). This is the external FIF corresponding to one outgoing line
This is because there is only one O memory. It is also possible to provide a plurality of external FIFO memories corresponding to one output line. As a result, even in the case described above, the probability that cells are discarded can be further reduced.

FIG. 24 shows an external FIF corresponding to one outgoing line.
When a plurality of O memories are provided, the processing procedure of the changed portion in the processing procedure of FIGS. 16 to 17 described in the third embodiment is illustrated. According to FIG. 24, in the flow chart of FIG. 16, the cell write destination is set to the external FIFO memory (S2), the cell cannot be written to the external FIFO memory (S4), and the cell is also written to the buffer memory. If it is impossible (S20), the process branches to the process of S6 to check whether there is an unused external FIFO memory (S6), and if there is an unused external FIFO memory, it tries to write. The external FIFO memory for the destination indicated by the cell is set, and further the corresponding external FI is set.
The address queue for the FO memory is also set up for that destination. Although the above setting is performed by the write buffer selection circuit 16, only one external FIFO memory can be set for one output line in the table A of FIG. 2 described in the third embodiment. ), Such as table A), in which a plurality of external FIFO memories can be set for one outgoing line is newly provided. FIG. 25 (A)
According to Table A of the outside F for outgoing line 2 ₁ (outgoing line # 1)
The IFO memory 21 ₁ (external FIFO memory # 0) and the external FIFO memory 21 ₃ (external FIFO memory # 2) are set. When writing a cell, the write buffer selection circuit 16 confirms the usage status of the table A, and if the usage status is "1", writes to the external FIFO memory in which the first dimension is set high. Figure 2
5 (A) In Table A, when writing the cell input to the outgoing line 2 ₁ (outgoing line # 1), the external FIFO memory 21
_{Since the} external FIFO memory 21 ₃ (external FIFO memory # 2) has a higher dimension than ₁ (external FIFO memory # 0), the write buffer selection circuit 16 sets the input line space switch 13 to the external FIFO memory 21 ₃ (external FIFO memory). Connect to # 2) and write the cell.

When reading a cell, in the third embodiment, the read buffer selection circuit 19 refers to the table D in FIG. 21, and the read status for the output line is "1".
, The cell address is fetched from the external FIFO memory address queue indicated by the set number. However, since only one external FIFO memory address queue number can be set for one output line in the table D of FIG. The number of the address queue for the external FIFO memory must be set.

The read buffer selection circuit 19 is shown in FIG.
When taking out the cell addressed to the outgoing line 2 ₁ (outgoing line # 1) by referring to the table D of (B), the address of the external FIFO memory address queue whose dimension is set low is taken out, and the corresponding external FIFO is taken out. Read a cell from memory.
In the table D of FIG. 25B, the external FIFO memory address queue 22 ₁ (external FIFO memory address queue # 0) is the external FIFO memory address queue 22 ₃ (external FIFO memory address queue # Since the dimension is set lower than that of 2), the read buffer selection circuit 19 extracts the cell address from the external FIFO memory address queue 22 ₁ (external FIFO memory address queue # 0), and reads the external address indicated by the address. The cell is taken out from the FIFO memory 21 ₁ , passes through the outgoing line space switch 14, and is output from the outgoing line 2 ₁ (outline # 1).

When addresses are fetched from the external FIFO memory address queue, the external FIFO memory address queue becomes empty eventually. The empty address queue for the external FIFO memory is cleared from the table D in order to make it unused, and all the external FIFO memories set to the dimension one higher for the relevant outgoing line are set one by one. Shift the dimension down.

For example, in the table D of FIG.
When all the addresses are fetched from the external FIFO memory address queue 22 ₁ (external FIFO memory address queue # 0) of the outgoing line 2 ₁ (outline # 1), the address queue number # 0 is cleared. Then, the number # 2 of the external FIFO memory address queue 22 ₃ (external FIFO memory address queue # 2) set to a higher dimension than that is shifted to the next lower dimension and set. At this time, the output line 2 ₁ of the table A in FIG.
It is set that (external FIFO memory # 0) is in use. Therefore, the read buffer selection circuit 19
When the address is fetched by the external FIFO memory address queue 22 ₁ (external FIFO memory address queue # 0), the write buffer selection circuit 1
6, the write buffer selection circuit 16 notifies the external FIFO memory address queue 21 ₁ (external FIFO memory address queue # 0)
-1 is subtracted from the number of addresses stored in. When the number of addresses as a result of the subtraction becomes 0, no address is stored in the external FIFO memory address queue 21 ₁ (external FIFO memory address queue # 0). Table A in (A)
Of the external FIFO memory 21 ₁ (external FIFO memory # 0) corresponding to the outgoing line 2 ₁ (external line # 1) of the table A
Clear more. When cleared, the write buffer selection circuit 16 shifts the external FIFO memory having a higher dimension than the external FIFO memory 21 ₁ (external FIFO memory # 0) one by one to a lower dimension. The external FIFO memory 21 ₁ cleared by this (external FIFO memory # 0)
Becomes unused. Further, the usage status for each outgoing line in the table A of FIG. 25A is cleared ('0') when all cells are taken out from all external FIFO memories used for the outgoing line. . In addition, FIG.
The usage status for each outgoing line in the table D in (B) is cleared ('0') when the addresses of all cells are fetched from the address queues for all external FIFO memories used for the outgoing line. To be done.

Example 5. Although the external FIFO memory described in the first to fourth embodiments is composed of the first-in first-out memory, a circuit similar to the storage control circuits 12 _{1 to} 12 _P for the internal buffer memory is used for the external memory. External memory is random access memory (RAM)
It may be.

[0115]

According to the first invention, the expansion memory can be arranged between the incoming line space switch and the outgoing line space switch. Also, the extended memory is parallel to the buffer memory. For this reason, it becomes possible to write and read cells to and from the extended memory as well as the buffer memory that has been conventionally present in the cell exchange apparatus. For example, if cells are concentrated on a specific outgoing line,
Since cells can be written to the extended memory as well as the buffer memory, the probability of discarding cells can be reduced.

Further, in the second invention, the buffer control circuit controls the writing and reading of cells to the extension memory. Therefore, the extended memory for writing the cells is automatically selected like the buffer memory existing in the conventional cell switching apparatus, and the address of the written cell is also managed by the buffer control circuit. Further, the reading of cells from the extended memory is also automatically performed by the buffer control circuit. As described above, there is an effect that the expansion memory can be easily provided without significantly changing the components of the buffer control circuit.

Further, in the third invention, since the address management means manages the addresses of the cells stored in the buffer memory and the extension memory when the extension memory is used, the circuit scale of the internal buffer control circuit can be reduced.

Further, in the fourth aspect of the invention, when the cells addressed to a certain outgoing line are intensively input, the expansion memory stores the cells addressed to the outgoing line. As a result, it is possible to reduce the discard rate when a load is concentrated such that cells are concentrated on a certain outgoing line as described above.

Further, in the fifth invention, the expansion memory in the fourth invention is constituted by the first-in first-out memory. Therefore, there is no need to manage the unused address of the expansion memory, and the buffer control circuit and the address management means manage only the expansion memory number, not the expansion memory address, so that an appropriate output line can be obtained. The cells can be output in the proper order.

[Brief description of drawings]

FIG. 1 is a block diagram showing a cell exchange apparatus according to an embodiment of the present invention.

FIG. 2 is a table diagram showing write destinations of cells to output lines provided in a write buffer selection circuit.

FIG. 3 is a table showing the number of addresses stored in an address queue included in the write buffer selection circuit.

FIG. 4 is a flowchart showing a cell writing procedure in the cell exchange / exchange device including the external memory according to the first embodiment.

FIG. 5 is a diagram showing the structure of a cell.

FIG. 6 is a diagram showing a structure of an address queue in the present invention.

FIG. 7 is a diagram showing an address queue when cells are concentrated on an outgoing line # 1 according to the present invention.

FIG. 8 is a diagram illustrating a timing at which the external FIFO memory according to the first embodiment is used.

FIG. 9 is a flowchart showing a procedure for taking out a cell from a buffer memory or an external FIFO memory for each output line in the read buffer selection circuit of the first embodiment.

FIG. 10 is a diagram illustrating the timing of resuming cell storage in the buffer memory according to the first exemplary embodiment.

FIG. 11 is a state transition diagram of writing and reading of cells in the first embodiment.

FIG. 12 is a flowchart showing a cell writing procedure in the cell exchange apparatus including the external FIFO memory according to the second embodiment.

FIG. 13 is a table diagram showing a cell write destination with respect to an output line provided in the write buffer selection circuit of the second embodiment.

FIG. 14 is a block diagram showing a cell exchange apparatus according to a third embodiment.

FIG. 15 is a table diagram showing the number of addresses stored in an external FIFO memory address queue provided in the write buffer selection circuit of the third embodiment.

FIG. 16 shows an external FIFO memory and external FI according to the third embodiment.
6 is a flowchart showing a cell writing procedure in a cell exchange apparatus including an FO memory address queue.

FIG. 17 is a flowchart showing the continuation of FIG. 16;

FIG. 18 is a diagram showing an address queue when cells are concentrated on an outgoing line # 1 in the third embodiment of FIG. 18;

FIG. 19 is a diagram illustrating a timing at which the external FIFO memory according to the third embodiment starts to be used.

FIG. 20 shows an external FIFO memory and external FI according to the third embodiment.
7 is a flowchart showing a cell reading procedure in a cell switching apparatus having an address queue for FO memory.

FIG. 21 is a table diagram showing a read destination for each output line provided in the read buffer selection circuit of the third embodiment.

FIG. 22 is a diagram illustrating a timing at which cell writing is restarted in the buffer memory according to the third embodiment.

FIG. 23 is a diagram showing a state transition diagram of writing and reading of a cell according to the third embodiment.

FIG. 24 is a flowchart showing a cell writing procedure of the fourth embodiment.

FIG. 25 is a table diagram showing an external FIFO memory corresponding to each output line provided in the write buffer selection circuit of the fourth embodiment and a read-out external FIFO memory provided for each output line in the read buffer selection circuit. It is a table figure which has shown the address queue for use.

FIG. 26 is a block diagram showing a cell switching device in a conventional example.

FIG. 27 is a time chart showing the timing of signals in each part of the block diagram shown in the conventional example.

FIG. 28 is a time chart showing the timing of signals in each part of the block diagram shown in the conventional example.

FIG. 29 is a time chart showing the timing of signals in each part of the block diagram shown in the conventional example.

FIG. 30 is a time chart diagram showing an enlarged main part of a conventional example.

FIG. 31 is a time chart diagram showing an enlarged main part of a conventional example.

[Explanation of symbols]

1 ₁ to 1 _n incoming line, 2 ₁ to 2 _n outgoing line, 10a ₁ to 10
a _n header processing circuit, 11 ₁ to 11 _p buffer memory, 13 incoming space switch, 14 output line space switch, 15 a buffer control circuit, 16 a write buffer selection circuit, 17 an address exchange circuit, 18 ₁ ~ 18 _m address queue, 19 read buffer selection circuit, 2
0 burst judgment circuit, 21 _{1 to} 21 _L external FIFO
Memory, 22 _{1 to} 22 _L Address queue for external FIFO memory.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhito Sasaki 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corp. Communication Systems Research Institute (72) Hirotoshi Yamada 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corporation (72) Inventor Kazuno Oshima 5-1-1, Ofuna, Kamakura City Mitsubishi Electric Co., Ltd.

Claims (5)

[Claims] 1. A plurality of incoming lines into which a cell consisting of a data part and a header part including its destination information is input, and a plurality of outgoing lines from which the cell is output according to the destination specified in the header part. , A header processing circuit which is provided corresponding to each of the incoming lines and detects the outgoing line of the destination from the header part of the cell input through the incoming lines, and the cell is written by designating an address. A plurality of buffer memories capable of reading the cells irrespective of the writing order by designating an address; and an input line space switch for selectively connecting the header processing circuit to a predetermined buffer memory. An output line space switch for selectively connecting the buffer memory to a predetermined output line; and a buffer in which the cell is written by controlling the input line space switch. The memory is selected, the address of the written cell in the buffer memory is managed for each destination of the cell, the output line space switch is controlled based on the address, and the cell is designated by its header part. In a cell exchange device equipped with a buffer control circuit for outputting in a predetermined order to the output line, an expansion memory can be arranged in parallel with the buffer memory between the input line space switch and the output line space switch. A cell exchange device characterized by the above. 2. The cell exchange apparatus according to claim 1, wherein the buffer control circuit controls writing and reading of cells using the buffer memory and the expansion memory. 3. The cell switching device according to claim 1, further comprising address management means for managing an address of a cell stored in either the buffer memory or the extension memory. Exchange device. 4. The cell switching device according to claim 1, wherein the expansion memory stores a cell of a specific destination. 5. The cell exchange apparatus according to claim 1, 2 or 3, wherein the expansion memory is a first-in first-out memory.