JP2561046B2 - Switching system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching system for exchanging time division multiplex communication information such as voice and data by using a fixed length cell having a header for routing. The present invention relates to a switching system suitable for integrating and exchanging burst exchange information such as data.

[0002]

2. Description of the Related Art A typical telephone voice bit rate (64K
Not only b / s), but also low-speed (several 100 b / s) data to video signals (several Mb / s) with various bit rates and various properties (burst, real-time, etc.) There is a need for a flexible and economical switching system that can be integrated and handled.

In response to such a request, a fixed length cell having a header containing information for routing is used to uniformly switch all information.
This is one promising idea. For example, the paper "The Institute of Electronics, Information and Communication Engineers 70th Anniversary General Conference (Showa 62)" switching department 1832 "line /
The switching system shown in "Consideration of packet integrated speech path" is one of them. In this example, all communication information is transferred using fixed-length blocks called cells. In the switching, the header-driven space switch is basically used, and in order to prevent multiple cells having the same destination from colliding with each other within the space switch, a time switch function is provided for each incoming highway. There is. In addition, the time switch function handles two modes: a circuit switching mode in which real-time performance is required, such as telephone voice, and a burst switching mode in which data generated in bursts is transmitted, although some delay is allowed. For this purpose, a memory for switching and a buffer memory for waiting are provided. The circuit switching mode cells are preferentially handled without passing through the buffer memory in order to guarantee real-time performance, while the burst switching mode cells are queued in the buffer memory and processed when there is a free time slot.

As another example, JP-A-59-135994.
The "TDM switching system" disclosed in the publication is cited. In this example, the concept of handling communication having two kinds of characteristics of the circuit switching mode and the burst switching mode is not specified, but it has a function of temporally exchanging fixed-length cells using a buffer memory. There is. At that time,
The same buffer memory is used for cell queuing and switching. To realize the waiting, the write address of the cell in the buffer memory can be known from the header. There is provided a queuing means for storing the cells for each destination.

A cross type is well known as a non-block multistage speech path switch for circuit switching. (Akimaru "Introduction to Modern Exchange Engineering" Ohmsha, Showa 54
Year PP. 136-137 and Sea Cross: A Study of Non-Blocking Networks, Bell System Technical Journal, Vol. 32, Vol.
Issue (1953) (C. Clos: A Study of Non Blocking N
etworks, Bell SystemTechnical Journal vol.32, No.3
(1953)) This cross-type multi-stage switch has the number of incoming lines of the primary switch is m, the number of outgoing lines is r, the number of incoming lines and outgoing lines of the secondary switch are both k, and the number of incoming lines of the tertiary switch is r, the number of outgoing lines is m, the number of primary switches is k, the number of secondary switches is r, and the number of tertiary switches is k, and the number of outgoing lines of the primary switch is one for each secondary switch. In the multi-stage switch configuration in which k outgoing lines of the secondary switch are connected to each tertiary switch one by one, it is a three-stage switch configured to satisfy r ≧ 2m−1 (cross formula). still,
The term "non-block" as used herein means that when there is free capacity on both the input line and the output line of the switch, there is always a path connecting between them.

[0006]

When switching is performed using fixed-length cells, the destinations of each cell are not necessarily distributed evenly, so that the cells destined for the same destination are temporarily concentrated, and congestion occurs. Or a cell may be lost due to memory overflow. above,
In the first paper by the applicant, a buffer memory for waiting for avoiding a congestion state is provided for each destination output highway. This buffer memory needs to store the entire cell, and can store a large number of cells without overflowing, and must be provided individually for each destination. Therefore,
This configuration has a problem of requiring a large amount of memory.

On the other hand, in the second switching system (Japanese Patent Laid-Open No. 59-135994), there is one buffer memory for all highways, and a queuing means for storing only the address of the buffer memory. Are provided for each cell destination. In this configuration, the bias of the destination of each cell can be absorbed with a relatively small amount of memory.
However, since the write address of the buffer memory is used periodically, it is logically equivalent to the buffer memory being fixedly divided for each destination, and when the waiting of a certain queue exceeds a certain amount. , The same write address is used even though there are still unread cells, and buffer memory overwrite occurs. At this time, the overwritten cell is lost.

The cross-type switch is a non-block when handling a plurality of calls having a single speed, but when each call has an arbitrary speed, a link connecting unit switches. It does not become non-blocking because it reduces the usage efficiency of. If the speed of each call is different,
For example, there is a so-called bug-eating phenomenon in which a low-speed call occupies a part of the link capacity, so that a high-speed call cannot enter there even though the link still has free capacity. Occur. For this reason, the use efficiency of the link decreases, and even if the above-mentioned cross formula is satisfied, a block occurs.

An object of the present invention is to provide a switching system which solves the above-mentioned problems of the conventional example, eliminates a large amount of memory use, and prevents blocks from being lost by overwriting a buffer memory.

It is another object of the present invention to provide a non-blocking multi-stage speech path switch which does not cause blocking even if each call has an arbitrary speed, with a simple and economical structure.

[0011]

In order to achieve the above object, a plurality of incoming highways (hereinafter simply referred to as incoming lines)
Time-division-multiplexing, writing the arriving cells to a buffer memory (hereinafter referred to as the main buffer), reading them in an appropriate order, demultiplexing, and allocating to a plurality of outgoing highways (hereinafter simply referred to as outgoing lines). In a switching system that performs switching operation by means of a FIFO (First In F
irst Out) buffer (referred to as an idle address FIFO) and means for managing the in-use address in correspondence with the outgoing line. When writing a cell to the main buffer, an empty address is taken out from the data output of the idle address FIFO buffer, At the time of reading a cell from the main buffer, an idle address chain is provided to return the read address to the data input of the idle address FIFO buffer.

The non-block multi-stage speech path switch can be solved by not only spatially increasing the number of links of the multi-stage switch, that is, increasing the number of links, but also increasing it temporally, that is, increasing the link speed. Specifically, the number of incoming and outgoing lines and the number of links are m and r, respectively, as described above, but when the speed of the incoming and outgoing lines is 1, the link speed is x times, and the number of links is r, r ≧
The switch configuration is set so as to satisfy 2 × {(m-1) / (x-1)}-1.

[0013]

When a cell arrives and is written in the main buffer, a free address is obtained from one idle address FIFO regardless of the destination output line of the cell. You can write cells in any of the areas. Even if the destination of the arriving cell is skewed to a specific outgoing line, the required capacity of the main buffer does not change because the cell to the other destination should decrease accordingly.

Further, until the cell is read, the address where the cell is stored does not return to the idle address FIFO, so that the cell is overwritten at the same address and the cell stored therein disappears. There is no.

In the multistage switch, (m-1) indicates a state in which (m-1) of m incoming lines are in use.
On the other hand, (x-1) is obtained by subtracting 1 which is the incoming line speed ratio from the link speed ratio x, and is "(m-1) / (x-
1) ”represents the number of links in a state in which the capacity of one incoming line cannot be accommodated although the link has a free capacity. The symbol "a" represents the smallest integer not less than a. One link is removed from here {"(m-1) /
Since (x-1) "-1} links are in this state and the outgoing line side is exactly the same as the incoming line side, the number of links is 2 x {" (m-1) / (x- 1) "-1}, if one new incoming line cannot be accommodated in the link, and there is another accommodable link, that is, 2x
If {"(m-1) / (x-1)"-1} +1, both the incoming line side (primary link) and the outgoing line side (secondary link) are free for one incoming line or more This switch never blocks because there is always a link with a common capacity.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, n input lines are connected to the input (DI) of the data of the main buffer 105 via the serial-parallel conversion multiplexer 101, and the data output (DO) of the main buffer 105 is parallel-serial conversion demultiplexing. It is connected to the vessel and separated into m output lines. Of the output of the serial-parallel conversion multiplexer 101, the part corresponding to the cell header is connected to the read address terminal (RA) of the header conversion table 102, and the new header of the data output (DO) of the header conversion table 102 is connected. The part is connected to the data input of the main buffer 105, and the free / busy information (empty = 0) part is the AN
It is connected to the write enable input (WE) of the main buffer 105 via the D gate 109, and the output line number portion is connected to the destination output line number input (DEST) of the address pointer 104. The data input (DI) and write address (WA) of the header conversion table 102 are connected to a control system (not shown). Idle address FIFO1
The data output (DO) of 03 is connected to the data input (DI) of the main buffer 105 and the next write address input (NWAD) of the address pointer 104, and the empty display output (EPTY) is written to the main buffer 105 via the AND gate 109. Connected to enable input (WE). Write address output of address pointer 104 (W
AD) is connected to the write address input (WA) of the main buffer 105 and read address output (RAD)
Outputs the read address (RA) of the main buffer 105 and the idle address FIFO via the selector 110.
It is connected to the data input (DI) of 103. Of the data output (DO) of the main buffer 105, the portion corresponding to the next read address is connected to the next read address input (NRAD) of the address pointer 104, and the other portion, that is, the portion corresponding to the cell body is the same. The output lines are separated via the serial conversion demultiplexer 106. The output of the control counter 107 is connected to the read counter input (RACNT) of the address pointer 104. The empty address register 111 is connected to the input of the selector 110. The queue status display output (STS) of the address pointer 104 is the selection input of the selector 110 and the idle address FIFO.
It is connected to the write enable input (WE) of 103.

First, the operation of writing a cell into the main buffer will be described. The cells arriving from each incoming line are parallel-converted by the serial-parallel converter / multiplexer 101 to facilitate the sequential handling of cells one by one. An example of the structure of a cell arriving from an incoming line is shown in FIG. 2A, and a conceptual diagram of serial-parallel conversion multiplexing is shown in FIG. The serial-parallel conversion multiplexer can be configured using a known circuit generally called a barrel shifter. As shown in FIG. 2A, the logical channel number is written in the header of the cell, and by accessing the header conversion table 102 with this number, the new logical channel number on the outgoing line side of the cell, the cell Get information about whether the cell is empty or used, and the destination outgoing line number of the cell. These pieces of information are written in the table by access from the control system at the time of call setup. Figure 2
An example of the output of the header conversion table 102 is shown in (b).

The destination outgoing line number of the cell is the address pointer 1
04, and an appropriate write address is obtained accordingly. The write address is an idle address FI
It is previously input from the FO 103. The cell is written to the main buffer 105 using the write address. If the cell is a vacant cell or if the idle address FIFO is vacant (that is, if the main buffer has no vacancy), the output of the AND gate 109 becomes L, so that the main buffer 105 cannot be written. Also, the read clock (RCK) of the idle address FIFO becomes L, and the empty address is not output.

Next, the read operation will be described. To read a cell, the read address is obtained from the address pointer 104 according to the number generated by the control counter 107, and this is used as the read address of the main buffer to read the cell. The value of the control counter corresponds to the outgoing line number. That is, one cell is sequentially read out for each outgoing line.
The address used as the read address is sent to the data input (DI) of the idle address FIFO 103,
It is used again as a write address. When there is no cell addressed to a certain output line in the main buffer, a queue status display output (STS) is output, and the selector 110 uses the empty cell address register 111 as the read address of the main buffer 105. The address stored in is selected. The contents of the main buffer corresponding to the address are always empty cells.

The data output of the idle address FIFO is stored in the main buffer together with the cell. This is because it indicates the storage address of the next cell that has the same destination as the destination output line of that cell. Detailed operation will be described below with reference to FIG. The cell structure in the main buffer is shown in FIG.
Shown in

Next, referring to FIG. 3, the address pointer 10
The configuration and operation of No. 4 will be described. Enter outgoing line number (DEST)
Are connected to the input of the output line number decoder 301 and the selection input of the write address selector 308. The m decoded outputs of the outgoing line number decoder 301 are connected to the clock inputs of m write registers (WR1 to m) 302 to 303, respectively. The next write address (NWAD) input from the external idle address FIFO is connected to the input of each write register, and the output of each write register becomes the write address output (WAD) via the write address selector 308. On the other hand, control counter input (R
ACNT) is connected to the selection inputs of the decoder 311 and the read address selector 309, and the m decoded outputs of the decoder 311 are respectively m read registers (RR).
1-m) is connected as a clock input to 304-305 through a gate. The next read address input (NRAD) from the outside is connected to the input of each read register,
The output of each read register is the read address selector 309.
It becomes a read address (RAD) via. The mismatch detectors 306 to 307 receive the outputs of the corresponding write register and read register, respectively, and the respective outputs become the queue status display outputs (STS) via the mismatch information selector 310. The output of the mismatch detector is also connected to one input of the gate.

By the output line number input (DEST), the output corresponding to the output line number is selected from the outputs of the m write registers by the write address selector 308, and is set as the write address output (WAD). At this time, the value held in the write register corresponding to the above is changed to the idle address F by the decode output of the output line number decoder 301 at the same time.
Update to the (NWAD) value input from the IFO. Therefore, the value of NWAD immediately before the update corresponds to the write address when the cell having the same destination as the destination output line number of the cell to be written at this time comes next. Therefore, if this NWAD value is stored in the main buffer together with the cell to be written at this time, when this cell is read, the next time the cell addressed to the same output line is read, You can know whether to read from the address. When reading a cell, a read address selector that uses the value of the control counter as a selection input selects a read register output, outputs the value held in that register as a read address output (RAD), and uses this as a read address. At the same time, the value held in the read register selected at this time is updated by the output of the decoder 311. The input of the read register at this time is the next read address which is read from the main buffer and is stored together with the cell 1 at the time of writing, so that the read register holds the address of the next cell addressed to the same outgoing line. I can do things.

FIG. 5 shows the configuration of the idle address FIFO 103. The idle address FIFO 103 includes a memory 501, a write counter (WCNT) 502, a read counter (RCNT) 503, and a coincidence detector 504. The write counter 502 has a write address (WA).
Is a ring counter that counts the number of addresses in the memory 501. The read counter 503 is a counter that outputs a read address (RA), and is a ring counter that counts the number of addresses in the memory 501. When the values of both counters are the same, the memory is empty, so the coincidence detector 504 detects this and outputs an empty output (EPTY). As described above, it has a FIFO function as a whole.

Next, another embodiment will be described with reference to FIG.
The switching system shown in FIG. 6 is basically based on the same principle as that shown in FIG. 1, but a priority control mechanism is further added to that of FIG. 6, the same components as those shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The biggest difference from FIG. 1 is that there are a plurality of address pointers. Here, it is assumed that there are three classes as priority classes. These are referred to as class 1 (C1), class 2 (C2), and class 3 (C3), respectively.

The output of the header conversion table 102 in FIG. 6 includes class display. The class display output is connected to the input of the class decoder (CDEC) 605 and the selection input of the write class selector (WSEL) 606.
Each decode output of the class decoder (CDEC) 605 is connected to the write address enable input (WAEN) of the address pointer corresponding to each class. Of the decoded outputs of the class decoder (CDEC) 605, the C2 output is ANDed with the output of the up / down counter 608 to be C2 '. Class decoder (CD
The C1 and C3 outputs of EC) 605 and the OR output of C2 'are connected to the write enable (WE) of the main buffer 105. Address pointer corresponding to each class, that is, address pointer (class 1) 601, address pointer (class 2) 602, address pointer (class 3) 6
Each queue status display output (STS) 03 is connected to the input of the read access control 604. An example of the relationship between input and output of read access control is shown in FIG. The output of the read access control 604 is the read class selector (RSEL) 6
07 and the input of the decoder (REDEC) 609. The decode output of the decoder (REDEC) 609 is connected to the read address enable input (RAEN) of the address pointer of the corresponding class, and
The OR of the decode output is connected to the write enable input (WE) of the idle address FIFO. The up / down counter 608 has a class 2 read address enable input (RAEN) as an up input and C2 ′ as a down input. The definition of each class is as follows: Class 1 has a small delay time and a small cell loss rate, Class 2 has a small delay time, but a large cell loss rate, and Class 3 has a slightly large delay time. The cell loss rate is small. Class 2 may have a slightly higher loss rate than other classes, thus limiting the available main buffer capacity. Specifically, the up-down counter 608 is set with the capacity that can be used in terms of the number of cells. The up / down counter 608 is down at the time of writing and up at the time of reading. Therefore, when this counter becomes 0, it indicates that the main buffer is used up to the limit value. At this time C
The 2'output goes to L and no new writes of this class are performed. Therefore, the class 2 cell arrived at this time is discarded. On the other hand, with regard to the delay time, read priority is set by read access control so that class 1 is the smallest and class 3 is the largest. Specifically, for each outgoing line, if a class 1 cell is in the main buffer, it is read first, if there is no class 1 queue, a class cell is read, and if there is no class 2 queue, a class 3 cell is read. Is read, and so on.

When the cell arrives, the header conversion table 10
The class to which the cell belongs can be identified by the output of 2, and the write address enable output (WAE) to the address pointer corresponding to the class by the class decoder 605.
N) is issued. On the other hand, the write address output (WAD) output by the address pointer is selected by the write class selector (WSEL) 606 and used as the write address (WA) of the main buffer. On the other hand, in the case of reading, as described above, the read access control 604
Monitors the presence or absence of a waiting queue corresponding to each outgoing line of each class, and controls so that the highest priority among the waiting queues is output. Specifically, the decode output of the decoder 609 indicates the address pointer of the class to be read, and the read class selector 607
The read address output output by the address pointer of the class to be read is selected and used as the read address of the main buffer.

Next, another embodiment will be described with reference to FIG. The configuration of FIG. 8 does not have the header conversion table 102 of FIG. In this case, the structure of the cell arriving from the incoming line is as shown in FIG. Such a format is suitable for a configuration in which a header conversion table is provided for each incoming line at a stage preceding the switch. In addition, when considering a switch having a multi-stage configuration described later, it is possible to collectively perform header conversion in advance without performing header conversion in each stage switch.

In each of the embodiments described above, if the main buffer and the idle address FIFO or the main buffer, the idle address FIFO and the address pointer are integrated into a circuit and mounted on the same chip,
A small switch can be realized, and the multistage structure described below can be easily realized.

Next, with reference to FIGS. 10 and 11, an embodiment of a multistage switch (multistage speech path switch) will be described. First, the non-blocking condition of the multistage switch will be described prior to the description of the specific embodiment.

Conventionally, a cross type is well known as a non-block multistage speech path switch for circuit switching. (Akimaru "Introduction to Modern Exchange Engineering" Ohmsha, Showa 54
Year PP. 136-137 and Sea Cross: A Study of Non-Blocking Networks, Bell System Technical Journal, Vol. 32, Vol.
Issue (1953) (C. Clos: A Study of Non Blocking N
etworks, Bell SystemTechnical Journal vol.32, No.3
(1953)) This cross-type multi-stage switch has the number of incoming lines of the primary switch is m, the number of outgoing lines is r, the number of incoming lines and outgoing lines of the secondary switch are both k, and the number of incoming lines of the tertiary switch is r, the number of outgoing lines is m, the number of primary switches is k, the number of secondary switches is r, and the number of tertiary switches is k, and the number of outgoing lines of the primary switch is one for each secondary switch. In the multi-stage switch configuration in which k outgoing lines of the secondary switch are connected to each tertiary switch one by one, it is a three-stage switch configured to satisfy r ≧ 2m−1 (cross formula). still,
The term "non-block" as used herein means that when there is free capacity on both the input line and the output line of the switch, there is always a path connecting between them.

The cross switch is non-blocking when handling multiple calls with a single speed. However, when each call has an arbitrary speed, the use efficiency of the link connecting the unit switches decreases, and thus the call is not non-blocking. If the speed of each call is different,
For example, there is a so-called bug-eating phenomenon in which a low-speed call occupies a part of the link capacity, so that a high-speed call cannot enter there even though the link still has free capacity. Occur. For this reason, the use efficiency of the link decreases, and even if the above-mentioned cross formula is satisfied, a block occurs.

The problem is that not only is the number of links of the multistage switch increased spatially, that is, the number of links is increased,
It is solved by increasing the time, that is, increasing the link speed. Specifically, the number of incoming and outgoing lines and the number of links are m and r, respectively, as described above, but when the speed of the incoming and outgoing lines is 1, the link speed is x times, and r ≧ 2 ×
The switch configuration is such that {(m-1) / (x-1)}-1 is satisfied.

In the above equation, (m-1) on the right side shows a state where (m-1) of the m incoming lines are in use. On the other hand, (x-1) is obtained by subtracting 1 which is the incoming line speed ratio from the link speed ratio x, and a certain link has a capacity which is one minute short of the incoming line by a minute amount Δ in the speed. Shows the limit value of Δ → 0 in the state (x−1 + Δ) that is used after leaving. Therefore, "(m-1) / (x-1)" is used in a state where the link has a free space but cannot accommodate one incoming line, that is, each link is used in the least efficient state. It indicates the number of links in the state in which the link is on. The symbol "a" represents the smallest integer not less than a. One link is removed from here {"(m-1) / (x-
1) ”-1} links are in this state, and the outgoing line side is exactly the same as the incoming line side, so the number of links is twice the above, that is, 2 × {“ (m−1) ”. / (X-1) "-
1} lines, a new incoming line cannot be accommodated in the link, and if there is another accommodating link, that is, 2 × {“(m−1) / (x−1)”. If “−1} +1”, there is always a link that has a free capacity equal to or more than one incoming line on both the incoming line side (primary link) and the outgoing line side (secondary link).

Therefore, when the number of links is r,
If r ≧ 2 × {“(m−1) / (x−1)” − 1} +1 is satisfied, this switch will not block.

An embodiment of the present invention will be described below with reference to FIG. As shown in FIG. 10, n
= Mk. As the first-stage switches, k unit switches each having an input terminal number m and an output terminal number 2m-3 were arranged. Also, as an intermediate stage switch, a unit switch with a number of input / output terminals of 2 m
As a final stage switch, k unit switches having an input terminal number of 2 m−3 and an output terminal number of m are arranged. As shown in FIG. 10, the connection between the respective unit switches is such that one unit switch that constitutes the first-stage switch has all the unit switches that constitute the intermediate-stage switch, and one unit switch that constitutes the intermediate-stage switch is the final switch. It is designed to be connected to all the unit switches that make up the stage switch.
The expression of the non-block condition described above, r ≧ 2 × {“(m−
1) / (x-1) "-1} +1, x = 2, r =
It is equivalent to 2m-3, and the equal sign holds. As the unit switches of each stage, those already described with reference to FIGS. 1, 6 and 8 and those described with reference to FIGS. 12 and 16 can be applied.

Next, FIG. 11 shows another embodiment of the multistage speech path switch. In the embodiment of FIG. 10, the expression of the non-block condition described above, r ≧ 2 × {“(m−1) / (x−
1) ”− 1} +1, the example is x = 2 and r = 2m−3, whereas in this example, x = 3 and r = m−2. Also in this case, the equal sign is established. The concept of the configuration is the same as in FIG. The configuration of each unit switch is also specifically the same as that of the first embodiment, and a detailed description thereof will be omitted.

According to the above-described embodiment, a call having an arbitrary communication speed can be realized by a non-block switchable multistage switch with a minimum necessary configuration.

Next, another embodiment of the unit switch will be described with reference to FIG. In FIG. 12, the constituent elements are the same as those in FIG. 1 except for the address FIFO group 1201, and the connection relationship is slightly different. In FIG. 12, the idle address FI
The data output (DO) of the FO 103 is directly connected to the write address (WA) of the main buffer 105.
Further, only the cell body is written in the main buffer 105, and the next address information is not written. The address FIFO group 1201 which is the point of this configuration will be described with reference to FIG.

The outgoing line number input (DEST) is connected to the outgoing line number decoder (WDEC) 1301, and the m decoded outputs thereof are respectively m FIFO buffers 1303 to 1303.
It is connected to the write signal (WCK) input of 1304. F
The data input of the IFO buffers 1303-1304 is the data output of the idle address FIFO of FIG.
The data output of the FIFO buffers 1303 to 1304 becomes a read address output (RAD) via the read address selector 1305. Read address selector 130
The control counter input (RACNT) 5 is a selection input. The control counter input (RACNT) is further input to the read order decoder 1302 and the empty state selector (EPSEL).
Connected to the select input of 1306. The decode output of the read order decoder 1302 is connected to the read signal (RCK) input of each FIFO buffer. The empty state signal (EP) of each FIFO buffer is an empty state selector (EPSE
It becomes a cue state display output (STS) via L).

In the present embodiment, at the time of cell writing, an empty address is taken out from the idle address FIFO and used as it is as the write address of the main buffer. At the same time, the address is written in the FIFO buffer corresponding to the destination outgoing line number of the cell in the address FIFO group 1201.
At the time of reading, an address is sequentially taken out from each FIFO buffer, and a cell is read from the main buffer using this address as a read address. When the FIFO buffer is empty, an EP output is issued.

In this configuration, the number of bufferable cells per outgoing line is limited by the capacity of the FIFO buffer in the address FIFO group. However, if this capacity is made sufficiently large, the overall configuration is simple. It is a composition.

FIG. 14 shows an example of expansion of the switch scale. The header drive type time switches 1401 to 1402 and the header drive type space switch 1403 are provided, and the header drive type time switches 1401 to 1402 are provided corresponding to the incoming lines, and their outputs are used as the inputs of the header drive type space switch.

Here, the header-driven time switch is a switch for changing the time order of cells based on header information. Specifically, the above-mentioned FIG. 1, FIG. 6, FIG.
A switching system such as that shown in FIG. 12 can be applied (however,
Multiplexing, excluding the demultiplexing unit). In these previously described switching systems, cell reading is performed based on the value of a control counter. Therefore, if the values of the control counters of the n header-driven time switches in FIG. 14 are always made different (for example, they are shifted one by one), all the cells read at the same time will have their destination outgoing lines. The numbers are different. Therefore, the header drive type space switch 1403
In that case, since the cells input at the same time have the same destination, collision does not occur. Therefore, the header drive type space switch may have a simple structure as shown in FIG. In FIG.
Timing circuits 1501 to 150 corresponding to the respective incoming and outgoing lines
n, selectors 1511-151n, and selected address generators 1521 to 152n, all the input lines are connected to the selected address generator in the parts corresponding to the header information of each incoming line, and the parts other than the header of each incoming line are the timing circuit. To each selector corresponding to each outgoing line. Since the destinations of cells input at the same time are all different, only one piece of header information having a destination corresponding to itself comes to each selected address generating unit. When the selection address corresponding to the incoming line from which the header information is generated is generated, the selector selects the destination according to the destination, and the space switch operation is performed as a whole.

FIG. 16 shows the configuration of FIG. 12 with a priority control mechanism added. There is class display output in the data output of the header conversion table 102, which is the address FIFO.
Connected to the class input (CLS) of group 1601.

FIG. 17 shows an address FIFO with a priority control function.
This is the configuration of O group. Description of the same parts as in FIG. 13 will be omitted. In this embodiment, two classes of priority and non-priority are provided in the reading order. Therefore, two FIs for each outgoing line
FO buffers (eg 1702 and 1704) are provided. The write signal input (WCK) of the FIFO buffer is ANDed with the decode output of the output line number decoder 1301 and the decode output of the class information decoder 1701. The read signal input (RCK) is the AND of the decode output of the read order decoder 1302 and the empty state display output (EP) of each FIFO. According to this configuration, when writing a cell, the write address (WAD) is stored in the FIFO buffer corresponding to the output line number and class, and when reading the cell, the FIFO (eg 1702) on the read priority side becomes empty. Until now this FIFO
The read address is output from the first FIFO, and the other FIFO (eg, 1704) is read only when this FIFO becomes empty.

In this embodiment, two classes of priority regarding the delay time are provided for explanation, but it is possible to increase the number of FIFO buffers for each class to handle a large number of classes. Also, by controlling the capacity of the FIFO buffer,
It can also be applied to classification according to the loss rate.

[0047]

According to the present invention, no cell disappears due to writing a new cell before the cell is read from the main buffer. Further, since the entire area of the main buffer can be used in common for all outgoing lines, even if the destination of cells to a specific outgoing line is biased, the memory capacity can be used efficiently. Therefore, cell discard is unlikely to occur. This is particularly effective when dealing with a strong bursty communication in which cells of the same destination instantaneously converge and arrive.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of the structure of a cell used in the embodiment of FIG.

FIG. 3 is a detailed functional block diagram of the address pointer shown in FIG.

FIG. 4 is an operation explanatory diagram of the serial-parallel conversion multiplexer of FIG.

5 is a detailed functional block diagram of the idle address FIFO shown in FIG.

FIG. 6 is a functional block diagram of an embodiment of the present invention.

7 is an explanatory diagram of the logic of read access control of FIG. 6;

FIG. 8 is a functional block diagram of an embodiment of the present invention.

9 is an explanatory diagram of the structure of a cell used in the embodiment of FIG.

FIG. 10 is an explanatory diagram of an embodiment of the present invention.

FIG. 11 is an explanatory diagram of an embodiment of the present invention.

FIG. 12 is a functional block diagram of an embodiment of the present invention.

13 is a detailed functional block diagram of the address FIFO group in FIG.

FIG. 14 is an explanatory diagram of an embodiment of the present invention.

15 is a functional block diagram of the space switch of FIG.

FIG. 16 is a functional block diagram of an embodiment of the present invention.

17 is a detailed functional block diagram of the address FIFO group in FIG.

[Explanation of Codes] 101 ... Serial-parallel conversion multiplexer, 102 ... Header conversion table, 103 ... Idle address FIFO,
104 ... Address pointer, 105 ... Main buffer,
106 ... Parallel-serial conversion demultiplexer, 107 ...
Control counter, 302 ... Write register, 304 ... Read register, 306 ... Mismatch detector, 308 ... Write address selector, 3
09 ... Read address selector, 604 ... Read access control, 1201 ... Address FIFO group, 13
03 ... FIFO buffer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Mori 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company, Totsuka Plant, Hitachi, Ltd. (72) Inventor Akira Horiki 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi Ltd. Totsuka Plant (72) Inventor Takao Kato 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ltd. Inside the Hitachi Ltd. Totsuka Plant (72) Inventor Hiroshi Kuwahara 1-280 Higashi Koikeku, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-59-135994 (JP, A) JP-A-58-97944 (JP, A) JP-A-61-202546 (JP, A) JP-A-61-232744 ( JP, A) JP Hei 2-1655 (JP, A) 1986 IEICE General Conference 1765

Claims (5)

(57) [Claims] 1. A fixed length cell comprising a header part and an information part.
Class information that distinguishes the handling conditions of the cell was also added.
Multiple cells based on the information contained in the header of the cell
Exchange between input highways and multiple output highways
A switching system for storing cells received from the plurality of input highways.
The cell to the destination output highway of the plurality of output highways.
And a first storage means for exchanging the first storage means
Second memory for accumulating information corresponding to free addresses in
And the information stored in the second storage means
Write and read control of the first storage means
And a control circuit, wherein the control circuit includes the first storage means and the second storage means.
And a first storage means that is installed in common with the control circuit.
Of the first storage means based on the read address of
The information corresponding to the address is stored in the second storage means.
Then, the information from the second storage means is transferred to the first storage device.
Connected to output as write address of column
The first storage of the cell based on the class information
Priority processing circuit that controls writing and reading to the means
A switching system characterized by being provided. 2. A fixed-length cell consisting of a header part and an information part
Class information that distinguishes the handling conditions of the cell was also added.
Multiple cells based on the information contained in the header of the cell
Exchange between input highways and multiple output highways
A switching system for storing cells received from the plurality of input highways.
The cell to the destination output highway of the plurality of output highways.
And a first storage means for exchanging the first storage means
Second memory for accumulating information corresponding to free addresses in
And the information stored in the second storage means
Write and read control of the first storage means
And a control circuit, wherein the control circuit includes the first storage means and the second storage means.
They are commonly installed in preparative, first storage means from the previous SL control circuit
Of the first storage means based on the read address of
The information corresponding to the address is stored in the second storage means.
Then, the information from the second storage means is transferred to the first storage device.
Connected to output as write address of column
The information from the second storage means to the next cell
It is stored as the next address to be written in the storage means of No. 1
A third storage means for storing the class information based on the class information.
Control of writing to and reading from the first storage means.
A priority processing circuit for controlling the cell of the cell corresponding to the class information.
In writing, the empty space output from the second storage means
Before the information corresponding to the address corresponds to the class information
Assigned as the write address of the memory cell, and
Address corresponding to the write address of the storage means of No. 3
Enter the next address in the space
In reading a cell from the first storage means,
Based on the next address output from the third storage means
Outputting the read address of the first storage means
Switching system characterized by . 3. A fixed-length cell consisting of a header part and an information part
Class information that distinguishes the handling conditions of the cell was also added.
Multiple cells based on the information contained in the header of the cell
Exchange between input highways and multiple output highways
A switching system for storing cells received from the plurality of input highways.
The cell to the destination output highway of the plurality of output highways.
And a first storage means for exchanging the first storage means
Second memory for accumulating information corresponding to free addresses in
And the information stored in the second storage means
Write and read control of the first storage means
And a control circuit, wherein the control circuit includes the first storage means and the second storage means.
And a first storage means that is installed in common with the control circuit.
Of the first storage means based on the read address of
The information corresponding to the address is stored in the second storage means.
Then, the information from the second storage means is transferred to the first storage device.
Connected to output as write address of column
The number of pieces of class information from the second storage means.
Information for writing the next cell to the first storage means.
It comprises a third storage means for accumulating as an address.
Writing to the first storage means of the cell based on the lath information
A priority processing circuit for controlling the writing and reading is provided, and the control circuit controls the cell of the cell corresponding to the class information.
In writing, the third record corresponding to the class information is written.
Before the address corresponding to the write address of the memory
Enter the following address and enter the address corresponding to the class information
When reading a cell from the first storage means, the class
The information output from the third storage means corresponding to the information
The read address of the first storage means based on the next address
A switching system characterized by outputting a response . 4. Class information for distinguishing the handling condition of the cell
Is class information that distinguishes the discard rate of the above cells, and
The priority control circuit of the control circuit is written in the first storage means.
The cell to be imbedded is provided with counting means, and the counting means is
Detect a predetermined value for a given class of cells
Then, the cell writing of the class to the first storage means is performed.
It is a control circuit that prohibits and discards cells
The switching system according to claim 1, wherein 5. Class information for distinguishing handling conditions of the cell
Is the class information that distinguishes the size of the allowable delay time of the above cell
And the control circuit reads the first storage means.
Is performed from a cell with a small allowable delay time.
The switching system according to claim 1 .