JP3075187B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronou).
s Transfer Mode: Used for communication.
The present invention relates to a technology for improving the throughput of an ATM exchange.

[0002]

2. Description of the Related Art An information transmission system in a wideband ISDN is called an ATM. This ATM divides a wide variety of information into short fixed-length packets with headers called "cells" and multiplexes the packets for transmission. The ATM has the advantages of conventional circuit switching and packet switching. It also has ultra-high-speed transmission and can be applied to moving image transmission.

[0003] For the cell exchange in such an ATM communication, an ATM exchange device for converting fixed-length cells at high speed by hardware using a simplified protocol is used. The switch used in this ATM switching device, that is, the ATM switch essentially involves the possibility of cell collision, that is, the possibility that a plurality of cells arriving from different input lines require a connection to the same output line at the same time. To have.

When such a cell collision occurs, A
It is necessary to avoid cell discard by temporarily storing cells in a cell buffer provided inside the TM exchange, and to suppress the cell discard rate in the ATM exchange.

As a method for achieving this object, an input buffer type A in which a cell buffer is arranged before a space switch is used.
There is an input / output buffer type ATM switch in which the operating speed of the TM switch and the space switch is made faster than that of the input / output line, and a cell buffer is arranged before and after the space switch.
The latter input / output buffer type ATM switch requires an operating speed of the space switch to be higher than an input / output line speed, and thus it is difficult to realize a high-speed switch accommodating a high-speed line. In order to construct a high-speed ATM switch, an input buffer type ATM switch in which a cell buffer is arranged in front of the space switch without increasing the speed is desirable in terms of hardware implementation.

FIG. 10 is a block diagram showing a configuration example of a conventional input buffer type ATM switch. FIG.
In the input buffer type ATM switch shown in FIG. ₁ , input buffers 211 to 21n are arranged for each of the input lines IN _{1 to} IN _n , and the input buffers 211 to 21n and the output line OUT ₁
Space switch 1 with cross point opening / closing function between ~ OUT _m
5, 221 to 21n are input lines I
FIFO type input buffers arranged for each of N _{1 to} IN _n , 1911 to 19 nm are cross points of the space switch 15, 231 to 23 n are lines for transmitting information cells, 241 to 24 n are lines for transmitting control signals, 251
２５25 m is a line for transmitting an arbitration control signal. FIG. 11 is a block diagram showing a configuration example of the cross point in FIG. Crosspoint 19ij
Is an address filter 400 (AF), a control circuit 401
It consists of.

For example, a cell arriving at the input line IN ₁ is written into the input buffer 211. The input buffer 211 operates according to a FIFO (First-In, First-Out) algorithm. The input buffer 211 sends out a request signal via the line 241 before sending out a cell. The request signal has, for example, request information and destination information. The request signal is for each cross point 1
The output line OUT ₁ to which the destination is connected to the cross point 19ij by the address filter 400 of 9ij.
ＯＵＴOUT _m is identified by referring to the routing bit. If the destinations match, the request information is sent to the control circuit 401. Plural input buffers 211 to 21
n on the same output lines OUT ₁ -OUT _m , for example, the input buffers 211 and 21 connected to the output line OUT _1.
When a request signal is issued from 2, 21n,
Contention control is performed using the line 251. As a method of contention control, for example, the cross point 19i
j is given a priority and output permission is given in accordance with the priority (fixed priority control), or a method by a ring arbiter is used to give output permission to the cross points 19ij in a ring-like order. . Contention control result, for example, connected to the output line OUT ₁ from the input buffer 21n is permitted.

[0008] The input buffer 21n having obtained the connection permission is
The first cell of the FIFO is connected to the line 23n and the space switch 15
Output line OUT ₁ through the cross point 19n1
Connect to Also, the input buffers 211 and 212 for which permission has not been obtained temporarily store the corresponding cells and wait for the next cell transmission timing.

With this operation, it is possible to avoid cell discard due to cell collision. Cell discard, for example,
In a state in which the input buffer 212 is filled with the temporary stored cells, further, when a new cell arrives from the input line IN _2, it occurs at the input side of the input buffer 212.

[0010]

However, in such an input buffer type ATM switch, HOL (Head-
Because of-line) blocking, the throughput of the ATM switch decreases. Here, the HOL blocking is
For example, it arranged on the input line IN ₁ input buffer 21
When the cell located at the head of one FIFO is temporarily stored to avoid cell collision, the cells located at the second and subsequent positions of the FIFO stored in the input buffer 211 have an empty output line to be connected. However, it refers to a state where it cannot be connected to the output line.

Assuming a randomly arriving load, when the input line N is infinite, the ATM is reduced to about 0.58 times the capacity of the input line due to the influence of HOL blocking.
It is known that the throughput performance of a switch can be suppressed.

When the scale of the ATM switch is increased (the number of input lines N and the number of output lines M are increased), in contention control on the same output line, the propagation delay of an electric signal for contention control is large. Therefore, implementation is difficult. For this reason, there is a problem that it is difficult to increase the scale of the ATM switch.

The present invention has been made in such a background, and an object of the present invention is to provide an ATM switch capable of reducing HOL blocking. An object of the present invention is to provide an ATM switch capable of improving throughput. An object of the present invention is to provide an ATM switch with high expandability.

[0014]

In the ATM switch of the present invention, one input line N × output line M ATM switch (main switch) is composed of S × T input line V lines × output line W. It consists of book sub-switches. Each of the sub-switches has an address filter and an input buffer on each of the V input lines for taking in cells having a destination to the sub-switch, and an output buffer on each of the W output lines.

After a cell is input to an input buffer in a specific sub-switch, it performs contention control (sub-contention control) with a cell having the same destination in the sub-switch, and a permitted cell is input to an output buffer. You. At each subswitch,
The sub-contention control in the sub-switch is performed independently. When cells are stored in the output buffer of the sub-switch, contention control between the sub-switches (main contention control) is performed between cells in the output buffer on the same output line in the main switch. As a result of the main contention control, the cell that has been granted permission is read from the output buffer in the sub-switch.

The features of the present invention are that input buffers are distributed in each sub-switch, output buffers are also distributed in each sub-switch, sub-contention control and It differs from the prior art in that there is main contention control between switches.

That is, the present invention relates to an ATM switch, which is characterized by N input lines and M switches.
Sub-switches having V input terminals and W output terminals for each of the output lines are S × T in a matrix.
(N = V.times.S, M = W.times.T), and each of the sub-switches has a V for identifying a cell to be connected to the W output terminals among the cells arriving at the V input terminals. Address filters, and an input buffer provided corresponding to the address filters, temporarily storing cells passing through the address filters, and outputting the read output to any of the W output terminals. The V input terminals of each of the T sub-switches arranged in a row are commonly connected to an input line for each of the V sub-switches, and the W output terminals of each of the S sub-switches arranged in the same column Are commonly connected to every W output lines, each sub-switch is independent of the other sub-switch,
It is provided with contention control means for avoiding collision of cells transmitted to the same output line.

As a result, most of the contention control is performed in a distributed manner in each sub-switch. Therefore, the contention control performed for the entire ATM switch can be simplified, so that the size of the ATM switch can be increased without considering the transmission delay of the electric signal for the contention control.

An output buffer for temporarily storing cells to be read from the input buffer and to be sent to any of the W output lines; a cell read from this output buffer and a cell read from another sub-switch; , And a means for controlling this selector so as to avoid collision of cells directed to the same output line.

In this case, cells to be output to the same output line are stored in the output buffer. Therefore, cells accumulated in the output buffer do not cause HOL blocking. In other words, by quickly transferring the cells stored in the input buffer to the output buffer, a decrease in throughput due to HOL blocking can be avoided. According to the present invention, each sub-switch is provided with an output buffer, contention control is performed for each sub-switch, and cells stored in the input buffer are quickly transferred to the output buffer, thereby avoiding a decrease in throughput due to HOL blocking.

Alternatively, the first output buffer for temporarily storing cells to be read out from the input buffer and to be transmitted to any of the W output lines and a cell for the same output line are prevented from colliding with each other. First contention control means for selecting an output route of a cell read from the first output buffer; and temporarily storing cells whose output route has not been selected as an output line by the first contention control device. A sub-switch including a second output buffer and second contention control means for selecting an output route of a cell read from the second output buffer so as to avoid collision of cells toward the same output line; A configuration including a conflict control unit may be employed.

In this case, the second contention control means includes means for returning, to the first output buffer, cells whose output route has not been selected as an output line by the second contention control means. It can also be configured.

That is, a first and a second output buffer are provided, contention control is performed on a subswitch basis, cells stored in an input buffer are quickly transferred to the first output buffer, and contention control is performed. By transferring the cells that cannot be output to the second output buffer, and by performing contention control and returning the cells that cannot be output to the first output buffer, the cells do not stay in a certain buffer for a long time, and HOL blocking is performed. Can be prevented from lowering the throughput.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

[0025]

【Example】

(First Embodiment) The structure of the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a conceptual diagram of an ATM communication network. FIG. 2 is a block diagram of the ATM switch according to the first embodiment of the present invention. FIG. 3 is a block diagram of the sub-switch according to the first embodiment of the present invention. FIG. 4 is a diagram for explaining contention control according to the first embodiment of the present invention. The embodiment of the present invention relates to an ATM switch of an ATM communication network as shown in FIG. Terminal devices TE1 and TE1 ', T
E2 and TE2 'and TE3 and TE3' transmit and receive signals of different forms, respectively.

The present invention relates to an ATM switch. The feature of the present invention is as shown in FIG. 2 and FIG.
A subswitch 20 having V input terminals and W output terminals for N input lines and M output lines, respectively.
kL (1 ≦ k ≦ S, 1 ≦ L ≦ T) is S ×
T cells (N = V × S, M = W × T) are arranged, and among the cells arriving at the V input terminals of the sub-switch 20 kL, the cells to be connected to the W output terminals are respectively identified. V address filters 5k1-5kV are provided corresponding to the address filters 5k1-5kV, and the cells passing through the address filters 5k1-5kV are temporarily stored, and the read output is sent to any of the W output terminals. V input terminals of T sub-switches arranged in the same row are commonly connected to V input lines 3k1 to 3kV, respectively, and are connected to the same column. The W output terminals of the S sub-switches are arranged in W output lines 4L1 to 4L1 respectively.
4LW, each sub-switch 20kL is independent of the other sub-switches 20kL, and an output buffer as contention control means for avoiding collision of cells transmitted to the same output line 4L1-4LW. 7L1
7 LW and a selector SEL.

The output buffers 7L1 to 7LW are read out from the input buffers 6k1 to 6kV and output W output lines 4L1
To 4LW are temporarily stored. The selector SEL is connected to the output buffers 7L1 to 7L
A cell read from W and a cell read from another sub-switch 20 kL are selectively output. As shown in FIG.
The control circuits 81j to 8Sj are connected to the same output line 4L1 to 4L4.
The selector SEL is controlled so as to avoid collision of cells toward LW.

Next, the operation of the first embodiment of the present invention will be described. Cells with routing bits are transferred on the input line. For example, output line 4LW on input line 3k2
It is assumed that a cell destined for is transmitted. Input line 3k2
In the address filter 5k2 at the entrance in the upper sub-switch 20kL, if the routing bit of the cell is a cell directed to the output lines 4L1 to 4LW in the sub-switch 20kL, the cell is input to the input buffer 6k2 of the sub-switch 20kL. You. In this way, in FIG. 3, the cell of the destination 4 LW (26 W in the output line in the sub-switch) transferred on the input line 3k2 is referred to by the address filter 5k2 by referring to the routing bit of the cell and input buffer. 6k2.

After cells are input to the input buffers 6k1 to 6kV in the sub switch 20kL, the output buffer 7
The operation until input to L1 to 7LW is the same as the operation of the conventional input buffer type ATM switch. The configuration of the cross points 1911 to 19VW in the sub-switch 20kL is common to the cross point of the conventional ATM switch shown in FIG. However, in the first embodiment of the present invention,
Output buffers 7L1 to 7L are provided for each output line 4L1 to 4LW.
W.

The sub-switch 20kL shown in FIG. 3 uses the input buffers 6k1-6kV for the input lines 3k1-3kV.
Each time, output buffers 7L1 to 7LW are connected to each output line 4L1 to
The input buffers 6k1 to 6kV and the output buffers 7L1 to 7LW are connected to each other by a space switch having a cross point opening / closing function.
W is each cross point in the sub-switch, 231-2
3W is a line for transmitting an information cell, 241 to 24W are
Lines for transmitting control signals, 251 to 25W, are lines for transmitting contention control signals.

The cell is written into input buffer 6k2. The input buffer 6k2 operates according to a FIFO algorithm. The input buffer 6k2 transmits a request signal via the line 241 before transmitting a cell. The request signal has, for example, request information and destination information. The request signal is transmitted at each cross point 1911-
The 19VW address filter 400 identifies whether the destination is the output line 4L1-4LW to which the cross point 1911-19VW is connected by referring to the routing bit. If the destination matches, the request information is determined. It is sent to the control circuit 401. Multiple input buffers 6k
A plurality of input buffers 6k1-6kV in the same sub-switch 20kL connected from 1-6kV to the same output line, for example, to the output line 26w going to the output buffer 7Lw.
Is sending a request signal from the control line 25w
Is used to perform contention control.

Here, the contention control means that the sub-switch 20
Since the request is directed to a request issued to the same output line 4LW in kL, the other sub-switch 20k
L and contention control operate completely independently. Hereinafter, the contention control in the sub-switch 20kL is called sub-contention control.

As a method of contention control, for example, a method of assigning priorities to the cross points 1911 to 19VW in advance and issuing output permission in accordance with the priorities (fixed priority control), or a method of giving output permission in a ring shape There is a method by a ring arbiter that is sequentially applied to the cross points 1911 to 19VW. As a result of the sub-contention control, for example, connection to the outgoing line 26w from the input buffer 6k2 to the output buffer 7Lw is permitted.

The input buffer 6k2 for which connection permission has been obtained is
The IFO first cell is connected to the line 26w via the line 232 and the cross point 192w.
It is input to the output buffer 7Lw. In addition, the input buffer for which permission has not been obtained temporarily stores the corresponding cell,
Wait for the next cell transmission timing.

This operation makes it possible to avoid cell discard due to cell collision. Cell discard, for example,
When a new cell arrives from the input line 3k2 via the address filter 5k2 in a state where the cell buffer 6k2 is filled with the temporarily stored cells, this occurs at the input side of the cell buffer 6k2.

Output buffers 7L1-7L of sub-switches
In the case of W, a FIFO operation is performed, but the reading speed is not constant and can be output only when permission is obtained. FIG. 4 is a diagram showing a block configuration when paying attention to the output buffers 71j to 7Sj of each sub switch in the output line 4Lj of the main switch. In FIG. 4, S sub switches are arranged vertically. Output buffer 71j in sub switch
When cells are stored in the output buffers 71j to 7Sj, the head cells of the output buffers 71j to 7Sj are
A request for cell transfer is sent to control circuits 81j to 8Sj corresponding to j to 7Sj. At a certain timing, when there are requests from the output buffers of a plurality of sub-switches on the same output line of the main switch, the control circuits 81j to 81j-
8Sj performs contention control between sub-switches. This is called main contention control to distinguish it from sub-contention control in the sub-switch. Similar to the sub-contention control method, the main contention control method includes a method using fixed priority control and a method using a ring arbiter. FIG. 5 is a diagram showing the operation of the output buffer. If there is no permission as a result of the contention control,
The line B and the line C are connected by the selector, and no cell is read from the output buffer. When there is permission, the line A and the line C are connected by the selector, the cell is read, and output to the outgoing line 4Lj. When no cells are stored in the output buffer, the line B and the line C are connected because there is no permission.

As described above, by distributing the input buffers for each sub-switch, each cell is dispersedly stored in the input buffer of the sub-switch having the destination output line. The load of incoming traffic is reduced. Therefore, HOL blocking can be reduced, and the throughput of the main switch can be improved.

Further, competition control between cross points is
By performing two-stage conflict control between the sub conflict control in the sub switch and the main conflict control between the sub switches, the sub conflict control can operate independently, and even if the switch size of the main switch is increased, The conventional competitive control method can solve the problem that mounting is difficult due to a large propagation delay of an electric signal. Therefore, according to the present invention, an ATM switch having expandability can be realized.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS.

FIG. 6 is a block diagram of a sub-switch 20kL of k rows and L columns among the sub-switches constituting the main switch. FIG. 6 shows a 4 × 4 sub-switch for simplicity of description, but can be generalized to a V × W sub-switch as in the first embodiment of the present invention. The V × W sub-switch is a space switch composed of V × W cross points of one input and two outputs,
Input buffers and W output buffers.

FIG. 7 is a block diagram showing the i-th input port section 32i. FIG. 8 shows the sub-switch 2 of FIG.
One-input two-output cross point 10ij at 0 kL
FIG. 3 is a block diagram of the configuration of FIG. The operation of the second embodiment of the present invention will be described. In FIG. 7, if a routing bit has a destination of the output line 4L1 to 4L4 in the sub-switch 20kL by the address filter AF on the line, the cell input from the input line 3ki is stored in the input buffer 21i. Written. This input buffer 21i
It operates according to the FIFO algorithm. Input buffer 2
1i, the cell is read out and the line 5 is read unless there is a stop command from the read stop signal 37 (for example, when the level is H).
The cell is transmitted via 3i. In line 53i, RB
(Routing bits) and data signals.

The Arb2 result signal on the line 59i becomes level H when there is a cell lost in the second sub-contention control of the cross point. The Arb1 result signal on the line 56i becomes level H when there is a cell lost in the first sub-contention control of the cross point.

When a cell is transferred on the line 53i, only RBs are taken out via the line 34. Line 59
When the Arb2 result signal of i is at level H, the line 53i
, The cell is not transferred, and the RB is transferred from the cross point via the line 60i. Therefore, the selector 31 does not transfer two RBs at the same time, and selects one of the RBs. Further, the RB 'of the head cell of the input buffer 21i is taken out via the line 35. By comparing the RB of the line 80 with the RB 'of the line 35,
If they match, the level is high on the line 36, and if they do not match, the level is low. Line 36 and line 53
Only when both the levels of i are H, the line 38
Then, the level of the read stop signal on the line 37 becomes H, and a read stop command is issued. When the level of the line 38 is H,
Since cells are transferred to the second cell buffer at the cross point, if reading is performed from the second cell buffer, cells may be transmitted to the same outgoing line at the same cross point. The order may be reversed. Therefore, cell reading is stopped to guarantee the cell order.

The operation of the cross point 10ij of the sub-switch 20kL will be described with reference to FIG. The cell transferred to the line 53i refers to the RB by the AF (address filter) 138 in the cross point, and if the RB matches the address of the cross point, the cell is temporarily stored in the first output buffer 39. At the same time, a cell output request is issued to the first control circuit 41 via the line 42. The first control circuit 41 performs contention control on the cross points 1011 to 1044 having cell output requests on the same output lines 4L1 to 4L4 in the sub-switch 20kL. This contention control is performed within the sub-switch 20kL, and is therefore called sub-contention control. Wins sub competition control (OK)
In this case, the cell is output from the first output buffer 39 to the output line 51.
j, and the Arb1 result signal on the line 56i is set to level L.
(OK). In the case of losing (NG) in the sub contention control, cells are read from the first output buffer 39, accumulated in the second output buffer 46, and the Arb1 result signal 56i is set to level H (NG). The first control circuit 41 notifies the second control circuit 48 that the cells are accumulated in the second output buffer 46 (cell output request), losing the sub contention control.

Second control circuit 48 informed that cells are stored in second output buffer 46 (cell output request).
Performs sub-contention control on crosspoints 1011 to 1044 having cell output requests on the same output lines 4L1 to 4L4. If the sub contention control has been won (OK), the cell is sent from the second output buffer 46 to the line 52j, and the Arb2 result signal on the line 59i is set to the level L (OK). If the sub-contention control is lost (NG), the cell is read from the second output buffer 46, and the cell is stored in the first output buffer 39 via the cell signal line 50, and
The 9b Arb2 result signal is set to level H (NG). The second control circuit 48 determines that the cells are accumulated in the first output buffer 39 (cell output request), losing the sub-contention control.
The first control circuit 41 is notified via the line 51. Also,
The RB signal is input to the input port units 321 to 321 via the line 60i.
324. The first control circuit 41 notified of the cell output request performs the same operation as when the cell output request is received on the line 42.

FIG. 9 shows a time chart in the sub-switch according to the second embodiment of the present invention. Input buffer 21i
Has cells A1, B1, A2, A3, and C1 having destination A, destination B, destination A, destination A, and destination C in order from the top. First, in the cell cycle T1, A1 is read from the input buffer 21i, input to the first output buffer 39, and the contention control is performed.
The rb1 result signal becomes “H”. A1 is transferred to the second output buffer 46 (T1). In the cell cycle T2, B1 is transmitted from the input buffer 21i. B1
Is output to the line 51j via the first output buffer 39 because the result of the contention control is OK. At the same time, the contention control of A1 is performed in the second output buffer 46. However, since the result is NG again, the Arb2 result signal becomes “H”, and A1 becomes the first output buffer 3 via the cell line 50.
9 (T2). In the cell cycle T3, A1 is output to the line 51j via the first output buffer 39 because the result of the contention control is OK. At this time, Ar
Since the b2 result signal is "H", the reading of A2 is stopped by the reading stop signal (T3). In the cell cycle T4,
A2 is transferred from the input buffer 21i to the first output buffer 39 to perform contention control. Since the result is NG, the Arb1 result signal becomes "H". A2 is transferred to the second output buffer 46. At this time, the RBs of A2 and A3 match, and the read of A3 is stopped by the read stop signal because the Arb1 result signal is "H" (T
4). In the cell cycle T5, A2 has passed from the second output buffer 46 to the line 52 because the result of the contention control was OK.
j (T5). In the cell cycle T6, A3
Is transferred from the input buffer 21i to the first output buffer 39 to perform contention control. Since the result is OK, it is output to the line 51j (T6). In the cell cycle T7, C1 changes from the input buffer 21i to the first output buffer 3
9, the contention control is performed, and the result is OK, C1 is output to the line 51j (T7).

Further, main contention control between the sub switches is performed, and as a result, output buffers 1251 to 1254 are output.
Is read from the cell.

In the second embodiment of the present invention, the use of a cross point of one input and two outputs in the sub-switch increases the chance of transmitting cells from the input buffer as compared with the first embodiment of the present invention. HOL blocking is further reduced as compared with the embodiment.

(Summary of Embodiment) The sub-switch system in the first embodiment of the present invention is based on an input buffer type switch system, and is provided with an output buffer for main contention control. The sub-switch in the embodiment is of an input / output buffer type using a one-input / two-output cross point.
Used for main contention control. As described above, the present invention can be applied to a sub-switch of another system as long as the sub-switch has an input buffer and an output buffer in the sub-switch.

As described above, by distributing the input buffers for each sub-switch, each cell is dispersedly stored in the input buffer of the sub-switch having the destination output line. The load of incoming traffic is reduced. Therefore, HOL blocking can be reduced, and the throughput of the main switch can be improved.

Further, the conflict control between the cross points is made into two-stage conflict control by the sub conflict control in the sub switch and the main conflict control between the sub switches, so that the sub conflict control operates independently. Therefore, even if the switch size of the main switch is increased, the problem that the conventional competitive control method is difficult to mount because the propagation delay of the electric signal is large can be solved. Therefore, according to the present invention, an ATM switch having expandability can be realized.

[0052]

As described above, according to the present invention,
Since the HOL blocking can be reduced, the throughput can be improved. Further, an ATM switch with high expandability can be realized.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of an ATM communication network.

FIG. 2 is a block diagram of the ATM switch according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a sub switch according to the first embodiment of the present invention.

FIG. 4 is a diagram for explaining contention control according to the first embodiment of the present invention.

FIG. 5 is a diagram showing the operation of an output buffer.

FIG. 6 is a block diagram of a sub-switch constituting a main switch.

FIG. 7 is a block diagram of an i-th input port unit.

FIG. 8 is a block diagram of a cross point according to a second embodiment of the present invention.

FIG. 9 is a time chart showing the operation of the sub-switch according to the second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration example of a conventional input buffer type ATM switch.

FIG. 11 is a block diagram showing a configuration example of a cross point.

[Explanation of symbols]

31, 40, 47, SEL Seretak 34, 35, 36, 37, 38, 42, 43, 44, 4
5, 49, 561 to 564, 591 to 594, 80, 2,
41-24V, 231-23V, 251-25W, 26
1-26W, 1921-192W, A, B, C, 511
514, 521 to 524, 571 to 574, 601 to
604 line 39 first output buffer 41 the first control circuit 46 the second output buffer 48 the second control circuit 50 cell signal line 138,5k1~5kV, 400 address filter 311~3SV, IN ₁ ~IN _n, 3k1~3kV input line 321 to 324 input port section 411~4TW, OUT ₁ ~OUT _m, 4L1~4LW
Output line 6k1-6kV, 211-214 Input buffer 81j-8Sj, 401 Control circuit 1011-1044, 1911-19nm Cross point 1251-1254, 7L1-7LW, 71j-7Sj
Output buffer 2011-20ST Sub-switch TE1, TE2, TE3, TE1 ', TE2', TE
3 'terminal device

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsuneo Matsumura 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-63-62432 (JP, A) JP-A-3-179850 (JP, A) JP-A-63-142738 (JP, A) JP-A-6-205041 (JP, A) JP-A-10-117196 (JP, A) JP-A-10-51461 (JP JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (2)

(57) [Claims] 1. For N input lines and M output lines
Each having V input terminals and W output terminals.
S × T switches (N = V × S, M
= W × T), and each of the sub-switches reaches V input terminals
Of the cells to be connected to the W output terminals
V address filters to identify each and this address
Provided for the filter and passed through this address filter
Cells are temporarily stored and the read output is the W output terminals.
Each of the V sub-switches of the T sub-switches arranged in the same row.
The input terminals are connected in common to the input lines for each of the V terminals, and each W terminal of the S sub switches arranged in the same column
Each output terminal is connected in common to every W output lines, and each sub-switch has its own
And independent of each other to prevent collision of cells sent to the same output line.
Equipped with conflict control means to avoid, Any of the W output lines read from the input buffer
The first output buffer temporarily stores cells to be sent to the
To avoid cell collisions for the same output line.
Output of the cell read from the first output buffer
A first conflict control means for selecting a route and the first conflict
Whether the output route is selected as the output line by the control means
The same output as the second output buffer that temporarily stores
This second to avoid cell collisions towards power lines
Select output route of cell read from output buffer
Conflict control means between sub-switches including second conflict control means
With steps An ATM switch, characterized in that: 2. The second conflict control means according to claim 2,
The output route is selected as the output line by the contention control means.
2. The ATM switch according to claim 1 , further comprising means for returning a missing cell to said first output buffer .