JPH08331101A - Frequency division multiplex signal transmitter - Google Patents

Abstract

PURPOSE: To provide a frequency division multiplex signal transmitter which monitors an outside band modulation signal and prevents transmission. CONSTITUTION: A signal R and a signal I are inputted to 1st to 128th Input terminals and to 384th to 511th terminals of the IDFT arithmetic part of an arithmetic part 4, and also, a constant voltage is inputted to 0th terminal, and zero is inputted to 129th to 383rd input terminals, and a double over-sampling IDFT arithmetic operation is executed. Consequently, a signal I and a signal Q are obtained. Thence, the modulation output R' signal and I' signal of the signal I and the signal Q are obtained by applying the IDFT arithmetic operation to the signal I and signal Q, and when the absolute value of either one of parts equivalent to a prescribed frequency exceeds a prescribed value, the signals I and Q are not inputted to an output buffer 5. The signal I and the signal Q are outputted to the output buffer 5 only when no outside band modulation signal is generated from the arithmetic part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency division multiplex signal transmitter, and more particularly to orthogonal frequency division multiplex (OFD) of a limited frequency band for encoded digital video signals.
M: Orthogonal Frequency Division Multiplex) The present invention relates to an orthogonal frequency division multiplex signal transmission device for converting and transmitting.

[0002]

2. Description of the Related Art One of the methods for transmitting coded digital video signals in a limited frequency band is 25
6 Quadrature Amplitude Modul (QAM)
ation) and the like, an OFDM method for transmitting multi-value modulated digital information as an OFDM signal using a large number of carriers is conventionally known. This OFDM system is a system in which a large number of carriers are arranged orthogonally and independent digital information is transmitted on each carrier. The phrase "carriers are orthogonal to each other" means that the spectrums of adjacent carriers become zero at the frequency position of the carrier.

According to this OFDM system, since a guard band period (guard interval) is set and information of the period is transmitted redundantly, transmission distortion caused by multipath of radio waves can be reduced. That is, in the reception of this OFDM signal, the amplitude and phase modulation components of the signal transmitted within the symbol period are detected, and the information value is decoded by these levels, so the signal of the first guard interval period is By removing and decoding
Since the frequency components of the multipath signal in the same symbol section and the signal to be received are the same, decoded digital data with less transmission distortion can be transmitted in a relatively narrow frequency band.

Conventionally, the above OFDM signal is generated by using a single inverse fast Fourier transform circuit (IFFT circuit). When the IFFT circuit is a power 2 ^L of length N of the data series 2, the circuit discrete Fourier transform of size N the (DFT) size is decomposed into N / 2 the DFT performed by multiplexing butterfly operation When the order is k, a signal of a value (level) corresponding to the digital value to be transmitted is given to the terminals of the real number part and the imaginary number part of k, and the signal for transmitting the digital value is obtained. It is known that performing an inverse DFT (IDFT) operation using N complex numbers during a time interval T can generate an OFDM signal, and each point of the inverse DFT corresponds to a carrier (see "Data compression and digital modulation"). ], Nikkei Electronics Book, 233
page).

Since a large number of information carriers generated using this IFFT circuit are modulated and transmitted according to the information to be transmitted, the OFDM signal which is a frequency division multiplexed signal of these information carriers is a random signal. Take a form.

Here, the IFFT circuit operates at a sample clock frequency higher than a predetermined frequency bandwidth. For example, N-point IDFT with double oversampling
In the case of using the input frequency aligned IDFT circuit as the IFFT circuit, the 0th to [N /
4] th input terminal, and [3N / 4] to [N-1] th
Digital information is input to the second input terminal to perform an arithmetic operation to generate an OFDM signal within the modulation band.

[0007]

For example, in the case of calculating N-point IDFT by double oversampling, the 0th to [N / 4] th input terminals of the input frequency aligned IDFT circuit and the [3N / Nth] input terminal. 4] to [N-1] -th input terminals to which digital information is input and modulation in-band OFDM
Conventionally, when generating a signal, the [(N / 4) +1] to
The signal level is set to zero at the [(3N / 4) -1] th input terminal so that an out-of-band signal is not generated.

In reality, however, the IDFT operation involves a multi-stage butterfly operation, and as a result an output signal is generated. Therefore, if an error occurs in the operation sequence for some reason, it should not be generated. This may result in modulated signals. In addition, the calculation result due to insufficient dynamic range of the D / A converter for the peak voltage generated when the phases of the maximum amplitude values of many information carriers are the same, which is a problem of the OFDM signal in which many information carriers are combined. It has been reported that the saturation of the signal occurs, which causes out-of-band modulation signals that should not be generated (Yiyan Wu et al. "OFDM for Digital Telev
ision Terrestrial Distribution overChannel with Mu
ltipath and Non-linear Distortions ", Workshop on HD
TV '94, 26-28 October 1994, Turin, Italy).

The present invention has been made in view of the above points,
An object of the present invention is to provide a frequency division multiplex signal transmitter that monitors an out-of-band modulated signal and prevents transmission.

[0010]

In order to achieve the above-mentioned object, the present invention has N (where N is a natural number of powers of 2) input terminals in each of the real part and the imaginary part, and the N 0th to [N / ^2a ] th input terminals (where a is a power of 2 and is a natural number smaller than N) among the input terminals, and [[ ^2a- 1) N / The digital signals to be transmitted are respectively input to the ^2a ] th to [N-1] th input terminals, and 0 is input to the remaining input terminals, and the inverse discrete Fourier transform is performed by a times oversampling. Of the first arithmetic means for performing, the second arithmetic means for performing a discrete Fourier transform on the signal obtained by the arithmetic operation by the first arithmetic means, and the value obtained by the arithmetic operation by the second arithmetic means, Within the desired transmission frequency band w of the signal output from the first computing means And, the high frequency side of the transmission frequency band w (a
-1) w / 2 frequency band and (a-1) w / on the low frequency side
Comparing means for comparing whether or not each absolute value of the frequencies corresponding to the two frequency bands is greater than or equal to a predetermined value, and when the comparison means obtains a comparison result in which all the absolute values are less than or equal to a predetermined value. Output control means for outputting the operation result of the operation means, an output buffer for inputting the operation result of the first operation means, and continuously reading the operation result, and an output signal of the output buffer directly or converted to an analog signal. Quadrature modulation means for quadrature-modulating the input signal and outputting a quadrature frequency-division multiplexed signal composed of a plurality of multi-value-modulated carriers, and transmission means for transmitting the quadrature frequency-division multiplexed signal output from the quadrature modulation means. It is configured to have and.

Further, the present invention is characterized in that it has an alarm means for issuing an alarm when the comparison means obtains a comparison result in which one of the absolute values is larger than a predetermined value.

[0012]

According to the present invention, the first computing means performs the inverse discrete Fourier transform with oversampling of a times and outputs the signal on the high frequency side of the transmission frequency band w with respect to the desired transmission frequency band w. Since the absolute values of the frequencies corresponding to the frequency band of (a-1) w / 2 and the frequency band of (a-1) w / 2 on the low frequency side are originally 0, the second calculation means The absolute values outside the desired transmission frequency band are monitored by performing a discrete Fourier transform on the calculation result of the first calculation means.

Then, it is compared whether or not each of these monitored absolute values is equal to or more than a predetermined value, and when the comparison results of all of these absolute values are equal to or less than the predetermined value, the first normal operation is normally performed.
The calculation means determines that the inverse discrete Fourier transform has been performed with a times oversampling, and transfers the calculation result to the output buffer.

On the other hand, when any of the above absolute values is larger than the predetermined value, there is an abnormality in the operation of the first operation means, and there is an out-of-band modulated signal whose transmission / reception is prohibited by the Radio Law. When it is judged that it has occurred, the transfer of the calculation result to the output buffer is prohibited. When the transfer to the output buffer is prohibited, an alarm can be issued by the alarm means.

Here, in the present invention, the first and second arithmetic means, the comparing means and the output control means are each constituted by a single digital signal processor, or the first arithmetic means is a first digital signal processor. One digital signal processor, and the second arithmetic means, the comparison means, and the output control means are each constituted by a second digital signal processor.

[0016]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of a first embodiment of a frequency division multiplex signal transmitter of the present invention. In the figure, digital data to be transmitted is input to the input terminal 1. The digital data is, for example, a digital video signal or audio signal compressed by an encoding method such as an MPEG method which is a color moving image encoding display method. This input digital data is supplied to the input circuit 2 and, if necessary, an error correction code is added based on the clock from the clock frequency divider 3. The clock frequency divider 3 divides the intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 9 to generate a clock synchronized with this intermediate frequency.

The digital data to which the error correction code is added is supplied from the input circuit 2 to the arithmetic unit 4. The operation unit 4 is a circuit that constitutes a main part of the present embodiment, and includes an IDFT operation unit that performs an inverse discrete Fourier transform (IDFT) operation to generate an in-phase signal (I signal) and a quadrature signal (Q signal). The I signal and the Q signal should not be further generated from the DFT operation unit which further performs the discrete Fourier transform (DFT) operation to generate the R ′ signal and the I ′ signal, and the values of these R ′ signal and the I ′ signal. The detection determination unit detects whether or not an out-of-band modulated signal is generated, and outputs or prevents output of the I signal and the Q signal based on the detection result.

The operation of the arithmetic section 4 will be further described with reference to the flowchart of FIG. As an example, the data series M
Is transmitted on 256 carrier waves, in double oversampling, NFT = 2M = 512 IDFT operations are performed to generate a signal. The input allocation to the IDFT calculation unit at this time is as follows if the numbers are sequentially assigned in the input frequency alignment type.

An information signal is provided which modulates a carrier wave n = 0-128.

N = 129 to 383 Carrier level is 0
And does not generate a signal.

N = 384-511 An information signal for modulating a carrier is provided.

That is, the number of input terminals of the IDFT operation unit is 512 for the real part (R) signal and 512 for the imaginary part (I) signal, of which 127 (n = 1) to 127 are the first.
127 pieces in total up to the nth (n = 127) and 1 pieces in total from the 385th (n = 385) to the 511th (n = 511)
Information signals are input to 27 input terminals each, and 0
The DC voltage (constant) is input to the th (n = 0) th input terminal and transmitted at the center frequency of the carrier wave.
For example, a fixed voltage for the pilot signal is input to the nth (n = N / 4) and 384th (n = 3N / 4) input terminals, and both ends are equivalent to a frequency that is 1/2 times the Nyquist frequency. It is transmitted by a carrier wave of the frequency.

Here, as shown in FIG. 3, which will be described later, the input information from a total of 128 input terminals from the first to the 128th is transmitted by the information transmission carrier above the central carrier frequency F0 (high frequency side). The input information from a total of 128 input terminals from the 384th to the 511th is transmitted by the information transmission carrier below the center carrier frequency (low band side). Also,
0 is input to the remaining 129th to 383rd input terminals (set to the ground potential) so that the carrier wave of that portion is not generated (not used for data transmission).

As described above, the operation unit 4 first inputs the 4-bit R signal and the 4-bit I signal to the 1st to 128th input terminals and the 384th to 511th input terminals of the IDFT operation unit, respectively. At the same time, a constant voltage is input to the 0th input terminal and 0 is input to the other 129th to 383rd input terminals (step 21), and the double oversampling IDFT operation is performed. An in-phase signal (I signal) and a quadrature signal (Q signal) are obtained (step 22).

Here, "-25" shown in step 22 is displayed.
6 ″ and “+256” are the 256th (n
= N / 2) the signal input to the input terminal is transmitted 2
For one carrier frequency, "-129" is {(3N / 4)-
The carrier frequency at which the signal input to the 1} th input terminal is transmitted, and "+129" is the carrier frequency at which the signal input to the {(N / 4) +1} th input terminal is transmitted. Here, as described above, "-256" to "-1"
The amplitude levels of carrier frequencies of 29 "and" +129 "to" +256 "are 0 in the normal case.

Next, the operation section 4 normalizes the I and Q signals obtained by the IDFT operation and then performs the DFT operation to obtain demodulated signal outputs R'and I'signals of the I and Q signals (steps). 23). Here, (I) when the data word length of the DFT operation is 16 bits and the D / A converter is 10 bits, processing for saturating the 14th to 5th bits to the maximum value or the minimum value in the state of the upper 2 bits 14th after doing
A DFT operation is performed on 10 bits of 5 bits.

"-256" of the R'and I'signals
The value of the portion corresponding to the frequencies of "-129" and "+129" to "+256" is originally "0" because 0 is input to the 129th to 383rd input terminals of the IDFT calculation unit. However, when an out-of-band modulation signal is generated due to the above-mentioned device failure or other causes or the occurrence of a peak voltage, it takes a certain value other than "0".

Therefore, "-25" of the R'and I'signals
It is compared whether or not the absolute value of any one of the frequencies corresponding to the frequencies of 6 "to" -129 "and" +129 "to" +256 "is larger than a predetermined value (step 24), and When the absolute values of all the parts are smaller than the predetermined value, it is determined that the out-of-band modulation signal is not generated, and the guard interval for reducing the multipath distortion is inserted in each of the I signal and the Q signal. After that (step 25), the data is output to the output buffer 5 (step 26).

On the other hand, in step 24, the R'and I'signals "-256" to "-129" and "+129" to "+" are added.
When the comparison result that the absolute value of any one of the portions corresponding to the frequency of 256 "is larger than the predetermined value is obtained, the operation unit 4 determines that the out-of-band modulated signal is generated. After making a judgment and displaying a warning on the display unit 6 of Fig. 1 (step 27), the process returns to step 21. Therefore, in this case, the above-mentioned I signal and Q signal are not output to the output buffer 5. To prevent output.

The above-described processing of steps 21 to 26 or 27 is performed at every symbol interval. In addition to the display on the display unit 6, the warning display in step 27 may be performed by a sound such as a buzzer.

In this way, the I signal and the Q signal are input from the arithmetic unit 4 to the output buffer 5 only when the out-of-band modulated signal is not generated. The role of the output buffer 5 will be described. As the output operation result of the operation unit 4, 256 pieces of input information are burst-generated as 512 time-axis signals (I signal and Q signal) in one IDFT operation. The circuits after the output buffer 5 continuously operate at a constant reading speed of the contents of the output buffer 5. Therefore, the output buffer 5 is provided to adjust the time difference between the two.

When 256QAM is used for the OFDM modulation method, 256 bytes are converted for transmission in one IDFT operation. Information transmission speed of 100 kbyte
In the case of es / s, the IDFT calculation is performed every 2.56 ms, and the output buffer 5 outputs the I signal and Q as the calculation result.
The signal is written. In a normal transmitter, ID
The speed of the FT operation is configured to meet this.

Further, in the case of the data written in the output buffer 5, in the above example, 512 points of data are read out in a time of 2.56 ms, so 200 kHz (= 512 /
(2.56 × 10 ⁻³ )) continuous clock is used.
This is the sample clock frequency.

In this embodiment, the system is configured so that the IDFT calculation time is 1/2 or less of the information transmission speed, in other words, the information transmission speed is 1/2 or less of the calculation time, and the remaining half time is used. Is to perform the DFT operation on the IDFT operation result. Specifically, for an information transmission rate of 100 kbytes / s, the IDFT calculation is 2.56 / 2 ms.
It will be implemented at the following times.

Thereafter, the IDFT calculation result is set to 2.56 / 2.
DFT calculation is performed in a time of ms or less. In general, the arithmetic unit 4 is composed of a digital signal processor (DSP), which performs IDFT arithmetic.
Sharing with arithmetic is easy.

Based on the clock from the clock frequency divider 3 of FIG. 1, the I and Q signals, which are the IDFT operation results continuously read from the output buffer 5, are D / A converter / low band. The signal is supplied to a filter (LPF) 7, where the clock from the clock frequency divider 3 is converted into an analog signal using the sampling clock as a sampling clock, and then the I signal and the Q signal of components of a required frequency band are passed by the LPF, At the same time, the glitch signal and the harmonic distortion components are removed and supplied to the quadrature modulator 8.

The quadrature modulator 8 uses the intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 9 as the first carrier wave, and the phase of this intermediate frequency is 9 ° by the shifter 10.
A 257-wave information carrier is obtained by performing quadrature amplitude modulation (QAM) with the I signal and Q signal of the digital data input from the D / A converter / LPF 7 using the 10.7 MHz intermediate frequency shifted by 0 ° as the second carrier. Consisting of OFDM
Generate a signal.

That is, in this embodiment, the I signal and the Q signal obtained by digital operation are digital-to-analog converted and supplied to the quadrature modulator 8 so that the center frequency F0 from the quadrature modulator 8 is 10.7 MHz. Figure 3
An OFDM signal having a frequency spectrum as shown in is extracted.

The OFDM signal in the case where the data sequence of the operation unit 4 is 2N = 512 has 257 wave carriers in total within the frequency band 99 kHz, of which 248 wave carriers are 256QAM modulated with 1 byte of information data. The remaining 9 carrier waves including the center frequency F0 are used for the transmission of the auxiliary signal.

However, in the frequency spectrum of the OFDM signal in this case, as shown in FIG. 3, carriers on the higher frequency side than the center frequency F0 are input to the 1st to 128th real part of the IDFT operation unit of the operation unit 4. The carrier wave which is modulated by the data input to the terminal and the imaginary part input terminal and which is on the lower frequency side than the center frequency F0 is the 384th to 511th real part input terminals and the imaginary number of the IDFT operation unit of the operation unit 4. It is modulated by the data input to the input terminal.

As described above, "128" shown in FIG. 3 is a pilot signal generated by the fixed voltage input to the 128th real part input terminal and imaginary part input terminal of the IDFT operation unit of the operation unit 4 described above. It is a carrier wave for transmission.
128 ″ is a carrier for pilot signal transmission generated by the fixed voltage input to the 384th real part input terminal and the imaginary part input terminal of the IDFT operation part of the operation part 4, and these are 1/2 times the Nyquist frequency. It is a carrier wave of a frequency that is equivalent to the frequency.

Further, the IDFT calculation unit 129 of the calculation unit 4
Since 0 is input to the 3rd to 383rd input terminals, as shown in FIG. 3, data of those input terminals in the OFDM signal is transmitted from "129" to "256" and "-256" to The carrier wave of "-129" is 0.

The above-mentioned OFDM signal, which is extracted from the quadrature modulator 8 and consists of a plurality of carriers arranged adjacent to each other for each symbol frequency, is supplied to the frequency converter 11 of FIG. 1 and frequency-converted into a transmission frequency band. For example, after the center carrier frequency F0 is set to 100 MHz, it is linearly amplified by the transmission unit 12 and transmitted from the transmission antenna.

As a result, the specifications of the signal transmitted by the transmitter of FIG. 1 are that the signal center frequency is 100 MHz and the transmission bandwidth is 100 kHz (actually 99 kHz as shown in FIG. 3).
z), modulation method 256QAM, OFDM, the number of carriers used is 257 (of which 248 are carriers for information transmission),
The guard interval is 60 μsec.

As described above, according to this embodiment, it is possible to prevent the transmission of out-of-band frequency components that are legally undesirable. Further, according to the present embodiment, the IDFT is executed by the DSP.
Since the arithmetic unit 4 that performs arithmetic operations and DFT operations can be configured,
It can be realized without the burden of software technology development. Furthermore,
In the present embodiment, by mounting a DSP having a somewhat high speed, it can be realized without adding hardware, which is also effective in terms of development man-hours, cost, and miniaturization.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a block diagram of a second embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and their description will be omitted. In FIG. 4, the arithmetic unit 31 includes the first to 128th input terminals of the real number part and the imaginary number part and 384
For each input terminal of the real part and the imaginary part from the 5th to the 511th part,
The 4-bit R signal and the 4-bit I signal from the input circuit 2 are respectively input, and a constant voltage is input to each input terminal of the 0th real number part and the imaginary number part. 0 is input to the second input terminal (step 21), and the double oversampling IDF is input.
T operation is performed, and as a result, an in-phase signal (I signal) and a quadrature signal (Q signal) are obtained.

The arithmetic unit 32 is supplied with the above-mentioned I signal and Q signal obtained by the arithmetic unit 31, normalizes them, and then performs DFT operation to output demodulated signals of I and Q signals R'signal and I'signal. After obtaining the R'signal and I '
Signals "-256" to "-129" and "+129" to "
It is compared whether or not the absolute value of any one of the parts corresponding to the frequency of +256 "is larger than a predetermined value, and when the absolute values of all the above parts are smaller than the predetermined value, it is out of the band. It is determined that a modulated signal is not generated, and a guard interval for reducing multipath distortion is inserted in each of the input I signal and Q signal, and then output to the output buffer 5.

Further, the arithmetic unit 32 has the R'signal and I '
Signals "-256" to "-129" and "+129" to "
If a comparison result is obtained that the absolute value of any one of the parts corresponding to the frequency of +256 "is larger than the predetermined value, it is determined that the out-of-band modulated signal is generated. , While displaying a warning on the display unit 6,
The transfer of the input I signal and Q signal to the output buffer 5 is prohibited.

As described above, according to this embodiment, similarly to the first embodiment, it is possible to prevent transmission of out-of-band frequency components that are legally undesirable. Further, the IDFT operation is performed by the operation unit 31, and the DFT operation and the subsequent DFT operation value determination processing and the IDFT operation result transfer control processing are performed by the operation unit 32.
Each of them is performed separately, and each of them can be easily realized by a DSP having the same information transmission speed.

Further, according to this embodiment, the arithmetic units 31 and 3 are
The reliability of the entire apparatus can be further improved by setting the power supply of each DSP of 2 in a separate system. Furthermore, not only does the data not be sent when an abnormality is detected,
It also becomes easy to initialize (reset) the entire device and create a warning signal to the operator.

By the way, the IDFT operation is generally calculated by a floating point operation or a fixed point operation, and the data word length is generally 16 bits or more. However, the D / A converter in the latter stage and the D / A converter part of the LPF7 are high-speed,
It is difficult to obtain 16 bits or more at present. Therefore, the IDFT calculation result must match the dynamic range of the D / A converter section.

Further, due to the nature of OFDM, peak power may occur with respect to the average power, although the probability is low. However, considering the balance between average power and peak power,
We want to maximize the average power and secure the signal S / N ratio. Therefore, the peak power generated with a very low probability must be saturated. Therefore, in each embodiment, the numerical values are normalized so that a value up to 1/4 of the theoretical peak power value matches the dynamic range of the D / A converter portion.

When the signal is saturated, the linearity of the system cannot be secured at that point, and an unnecessary carrier wave may be generated outside the desired band. In the first and second embodiments described above, such a situation can be detected and the reliability of the device can be secured.

Next, a receiver for the OFDM signal transmitted by the transmitter of this embodiment will be described. 5 is O
The block diagram of an example of an FDM signal receiver is shown. The transmitted OFDM signal is received by the receiving unit 41 via the receiving antenna and then high-frequency amplified, further frequency-converted to an intermediate frequency by the frequency converter 42, amplified by the intermediate-frequency amplifier 43, and then described later. Are supplied to the carrier extraction and quadrature demodulator 44.

The carrier extraction circuit part of the carrier extraction / quadrature demodulator 44 is a circuit for extracting the center carrier (carrier) of the input OFDM signal as accurately as possible with a small phase error. In this embodiment, each carrier that transmits information is
It is arranged adjacent to every 387 Hz which is the symbol frequency and
Since the FDM signal is configured, the information transmission carrier adjacent to the center carrier is also separated from the center frequency by 387 Hz, and in order to extract the center carrier, the information transmission carrier adjacent to the center carrier is separated by only 387 Hz. A highly selective circuit is required so that it is not affected.

Therefore, the central carrier F0 is extracted by using a PLL circuit in the carrier extraction circuit section. However, as the VCO that constitutes the PLL circuit in this case, a voltage-controlled crystal oscillation circuit (VCXO) using a crystal oscillator that oscillates at about ± 200 Hz, which is about ½ of the carrier frequency of the adjacent variable range, is used. L used and configuring a PLL circuit
An LPF having a sufficiently low cutoff frequency with respect to 387 Hz is used as the PF.

The center carrier F0 extracted by the carrier extractor and quadrature demodulator 44 is supplied to the intermediate frequency oscillator 45, where the center carrier F0 is 10.7 phase-locked to the center carrier F0.
Generates an intermediate frequency of MHz. Intermediate frequency oscillator 4
The output intermediate frequency of 5 is directly supplied to the quadrature demodulator 44 as the first demodulation carrier, while the 90 ° shifter 46 shifts the phase by 90 °, and then the carrier extraction and quadrature demodulation are performed as the second demodulation carrier. Is supplied to the container 44.

As a result, from the quadrature demodulator section of the carrier extraction / quadrature demodulator 44, an analog signal (frequency division multiplexed signal) equivalent to the analog signal input to the quadrature modulator 8 of the transmitter is demodulated and taken out. , While being supplied to the synchronization signal generation circuit 47, the low pass filter 48 causes OF
The signal of the required frequency band transmitted as DM signal information is passed and supplied to the A / D converter 49 and converted into a digital signal.

What is important here is the sampling timing for the input signal of the A / D converter 49, which is based on the sample sync signal having a frequency twice the Nyquist frequency generated from the pilot signal by the sync signal generating circuit 47. Is generated. That is, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and the timing of the sample clock is obtained by performing frequency multiplication according to the frequency ratio.

The sync signal generation circuit 47 receives the demodulated analog signal and generates a sample sync signal by a PLL circuit that is phase-locked with a pilot signal transmitted as a continuous signal in each symbol period including a guard interval period. The symbol synchronization signal generation circuit section for generating a symbol synchronization signal by detecting the symbol period by checking the phase state of the pilot signal with the signal extracted from the generation circuit section and part of the sample synchronization signal generation circuit section The system clock generating circuit unit generates a system clock such as a section signal for removing the guard interval period from the signal and the symbol synchronization signal.

The digital signal taken out from the A / D converter 49 is supplied to the guard interval period processing circuit 50, where the influence of multipath distortion is small on the basis of the system clock from the synchronizing signal generating circuit 47. The symbol period signal is obtained and supplied to the FFT and QAM decoding circuit 51.

The FFT (Fast Fourier Transform) circuit section of the FFT / QAM decoding circuit 51 performs a complex Fourier calculation by the system clock from the synchronization signal generation circuit 47, and outputs the output signal of the guard interval period processing circuit 50 for each frequency. The signal levels of the real part and the imaginary part are calculated.

The real part for each frequency obtained in this way,
Each signal level of the imaginary part is compared with the demodulation output of the reference carrier wave by the QAM decoding circuit unit to obtain the level of the quantized digital signal transmitted by the carrier wave for digital information transmission, and the digital information is obtained. Be decrypted. The decoded digital information signal is subjected to output processing such as parallel-serial conversion by the output circuit 52 and output to the output terminal 53.

The present invention is not limited to the above-mentioned embodiments, and it is also conceivable to use an integrated circuit (IC) for fast Fourier transform (FFT) as the arithmetic units 4, 31 and 32, for example. Also, the oversampling is not limited to 2 times, but a times (where a is 2
The present invention can be applied to any power of 10).

Further, although the quadrature modulator 8 has been described as receiving an analog signal, it may be configured to quadrature modulate the digital signals I and Q from the output buffer 5 by digital processing. In this case, , D / A converter / LPF 7 may be deleted, and a D / A converter and a bandpass filter may be provided in series on the output side of the quadrature modulator. The band filter in this case is for suppressing unnecessary frequency components other than the monitoring band.

[0066]

As described above, according to the present invention,
When it is determined by the first arithmetic unit that the operation of the inverse discrete Fourier transform is abnormal due to a-times oversampling, and an out-of-band modulated signal whose transmission and reception are prohibited by the Radio Law is generated, Since the transfer of the calculation result of the calculation means to the output buffer is prohibited, it is possible to prevent the transmission of the out-of-band modulated signal which is prohibited from being transmitted and received by the Radio Law.

Further, according to the present invention, it is possible to prevent transmission even when an out-of-band modulated signal that may occur at the time of signal saturation due to peak power generation is generated, and it is possible to improve the reliability of the device. When the transfer to the output buffer is prohibited, an alarm can be issued by the alarm means.

Further, according to the present invention, the first and second arithmetic means, the comparing means and the output control means are each constituted by a single digital signal processor, or the first arithmetic means is the first digital signal processor. Of the digital signal processor, and the second arithmetic means, the comparing means and the output control means are respectively constituted by the second digital signal processor. Means can be realized.

Further, according to the present invention, when the first and second calculating means, the comparing means and the output controlling means are respectively constituted by a single digital signal processor, the development man-hour, the cost and the device Effective for downsizing.

Further, according to the present invention, the first arithmetic means is constituted by the first digital signal processor, and the second arithmetic means, the comparing means and the output control means are respectively provided in the second digital signal processor. When the signal processor is used, a digital signal processor having an information transmission speed equivalent to that of the signal processor can be used, and the device can be effectively realized particularly when oversampling is large.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining a process of a main part of the present invention.

FIG. 3 is a diagram showing an example of a frequency spectrum of an OFDM signal transmitted by the transmitter of the present invention.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of an example of a receiving device that receives an OFDM signal transmitted by the transmitting device of the present invention.

[Explanation of Codes] 1 data input terminal 2 input circuit 3 clock divider 4 arithmetic unit (first arithmetic unit, second arithmetic unit, comparing unit, output control unit) 5 output buffer 6 display unit (alarm unit) 7 D / A converter / LPF 8 Quadrature modulator 9 Intermediate frequency oscillator 10 90 ° shifter 11 Frequency converter 12 Transmitter 31 Calculation unit (first digital signal processor: first calculation means) 32 Calculation unit ( Second digital signal processor: second calculating means, comparing means, output controlling means)

Claims (4)

[Claims] 1. A real part and an imaginary part each have N (where N is a natural number of a power of 2) input terminals, and the 0th to [N / 2 of the N input terminals are provided. ^a ] (where a is a power of 2 and is a natural number less than N)
Up to [( ^2a- 1) N / ^2a ] th to [N-1] th input terminals, the digital signals to be transmitted are input, and the remaining input terminals have 0s. And a second arithmetic means for performing an inverse discrete Fourier transform by oversampling by a times, and a second arithmetic means for performing a discrete Fourier transform on the signal obtained by the arithmetic operation by the first arithmetic means. Among the values obtained by the calculation by the second calculating means,
With respect to the desired transmission frequency band w of the signal output from the first computing means, the high frequency side (a-1) w / 2 frequency band of the transmission frequency band w and the low frequency side (a-1) -1)
Comparison means for comparing whether or not each absolute value of the frequencies corresponding to the w / 2 frequency band is greater than or equal to a predetermined value, and the comparison means obtains a comparison result in which all the absolute values are less than or equal to the predetermined value. When the comparison result that any one of the absolute values is larger than the predetermined value is obtained, the first calculation means outputs the calculation result of the first calculation means.
Output control means for prohibiting the output of the calculation result of the calculation means, an output buffer to which the calculation result of the first calculation means is input and which continuously reads this, and an output signal of the output buffer is a direct or analog signal. Quadrature modulation means for converting and inputting, quadrature-modulating this, and outputting a quadrature frequency division multiplex signal composed of a plurality of multi-value modulated carriers, and a quadrature frequency division multiplexing signal output from the quadrature modulation means A frequency division multiplex signal transmission device, comprising: 2. The alarm means for issuing an alarm when the comparison means obtains a comparison result in which one of the absolute values is larger than the predetermined value. Frequency division multiplex signal transmitter. 3. The first and second calculation means, the comparison means and the output control means are each constituted by a single digital signal processor. A frequency division multiplex signal transmission device as described. 4. The first computing means is composed of a first digital signal processor, and the second computing means, the comparing means and the output control means are respectively second digital signal processors. The frequency division multiplex signal transmitter according to claim 1 or 2, wherein