JPH09107345A - Frequency division multiplex signal generator and decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the frequency division multiplex signal generator by which miniaturization and light weight of a transmitter are attained by generating a frequency division multiplex signal of plural groups and controlling the polarity of the frequency division multiplex signal so as to reduce a peak power. SOLUTION: An inverse high speed Fourier transformation (IFFT) circuit 33 divides input real number part data and input imaginary number part data respectively into plural numbers, and plural arithmetic sections conduct IFFT arithmetic operation. Plural peak detection circuits 37-40 detect a peak power and a peak position of the frequency division multiplex signal outputted from the circuit 33 for each group. When a peak power of a prescribed value or over is detected, polarity control circuits 42-45 set the polarity of the frequency division multiplex signal of other groups in a direction to cancel the peak power of a prescribed value or over to suppress instantaneous power. The IFFT circuit 34 applies IFFT arithmetic operation to a polarity control signal from the data polarity discrimination circuit 41. An adder circuit 46 adds output signals of the circuits 33, 34 to provide an output of a signal whose peak power is suppressed to a prescribed value or below to an orthogonal modulator 47.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency division multiplexing signal generator and a decoding apparatus, and more particularly to an orthogonal frequency division multiplexing (OFDM) of a limited frequency band for encoded digital video signals.
The present invention relates to a frequency division multiplex signal generating device for generating a signal and a decoding device for decoding the OFDM signal.

[0002]

2. Description of the Related Art One of the methods for transmitting coded digital video signals in a limited frequency band is 25
6 Quadrature Amplitude Modul (QAM)
ation) and other multi-value modulated digital information is transmitted as an OFDM signal using a large number of carriers, the OFDM method is more resistant to multipath, less susceptible to interference, and has relatively good frequency utilization efficiency. Are known.

This OFDM system is a system in which a large number of carriers are arranged orthogonally and independent digital information is transmitted on each carrier, and the OFDM signal takes the form of a random signal. The phrase "carriers are orthogonal to each other" means that the spectrums of adjacent carriers become zero at the frequency position of the carrier.

According to this OFDM system, since a guard band period (guard interval) is set and information of the period is transmitted redundantly, transmission distortion caused by multipath of radio waves can be reduced. That is, in the reception of this OFDM signal, the amplitude and phase modulation components of the signal transmitted within the symbol period are detected, and the information value is decoded by these levels, so the signal of the first guard interval period is By removing and decoding
Since the frequency components of the multipath signal in the same symbol section and the signal to be received are the same, decoded digital data with less transmission distortion can be transmitted in a relatively narrow frequency band.

[0005]

However, in the related art, a large amount of power is rarely generated because no measures have been taken against the peak power that occurs instantaneously for an OFDM signal formed by combining a large number of information carriers. Sometimes. For example, the power of an OFDM signal using 256 information carriers is an average power that is 256 times the power of one information carrier, so if the maximum amplitude voltage values of all the information carriers are generated in agreement, 655, which is the square of 256
36 times. Therefore, if the power of one information carrier is 1 m
If W, the average power obtained by combining these 256 information carriers is about 256 mW, but becomes 65 W when the maximum amplitude positions of all the information carriers match.

Therefore, in the conventional frequency division multiplex signal generator, the probability that the maximum amplitude values of all the information carriers match is very small and practically does not occur, but the average power value is a low value with a margin. And a transmission power device capable of generating a large output signal with a margin of about 10 to 20 times the average power (a device capable of generating 2.5 W to 5 W when the power of one information carrier is 1 mW). ) Was used so that even high power signals that occur infrequently can be transmitted without being saturated. Therefore, the conventional frequency division multiplex signal generator has a problem that the entire device is expensive and becomes large in size.

The present invention has been made in view of the above points. By reducing the peak power of the generated frequency division multiplexed signal, the transmitter can be made smaller and lighter, including the power supply of the transmitter. An object of the present invention is to provide a frequency division multiplex signal generator and a decoding device to be obtained.

[0008]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a first method for separately modulating a plurality of divided digital information signals to generate a plurality of groups of frequency division multiplexed signals. Operation circuit, a plurality of peak detection circuits for detecting the peak power and the peak position of the output frequency division multiplexed signal of the first operation circuit for each group, and detection from the corresponding peak detection circuit of the plurality of peak detection circuits. When the peak power of a predetermined value or more is detected based on the signal, the polarity of the frequency division multiplexed signal of the other group from the first arithmetic circuit is set in the direction of canceling the peak power of the predetermined value or more, and the polarity is set. Within the frequency band between the highest frequency and the lowest frequency of the frequency division multiplexed signal by modulating the polarity information set by the polarity control means and the information generating polarity control means. A second arithmetic circuit which is included and generates a signal different from the frequency division multiplexed signal; an output frequency division multiplexed signal of the first arithmetic circuit whose polarity is controlled by the polarity control means; And an adder circuit for adding and synthesizing the output signal and outputting the result.

As described above, in the present invention, when the peak power of a predetermined value or more is detected in any of the output frequency division multiplexed signals of the plurality of groups of the first arithmetic circuit, the peak power is detected by the polarity control means. After setting the polarities of the frequency division multiplexed signals of other groups different from the group in which is detected to the direction of canceling the peak power of a predetermined value or more, the output frequency division multiplexed signals of the plurality of groups are added and synthesized by the addition circuit. As a result, it is possible to suppress the generation of peak power of a predetermined value or more in the frequency division multiplexed signal that is added and synthesized.

Here, the polarity control information indicating the presence / absence of polarity inversion must be transmitted for correct decoding. The frequency band used for transmission is preferably within the same frequency band as the frequency band of the output frequency division multiplexed signal of the first arithmetic circuit for transmitting the digital information signal. But,
Since information on whether or not the polarity has been inverted can be obtained only after the calculation by the first calculation circuit, it is necessary to devise to transmit in the same frequency band.

Therefore, in the present invention, the first arithmetic circuit is
A carrier hole is set in the frequency band between the highest frequency and the lowest frequency of the frequency division multiplexed signal, and the second arithmetic circuit generates a carrier wave modulated with polarity information at the frequency position of the carrier hole. Thereby, the polarity information can be transmitted within the same frequency band as the frequency band of the output frequency division multiplexed signal of the first arithmetic circuit.

In the present invention, the second arithmetic circuit is the first
The carrier wave modulated by the polarity information is generated in synchronism with the output signal of the arithmetic circuit, and is output at the same timing as the output frequency division multiplexed signal of the first arithmetic circuit. As a result, the signals output from the first and second arithmetic circuits are in an orthogonal relationship and do not interfere with each other.

The first arithmetic circuit according to the present invention is
Each of the plurality of divided digital information signals transmitted on a symbol-by-symbol basis is subjected to inverse discrete Fourier transform separately within the symbol period to generate a plurality of groups of frequency division multiplexed signals. It is characterized in that the information is subjected to an inverse discrete Fourier transform in the same symbol period as the frequency division multiplexed signals of the plurality of groups to generate a modulated carrier.

That is, the second arithmetic circuit may be a single-function arithmetic circuit only for generating the carrier wave modulated by the polarity information, and therefore, the arithmetic processing is performed in a very short arithmetic time as compared with the first arithmetic circuit. Therefore, even if the second arithmetic circuit performs the arithmetic operation after the arithmetic operation of the first arithmetic circuit is completed, the delay time of the transmission due to the operation can be ignored, and the second arithmetic circuit can perform the second arithmetic operation within the same symbol period.
The arithmetic operation of the arithmetic circuit can be finished.

In order to achieve the above-mentioned object, the decoding device of the present invention is a frequency division multiplex signal composed of a plurality of first carrier waves modulated into a digital information signal and divided into a plurality of groups, and these frequency division signals. Modulated with polarity information indicating the presence or absence of polarity inversion of the multiplex signal for each group, and
A decoding operation circuit for inputting a composite signal obtained by frequency-dividing a second carrier, which is a frequency between the highest frequency and the lowest frequency of the plurality of first carriers, and performing Fourier transform operation for decoding, and a decoding operation Multiple polarity corrections that perform polarity correction operations to restore the polarities separately based on the polarity information decoded from the decoding arithmetic circuit for the decoded signals output from the circuit in parallel for each group. It is composed of a circuit.

Here, each of the plurality of polarity correction circuits converts the digital information signal value in which the signal points of the modulation method for the first and second carriers are defined symmetrically with respect to the origin. Therefore, it is desirable in terms of circuit configuration to perform polarity conversion of the digital information signal by referring to the conversion table with the decoded polarity information.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. First, before describing the frequency division multiplex signal generator and decoder of the present invention, an outline of an OFDM signal transmission / reception system to which the frequency division multiplex signal generator and decoder of the present invention is applied will be described. Here, the transmission information is OFD by 256 carrier waves.
Transmit as M signal.

FIG. 4 is a block diagram showing an example of an OFDM signal transmitting / receiving system to which the device of the present invention is applied. In the figure, digital data to be transmitted is input to the input terminal 1. The digital data is, for example, a digital video signal or audio signal compressed by an encoding method such as an MPEG method which is a color moving image encoding method. This input digital data is supplied to the input circuit 2 and, if necessary, an error correction code is added based on the clock from the clock frequency divider 3. The clock frequency divider 3 divides the intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 8 to generate a clock synchronized with this intermediate frequency.

The digital data to which the error correction code is added is supplied from the input circuit 2 to the arithmetic unit 4. The arithmetic unit 4 is composed of an IFFT circuit that performs, for example, an inverse fast Fourier transform (IFFT) operation on input data, and an output buffer that temporarily stores the operation result. As the IFFT circuit that constitutes the arithmetic unit 4, the data series N is 25
6 IFFT circuit and 2N = M = 512 IF
Two examples of the FT circuit will be described. When the IFFT circuit forming the arithmetic unit 4 is the former IFFT circuit, the number of input terminals of the real part (R) is 256, and the imaginary part (I).
The number of input terminals is 256 and the 4-bit digital data is input to 256 input terminals in total for both the real part and the imaginary part, so that the input information of the 0th (k = 0) input terminal is It is transmitted at the center frequency of the carrier wave to be transmitted, and the input information of the k = N / 2, 127th (k = N / 2) input terminal is transmitted at both end frequencies that are equivalent to the Nyquist frequency.

The IFFT which constitutes the IFFT device 4
When the circuit is the latter IFFT circuit, the number of input terminals of the real part (R) is 512, the number of input terminals of the imaginary part (I) is 512, and the 4-bit digital data is the real part and the imaginary part, respectively. The input information of the 0th (k = 0) input terminal is obtained by respectively inputting to 128 input terminals from 0th to 127th and 127 input terminals from 384th to 511th respectively. It is transmitted at the center frequency of the carrier wave to be transmitted, and is the 127th (k = M /
4) and the input information of the 384th (k = 3M / 4) input terminals are transmitted at both end frequencies which are equivalent to the Nyquist frequency.

Here, a total of 1 from the 1st to the 127th
The input information of the 27 input terminals is transmitted by the information transmission carrier above the center carrier frequency (high frequency side), and the input information of a total of 127 input terminals from the 384th to the 511th is below the center carrier frequency. It is transmitted by a carrier wave for information transmission on the side (low band side). The input information at the 127th and 384th input terminals is transmitted at both end frequencies which are equivalent to the Nyquist frequency. Note that 0 is input to the remaining input terminals.

In any of the above cases, of the 258 sets of outputs from the arithmetic unit 4, 2 out of the 257 waves excluding the set of outputs transmitted at the center carrier frequency of k = 0.
Information is transmitted using 48 carrier waves, and the remaining 9 waves are used for calibration and other auxiliary signal transmission. Therefore, 248 bytes of digital data in one symbol period, that is, a pair of parallel data 248 pairs of 4 bits are input from the input circuit 2 to the real part input terminal and the imaginary part input terminal of the arithmetic unit 4 during one symbol period. To be done.

Based on the clock from the clock frequency divider 3, the IFFT operation is performed by the operation unit 4 and is taken out.
A total of 257 sets of output data transmitted by a total of 257 waves of carriers are passed through a guard interval circuit 5 for reducing multipath distortion, and a D / A converter / low-pass filter (L
PF) 6, where the clock from the clock frequency divider 3 is converted into an analog signal using the clock as a sampling clock, and then the LPF passes the real part component and the imaginary part component of the required frequency band for quadrature modulation. It is supplied to the container 7, respectively.

The quadrature modulator 7 uses the intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 8 as the first carrier wave, and the phase of this intermediate frequency is 90 ° by the shifter 9.
° Quadrature amplitude of the real part component (real part data) and the imaginary part component (imaginary part data) of the digital data input from the D / A converter / LPF6, respectively, using the shifted 10.7MHz intermediate frequency as the second carrier wave. Modulation (QAM) is performed to generate an OFDM signal having a frequency spectrum shown in FIG.

The frequency spectrum of FIG. 5A shows the OF when the data sequence of the arithmetic unit 4 is N (= 256).
DM signal frequency spectrum, frequency band 99 kHz
There are a total of 257 carrier waves in z, of which 24
Eight carrier waves are 256QAM-modulated with 1-byte information data, and the remaining nine carrier waves including the center frequency F0 are used for transmitting auxiliary signals.

Here, the carrier wave on the higher frequency side than the center frequency F0 is modulated by the data inputted to the first to 128th real part input terminals and imaginary part input terminals of the IFFT circuit, and the center The carrier wave on the lower frequency side than the frequency F0 is modulated by the data input to the 128th to 255th real part input terminals and imaginary part input terminals of the IFFT circuit.

Further, "128" and "-1" are shown in FIG.
Carriers having a Nyquist frequency are generated at positions indicated by "28", which are carrier waves for pilot signal transmission generated based on the fixed voltage data input to the 128th input terminal as described above. That is, the fixed voltage data input to the same 128th input terminal is
It is transmitted by two carrier waves.

The data sequence of the arithmetic unit 4 is 2N (=
512), the OFDM signal in the frequency band 99
There are 257 carrier waves in total within kHz, of which 248 carrier waves are 1 byte of information data and 256QA.
The remaining 9 carrier waves, which are M-modulated and include the center frequency F0, are used for the transmission of the auxiliary signal.

However, in the frequency spectrum of the OFDM signal in this case, as shown in FIG. 5B, the carrier on the higher frequency side than the center frequency F0 is the first to 128th real part input terminals of the IFFT circuit. And the carrier wave on the low frequency side of the center frequency F0, which is modulated by the data input to the imaginary part input terminal and the like, is 384 of the IFFT circuit.
It is modulated by the data and the like input to the real part input terminal and the imaginary part input terminal of the 5th to 511th parts.

In this case, as shown in FIG.
“128” is a carrier for pilot signal transmission generated by the fixed voltage input to the 128th real part input terminal and the imaginary part input terminal of the IFFT circuit, and “−”
128 "is a carrier for pilot signal transmission generated by a fixed voltage input to the 384th real number part input terminal and the imaginary number input terminal of the IFFT circuit, and these are carrier waves having a frequency 1/2 times the Nyquist frequency. .

The above OFDM signal, which is extracted from the quadrature modulator 7 and is composed of a plurality of carriers that are adjacently arranged at every 387 Hz, which is the symbol frequency of the data before the guard interval processing, is the frequency converter 10 of FIG. To the transmission frequency band, and the center carrier frequency F0 is set to 100 MHz, for example, and then linearly amplified by the transmission unit 11 and transmitted from the transmission antenna.

As a result, the specifications of the signal transmitted by the transmitter of FIG. 4 are that the signal center frequency is 100 MHz and the transmission bandwidth is 100 kHz (actually 99 kHz as shown in FIG. 8).
z), modulation method 256QAM, OFDM, the number of used carriers is 257 waves (of which, the number of information transmission carriers is 248 waves), and the guard interval is 60 μsec. Also, a pair of 4
Since 248 sets of bit data are transmitted on a carrier of 248 waves, the transmission rate is 248 kbytes per symbol period, and therefore the transmission rate (transfer rate) per second is about 750 kbps (≈8 bits × 378 Hz × 248). ÷ 1
000).

Next, the frequency division multiplex signal receiver will be described. The above OFDM signal is received by the receiving unit 13 via the receiving antenna via the spatial transmission line 12 of FIG. 4, is then high-frequency amplified, is further frequency-converted to the intermediate frequency by the frequency converter 14, and is intermediate-frequency amplified by the intermediate-frequency amplifier 15. After being amplified, it is supplied to the quadrature demodulator 16 and the carrier extraction circuit 17.

The carrier extracting circuit 17 is a circuit for extracting the center carrier (carrier) of the input OFDM signal as accurately as possible with a small phase error. Here, since the carrier waves for transmitting information are arranged adjacent to each other at a symbol frequency of 387 Hz to form an OFDM signal, the information transmission carrier adjacent to the center carrier is also separated from the center carrier by 387 Hz. . In order to extract the central carrier wave, the central carrier wave F0 is extracted by using a highly selective PLL circuit so as not to be affected by the adjacent information transmitting carrier waves which are separated by only 387 Hz.

The center carrier F0 extracted by the carrier extracting circuit 17 is supplied to the intermediate frequency oscillator 18, where it generates an intermediate frequency of 10.7 MHz which is phase-locked with the center carrier F0. The output intermediate frequency of the intermediate frequency oscillator 18 is directly supplied to the quadrature demodulator 16 as a first demodulation carrier, while the 90 ° shifter 19 shifts the phase by 90 ° before the quadrature demodulation as a second demodulation carrier. Is supplied to the container 16.

As a result, an analog signal (frequency division multiplexed signal) equivalent to the analog signals of the real number part and the imaginary number part input from the quadrature demodulator 16 to the quadrature modulator 7 of the transmitter.
Is demodulated and taken out, and the sample clock decoding circuit 2
0 while the low pass filter 21 causes OFDM
The signal in the required frequency band transmitted as signal information is passed and supplied to the A / D converter 22 and converted into a digital signal.

The sampling timing for the input signal of the A / D converter 22 is the sampling clock decoding circuit 2
0 is generated on the basis of a sample clock having a frequency twice the Nyquist frequency, which is transmitted from a specific carrier and is set from the pilot signal with a predetermined integer ratio to the sample clock frequency. That is, the sample clock decoding circuit 20 receives the intermediate frequency and the demodulated analog signal and generates a sample clock by the PLL circuit that is phase-locked with the pilot signal transmitted as a continuous signal in each symbol period including the guard interval period. In addition, the symbol synchronization signal decoding circuit 23
Examines the phase state of the pilot signal with this sample clock, detects the symbol period, and decodes the symbol synchronization signal. The system clock generation circuit 24 generates a system clock such as a section signal for removing the guard interval period from the sample clock and the symbol synchronization signal.

The digital signal taken out from the A / D converter 22 is supplied to the guard interval period processing circuit 25, and based on the system clock from the system clock generation circuit 24, the one which is less affected by multipath distortion. The symbol period signal is obtained and supplied to the FFT and QAM decoding circuit 26.

The FFT (Fast Fourier Transform) circuit section of the FFT / QAM decoding circuit 26 performs a complex Fourier operation with the system clock from the system clock generating circuit 24, and outputs the output signal of the guard interval period processing circuit 25 for each frequency. The signal levels of the real part and the imaginary part are calculated.

The real part for each frequency obtained by this,
Each signal level of the imaginary part is compared with the demodulation output of the reference carrier wave by the QAM decoding circuit unit to obtain the level of the quantized digital signal transmitted by the carrier wave for digital information transmission, and the digital information is obtained. Be decrypted. The decoded digital information signal is subjected to output processing such as parallel-serial conversion by the output circuit 27 and output to the output terminal 28.

Next, the frequency division multiplex signal generator of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of a frequency division multiplex signal generator according to the present invention. This frequency division multiplex signal generator is a device that can be used as a circuit from the arithmetic unit 4 to the quadrature modulator 7 in FIG.
IFFT circuit 33 and second IFFT circuit 34, sample synchronization circuit 35, symbol synchronization circuit 36, four peak detection circuits 37 to 40, and data polarity determination circuit 4
1, four polarity control circuits 42 to 45, and an adder circuit 46
And a quadrature modulator 47.

The digital data input via the input terminal 31 is a 256-byte signal to be transmitted in one symbol period, of which the real part data is input to the IFFT circuit 33 via the terminal 31 and the imaginary part. Data is input to the IFFT circuit 33 via the terminal 32. IFF
The T circuit 33 performs an IFFT operation after dividing the input data into four digital signals (real number part data and imaginary number part data) every 64 bytes.

That is, the IFFT circuit 33 has four IFs.
It has an FT calculation unit, and the input real number part data and the input imaginary number part data are each divided into four, and the IFFT calculation unit performs the IFFT calculation. Here, assuming that the data series N is 256 in each of the four IFFT operation units, each of the real number part and the imaginary number part has a total of 256 input terminals. 4-bit digital data is input to each input terminal.

Here, each of the above-mentioned four IFFT calculation units is a first IFFT calculation unit which outputs a carrier frequency of ± 4m (m is an integer of 0 to 31), and ± 4m + 1 (m).
Is an integer from 0 to 31) The second that outputs the th carrier frequency
IFFT calculation unit, which outputs the ± 4m + 2 (m is an integer of 0 to 31) th carrier frequency, and the third IFFT calculation unit which outputs ± 4m + 3 (m is an integer of 0 to 31) th carrier frequency It is composed of a fourth IFFT operation unit.

Further, in order to set a carrier hole of a predetermined specific carrier frequency, the IFFT circuit 33 sets the voltage to the input terminal of each corresponding IFFT calculation unit to zero. That is, the OFDM signal is IFFT
When the input terminal voltage of the circuit is set to 0, the level of the carrier wave corresponding to it becomes 0. This is called a carrier hole, and this property is used when sharing the transmission band with other transmission methods. For example, when transmitting an OFDM signal in a transmission band overlapping with the NTSC system, the center carrier frequency part of an NTSC system television signal and a carrier in a band for transmitting a color signal are set to 0.

In this embodiment, as will be described later, polarity information indicating polarity switching is transmitted at a specific carrier frequency. Here, since there are four systems of polarity control circuits 42 to 45, a predetermined number of carrier waves corresponding to the four polarity control circuits 42 to 45 are arranged. That is, the polarity information is transmitted for each system by four carrier waves or two by two carrier waves.
Transmits polarity information for each system, or 1 by 16QAM
The carrier wave of a book is used to transmit 4-bit polarity information.
The voltage of the input terminal for the corresponding frequency is kept at 0 in advance so that no output signal is generated from the IFFT circuit 33 at the position of the frequency corresponding to this specific carrier wave. In this way, the level of the specific carrier in the frequency band between the highest frequency and the lowest frequency of the plurality of carriers transmitting the digital information signal is set to zero.

In this way, the IFFT circuit 33 outputs the OFD.
The carrier wave frequency forming the M signal is divided into four in a comb shape and output. Since the four IFFT operation units in the IFFT circuit 33 each perform an operation on 64 carrier waves, the peak power value with respect to the average power value is 25 as a matter of course.
This is a value that is 1/4 times the value when the calculation is performed on six carrier waves.

These output signals are added as they are, and OF
When a DM signal is generated, the problem of peak power, which has been a conventional problem, remains. Since the amplitude and phase of each carrier wave forming the OFDM signal is determined by the modulation signal, when the input signal has little correlation, the output signal also becomes a set of random carrier wave signals.

As described above, the average power obtained by combining carrier signals of random 256 waves is 2 times the power of one carrier wave.
56 times higher. If the instantaneous peak positions of all the carriers match, the power value becomes 65536 times 256 squared. Actually, the probability that the peak values of the 256 carrier waves match is very small, and it cannot be said that this will happen. It is said that the peak value of power that can normally occur is 10 to 20 times the average power. That is, when the average transmission power of the OFDM signal is set to 10 W, the power amplifier of the transmission unit 11 has 10
The ability to transmit power of 0 W to 200 W without distortion is required (the theoretical maximum power at this time is 2560).
W).

Therefore, in the present embodiment, the average power is increased and the C / N at the receiving point is improved by suppressing such instantaneous power to be low. That is, IF
The signals of the carrier frequency band divided into four obtained from the FT circuit 33 are provided in the polarity control circuits 4 corresponding to each other.
2 to 45 are separately supplied to the data polarity determination circuit 41.

The data polarity determination circuit 41 determines, on the basis of the input peak detection data, the maximum instantaneous power value of the signal in the four divided frequency bands, its polarity, and the generation time position at which position in the IFFT operation occurs. Find the polar combinations that reduce the peak power value (there are 16 total combinations),
Based on the obtained determination result, the polarity control circuits 42, 43,
While controlling 44 and 45, the polarity information indicating the combination of polarities is supplied to the second IFFT circuit 34.

The polarity control circuits 42 to 45 are normally IFF.
The polarity is controlled so that the output signal of the T circuit 33 is output to the adding circuit 46 in the same phase, but when the corresponding peak detection circuits 37 to 40 detect the peak power (peak voltage) or more. Sets the polarities of the frequency division multiplexed signals of the other groups from the IFFT circuit 33 in the direction of canceling the peak power of a predetermined value or more and supplies them to the adder circuit 46. Therefore, for example, the peak detection circuit 37
When the peak power of a predetermined value or more is detected by the first group of frequency division multiplexed signals, the polarity control circuit 4
Any one or two or more of the polarity control circuits 43 to 45 other than 2 controls the polarities of the frequency division multiplexed signals of the second to fourth groups at the same peak position in the direction of canceling the detected peak power. The Rukoto.

Here, it is necessary to obtain correct data for the frequency division multiplexed signal whose polarity has been switched by switching the polarity after FFT calculation in the decoding device. Therefore, when switching the polarities in the frequency division multiplex signal generator, it is necessary to transmit to the decoding device information about which carrier has the polarities switched. Therefore, in this embodiment,
The combination of polarity switching is limited to a pattern of an appropriate kind such as a predetermined group, so that it can be reliably transmitted to the frequency division multiplex signal reception device with a small amount of information, and decoding can be performed by the decoding device in the reception device in a short time. To do.

That is, the IFFT circuit 34 of FIG. 1 performs an IFFT operation on the polarity control information input from the data polarity determination circuit 41, and obtains the operation result transmitted by the carrier wave corresponding to the carrier wave frequency of the carrier hole. Output. At this time, the IFFT circuit 34 changes the IFFT circuit 33.
The same sample pulse from the sample synchronization circuit 36 and the symbol signal from the symbol synchronization circuit 37 are supplied, and thereby the operation result is output in synchronization with the IFFT circuit 33.

Here, the effective symbol period of IFFT for generating a carrier wave of 257 waves within 99 kHz is about 2.6 m.
sec (= 256 / 99,000), but the above IF
The time required for the IFFT operation by the FT circuit 33 is about 2 m
It takes about 0.5 sec, and the time required for peak detection, polarity determination, and IFFT calculation by the IFFT circuit 34 is 0.5 msec.
Because the following can be done, the IFF from this IFFT circuit 34
The T calculation result is supplied to the adder circuit 46, and is embedded in the carrier hole within the same symbol period as the polarity determined data.

That is, the purpose of the IFFT circuit 34 is to generate the polarity control information to be embedded in the carrier hole in a short time after that, because the polarity control information is obtained after the calculation by the IFFT circuit 33.

As a result, the peak power is suppressed to a predetermined value or less from the adder circuit 46 for adding the output signals of the polarity control circuits 42 to 45 and the calculation result of the IFFT circuit 34, and the polarity information is modulated to the above value. An OFDM signal composed of a total of 256 carriers embedded in the carrier holes is output. The output signal of the adder circuit 46 is intermittently input to an output buffer (not shown), continuously read, and further supplied to a quadrature modulator 47 through a predetermined circuit to be quadrature-modulated.

By the way, as described above, the IFFT circuit 33
And the output signals of 34 are added by the addition circuit 4 within the same symbol period.
Since it is added in 6 and sent out, the operation of the IFFT circuit 34 is required to be performed in a short time. In the case of FIG. 1, the combination of the polarity information is actually 16 raised to the fourth power, so the IFFT circuit 34 stores the 16 calculated output signal waveforms in advance in a read-only memory (ROM) as a table. If a table of required combination information is designated and output, the actual calculation time can be regarded as zero.

When the output signal is periodic, the output signal can be generated from limited signal data such as one cycle or only the positive portion of the signal or only the information in the first quadrant. When the phases of the output signals are different, the timing of reading can be devised and output. Further, when similar signal outputs having different amplitudes are generated, it is possible to output the signal through a fixed level attenuator so that the read signal output has a predetermined level.

What is essential is that the same time-controlled output signal as that of the IFFT circuit 33 is generated from the IFFT circuit 34, which is a signal of the IFFT circuit 34 that is orthogonal to the OFDM signal of the IFFT circuit 33. It must be separated and properly separated at the receiving end.

Next, each embodiment of the decoding device of the present invention will be described. FIG. 2 shows a block diagram of a first embodiment of a decoding device according to the present invention. As shown in the figure, this decoding device includes a quadrature demodulator 51, two FFT circuits 52.
And 53, and four polarity correction circuits 54 to 57. The quadrature demodulator 51 corresponds to the circuit portion including the quadrature demodulator 16 and the intermediate frequency oscillator 18 and the 90 ° shifter 19 in FIG. 4, and the other circuit portions correspond to the FFT and QAM decoding circuit 26, and the LPF 21 in FIG. , A / D converter 2
2. The guard interval period processing circuit 25 and the like are not shown because they are not directly related to the present invention.

In FIG. 2, the transmitted OFDM signal is quadrature demodulated by the quadrature demodulator 51 and decoded into an in-phase signal (I signal) and a quadrature signal (Q signal), and then FF.
The information is supplied to the T circuits 52 and 53, respectively, and subjected to fast Fourier transform (FFT) to decode the information of each carrier. Here, from the FFT circuit 52, the decoded transmission data for each carrier group divided into four is extracted,
The corresponding polarity correction circuits 54, 55, 56 and 5 respectively.
7 is supplied.

On the other hand, from the FFT circuit 53, the decoded polarity information is taken out from a predetermined output terminal from which the decoded output of the polarity information transmitted by the specific carrier is obtained and supplied to the polarity correction circuits 54, 55, 56 and 57. To be done. The polarity correction circuits 54, 55, 56 and 57 correct the polarity of the decoded transmission data from the FFT circuit 52 to the original polarity based on the above-mentioned decoding polarity information and output it. That is, since the OFDM signal in the band in which the polarity is inverted and transmitted produces a demodulation output in which the polarity is inverted, the OFDM signal is converted into a signal of each correct polarity to obtain a normal digital demodulation signal output.

By the way, the FFT circuit 53 is operated by the FFT.
The same FFT calculation as that of the circuit 52 is performed, and these FFT circuits can be collectively configured by one. FIG. 3 shows a block diagram of a second embodiment of the decoding apparatus of the present invention in this case. In the figure, the same components as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 3, the FFT circuit 61 is the FF.
An FFT circuit in which the T circuits 52 and 53 are combined, and the decoded data is output to the corresponding polarity correction circuits 54, 55, 56 and 57 from the respective output terminals from which the decoded transmission data for each carrier group divided into four are obtained. Then, the polarity correction circuits 54 and 5 convert the decoded polarity information from a predetermined output terminal from which a decoded output of the polarity information transmitted by the specific carrier is obtained.
5, 56 and 57.

Next, the polarity of the IFFT signal output is inverted and Q
The relationship of the AM-modulated signal point arrangement will be described. When receiving an OFDM signal, the signal point arrangement may shift due to the influence of noise or the like, resulting in a bit error. Therefore, in order to suppress this bit error to a minimum, the data for the signal point is defined by the Gray code. For example, as the data values for the one-dimensional signal points from the signal point level “+8” to “−8”, “0100” when the signal point level is “+8” and “0101” when the signal point level is “+7”. , ”
When it is +6 ”, it is“ 0111 ”, and when it is“ +5 ”, it is“ 01
10 "," +4 "is" 0010 "," +3 "is" 0011 ", and" +2 "is" 0001 ","
"0000" when +1 "," 10 "when" -1 "
00 "," -2 "is" 1001 "," -3 "is" 1011 "," -4 "is" 1010 ","
When it is -5 ", it is" 1110 ", when it is" -6 ", it is" 11 ".
11 "and" -7 "are" 1101 ", and" -8 "are" 1100 ".

In this case, since the most significant bit (MSB) value is only inverted in the digital data in which the signal points are inverted, the digital data only needs to be inverted in the MSB bit. Therefore, the polarity correction circuits 54 to 57 have a digital data value in which the signal point arrangement of 256QAM is defined as a signal point symmetric with respect to the origin as a conversion table, and the conversion table is referred to by the polarity information to obtain the digital data. The polarity of is converted.

When the definition of the data for the signal points is made in another form, the polarities can be converted by using the conversion table.

The present invention is not limited to the above embodiment, and the number of divisions may be plural. Also,
Although the output of the IFFT circuit 33 has a real number part and an imaginary number part, the polarity switching circuit according to the present invention may be inserted into these output circuits individually and switched, or may be switched simultaneously. When individually switching so as to cancel the peak power, the peak power suppression control can be performed more finely, but the combination information of the polarities increases accordingly. In this case, it goes without saying that the demodulation circuit also has a structure corresponding thereto.

[0070]

As described above, according to the present invention,
By dividing the frequency-division-multiplexed signal including a plurality of carriers into n groups and separately generating the frequency-division-multiplexed signals, the peak power of the signal can be reduced as compared with the case where the frequency-division-multiplexed signal including the desired number of carriers is generated by a single arithmetic circuit. It can be suppressed to 1 / n, and when the frequency division multiplex signal of one group among the n groups of frequency division multiplex signals has a peak power of a predetermined value or more, the other group at the peak power generation position. By controlling the polarity of the frequency-division multiplexed signal, the instantaneous power of the output frequency-division multiplexed signal can be further suppressed to a low value. Therefore, the margin of the power amplifier can be reduced, and the size and weight of the transmitter can be reduced, including the power supply of the transmitter. It can be.

Further, according to the present invention, the peak power value of the frequency division multiplexed signal composed of a large number of synthesized information carriers can be suppressed to a small value. The average transmission power can be set large, the carrier power to noise power ratio (C / N) at the receiving point can be improved, and the communication quality at a weak electric field position with a smaller error rate can be improved. it can.

Further, in the present invention, since the polarity control information is transmitted within the same transmission band, the transmission frequency for the polarity control information is not required, and the utilization rate of the frequency band is OF.
The characteristics of the DM signal are not impaired.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a frequency division multiplex signal generator of the present invention.

FIG. 2 is a block diagram of a first embodiment of a decoding device of the present invention.

FIG. 3 is a block diagram of a second embodiment of a decoding device of the present invention.

FIG. 4 is a block diagram showing a configuration of an example of an OFDM signal transmission / reception system to which the present invention is applied.

FIG. 5 is a diagram showing a frequency spectrum of an OFDM signal.

[Explanation of symbols]

2 Input Circuit 3 Clock Divider 4 Arithmetic Device 7, 47 Quadrature Modulator 8, 18 Intermediate Frequency Oscillator 9, 1990 90 ° Shifter 31, 32 Digital Data Input Terminal 33 First IFFT (Inverse Fast Fourier Transform) Circuit (No. 1) 1 arithmetic circuit) 34 2nd IFFT (Inverse Fast Fourier Transform) circuit (2nd arithmetic circuit) 35 Sample synchronization circuit 36 Symbol synchronization circuit 37-40 Peak detection circuit 41 Data polarity determination circuit (polarity control means) 42- 45 polarity control circuit (polarity control means) 46 adder circuit 51 quadrature demodulator 52, 53, 61 FFT (fast Fourier transform) circuit (decoding arithmetic circuit) 54 to 57 polarity correction circuit

Claims (6)

[Claims] 1. A first arithmetic circuit for individually modulating each of a plurality of divided digital information signals to generate a plurality of groups of frequency division multiplexed signals, and an output frequency division multiplexing of the first arithmetic circuit. A plurality of peak detection circuits for detecting the peak power and the peak position of a signal for each group, and a peak power of a predetermined value or more is detected based on a detection signal from a corresponding peak detection circuit among the plurality of peak detection circuits. In this case, the polarity of the frequency division multiplexed signals of the other group from the first arithmetic circuit is set in a direction in which the peak power of the predetermined value or more is canceled, and polarity control means for generating polarity information, The polarity information set by the polarity control means is modulated to be included in the frequency band between the highest frequency and the lowest frequency of the frequency division multiplexed signal, and A second arithmetic circuit that generates a signal different from the frequency division multiplex signal, an output frequency division multiplex signal of the first arithmetic circuit whose polarity is controlled by the polarity control means, and an output of the second arithmetic circuit. A frequency division multiplex signal generator having an adder circuit for adding and synthesizing signals and outputting the result. 2. The first arithmetic circuit sets a carrier hole within a frequency band between the highest frequency and the lowest frequency of the frequency division multiplexed signal, and the second arithmetic circuit sets the frequency of the carrier hole. 2. The frequency division multiplex signal generator according to claim 1, wherein a carrier wave modulated with the polarity information is generated at a position. 3. The second arithmetic circuit generates a carrier wave modulated by the polarity information in synchronization with the output signal of the first arithmetic circuit, and is the same as the output frequency division multiplexed signal of the first arithmetic circuit. 3. The frequency division multiplex signal generator according to claim 2, wherein the frequency division multiplex signal generator outputs the signal at a timing. 4. The first arithmetic circuit separately frequency-division-multiplexes a plurality of groups by performing an inverse discrete Fourier transform on each of the plurality of divided digital information signals transmitted on a symbol basis within a symbol period. Generating a signal, and the second arithmetic circuit inversely discrete Fourier transforms the polarity information within the same symbol period as the frequency division multiplexed signals of the plurality of groups to generate a modulated carrier. The frequency division multiplex signal generator according to any one of claims 1 to 3. 5. A frequency division multiplexed signal composed of a plurality of first carrier waves modulated by a digital information signal, divided into a plurality of groups, and a polarity indicating presence / absence of polarity inversion of these frequency divided multiplexed signals for each group. Decoding in which a composite signal that is modulated with information and that is frequency-divided with a second carrier that is a frequency between the highest frequency and the lowest frequency of the plurality of first carriers is input, and is subjected to Fourier transform operation and decoding For the decoding operation circuit and the decoded signal output in parallel for each of the plurality of groups decoded from the decoding operation circuit, the polarities are separately set based on the polarity information decoded from the decoding operation circuit. A decoding device having a plurality of polarity correction circuits for performing a polarity correction operation for returning to the original. 6. Each of the plurality of polarity correction circuits comprises:
The modulation information signal point arrangement for the first and second carrier waves is used as a conversion table having digital information signal values for defining signal points that are point-symmetric with respect to the origin, and the conversion table is obtained using the decoded polarity information. 6. The polarity conversion of the digital information signal is performed with reference to the digital information signal.
The described decoding device.