JPH08330919A - Delay generation circuit - Google Patents

Abstract

PURPOSE: To reduce the scale of a variable delay circuit by providing a rate switching circuit which extracts the pulses outputted from the variable delay circuit every time the count value of a counter is equal to the prescribed value. CONSTITUTION: A variable delay circuit 20 is placed at the preceding stage or a rate switching circuit 10. The circuit to outputs a coincidence detection signal of H logic through a coincidence detection circuit 14 every time the count value of a counter 12 is equal to the value that is set at a dividing number setter 13. Then the circuit 10 controls the opening of an AND gate 15 by the H logic signal. In such an arrangement where the circuit 20 is placed before the circuit 10, the total amount of clock pulses CLK supplied to the circuit 20 are inputted to an active element string A that constructs the delay elements of the circuit 20. Therefore, the number of pulses inputted to the element string A is never changed despite the change of rate cycle of the circuit 10. Thus the stable timing signals are generated without variance in the delay time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay generation circuit which can be used in a test device for testing a memory composed of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a device for testing a memory, it is necessary to generate timing signals having different delay times from the reference clock cycle (test cycle cycle) and the phase of the reference clock. FIG. 3 shows an example of a conventional timing signal generating circuit. In the figure, 10 is a rate switching circuit for switching the test cycle, and 20 is a variable delay circuit. Rate switching circuit 10
Is generally called a variable frequency divider, and performs an operation of dividing a clock input from the input terminal 11 by an arbitrary frequency division ratio and taking it out.

That is, the clock CLK (FIG. 4A) input to the input terminal 11 is input to the counter 12, and the number of clocks input to the counter 12 is counted. Counter 1
The count output of 2 is input to the coincidence detection circuit 14, and compared with the division number set in the division number setting unit 13 in the coincidence detection circuit 14, and the division number set in the division number setting unit 13 and the counter 12 are compared.
The coincidence detection circuit 14 outputs a detection signal of, for example, an H logic every time the count value of 1 is coincident with, and the AND gate 15 is controlled to open by this detection signal, and one clock CLK is taken out from the AND gate 15. Pulse C extracted in this way
P (FIG. 4B) is a cycle obtained by dividing the clock CLK according to the frequency division number set in the frequency division number setting unit 13, and defines the test cycle T. The counter is reset by the pulse CP extracted from the AND gate 15.

The pulse CP extracted from the rate switching circuit 10 is delayed by the variable delay circuit 20 within an interval of the clock CLK and extracted for an arbitrary time. (Note that the delay time in units of the cycle of the clock pulse CLK is given by another delay circuit such as a frequency divider) Variable delay circuit 2
0 uses an active element array A generally formed in a CMOS type IC as a delay element. In the example shown in the figure, the buffer amplifiers are connected in cascade, and the pulse CP
FIG. 4C shows a case in which the delay pulse CCP (FIG. 4C) to which an arbitrary delay time τ is given is taken out. The AND gate group G constitutes a switching circuit for controlling from which stage of the active element array A the pulse CP is taken out. J indicates a control circuit that determines which AND gate in the AND gate group G is controlled to be opened. The delayed pulse CCP extracted by the AND gate group G is the OR gate OR
Pulse C taken out through and input to the output terminal 21
Pulse CCP delayed by an arbitrary time τ from the phase of P
Is taken out.

Conventionally, an active element array A formed in a CMOS type IC is used as a delay element. CMOS type I
The reason why C is used is that the CMOS type IC consumes a very small amount of power in a stationary state (no signal state), and thus generates a small amount of heat in the circuit. The CMOS type IC certainly consumes less power in a stationary state. However, when a signal is given and the on / off operation is repeated, power is consumed. Therefore, when the number of pulses CP supplied changes, the power consumption also changes. When the power consumption changes, the temperature of the circuit board also changes, and this temperature change causes a disadvantage that the delay time τ of the active element array A changes. That is, in the rate switching circuit 10, if the frequency division number is changed and the period T of the pulse CP is changed, there is a disadvantage that the delay time τ of the variable delay circuit 20 changes.

Therefore, conventionally, a dummy active element array AA is provided close to the active element array A used as a delay element,
A pulse train, for example, a clock CLK is applied to this dummy active element array AA, and every time a pulse CP is output from the rate switching circuit 10, a gate 22 provided at the entrance of the active element array AA is provided.
Is controlled to be closed, the clock CLK supplied to the dummy active element array AA is deleted by one, and the total number of pulses supplied to the entire CMOS IC is made constant, so that the temperature in the CMOS IC is Is maintained at a constant temperature.

[0007]

As described above, the CM
In order to maintain the temperature inside the OS type IC at a constant temperature, a dummy active element group AA is conventionally provided. Therefore, there is a disadvantage that the circuit scale of the variable delay circuit 20 becomes large. An object of the present invention is to provide a delay generation circuit that can reduce the circuit scale of a variable delay circuit.

[0008]

According to the present invention, a rate switching circuit is provided at the subsequent stage of a variable delay circuit, and a target delay time is given in advance to all clock pulses input to the variable delay circuit, and the delay time is delayed. The pulse train is configured to be divided into arbitrary cycles. Therefore, according to the configuration of the present invention, since the entire amount of the clock pulse that is always input is given to the active element array forming the delay circuit, it is not necessary to provide a dummy active element array in addition to this active element array. Therefore, the circuit scale of the variable delay circuit can be halved.

[0009]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, portions corresponding to those in FIG. 3 are designated by the same reference numerals. In the present invention, the variable delay circuit 20 is arranged before the rate switching circuit 10. That is, the clock pulse CLK is input to the input terminal 23 of the variable delay circuit 20, and the entire amount of the input clock pulse CLK is supplied to the active element array A of the variable delay circuit 20. A pulse CL delayed from an arbitrary stage of the active element array A by the gate group G
Take out KK (Fig. 2B). This delay pulse CLKK is taken out through the OR gate OR and input to the rate switching circuit 10.

In the rate switching circuit 10, each time the count value of the counter 12 reaches the numerical value set in the frequency division number setting unit 13,
The coincidence detection circuit 14 outputs an H logic coincidence detection signal, and the AND gate 15 is aperture controlled by the H logic signal. The AND gate 15 takes out the delay pulse output from the OR gate OR every three cycles of the clock pulse CLK in this example, and outputs the pulse CCP (FIG. 2C) which gives the test cycle T to the output terminal 16. The pulse CCP output to the output terminal 16 is delayed from the reference timing T ₀ (phase of the clock pulse CLK) by a time τ, and is defined as a rate cycle of a cycle T of 3 cycles in the example of the clock pulse CLK in the figure.

[0011]

As described above, according to the present invention, since the variable delay circuit 20 is provided in the preceding stage of the rate switching circuit 10, the total amount of the clock pulse CLK supplied to the variable delay circuit 20 is in the variable delay circuit 20. It is input to the active element array A that constitutes the delay element. Therefore, since the number of pulses input to the active element train A does not change even if the rate cycle T of the rate switching circuit 10 is changed, the temperature inside the CMOS type IC is maintained at a constant value, and thus the delay time changes. In fact, a stable timing signal can be generated.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of FIG.

FIG. 3 is a connection diagram for explaining a conventional technique.

FIG. 4 is a waveform diagram for explaining the operation of FIG.

[Explanation of symbols]

 10 rate switching circuit 12 counter 13 frequency division setting device 14 coincidence detection circuit 15 AND gate 16 output terminal 20 variable delay circuit 23 input terminal

Claims (1)

[Claims] 1. A. First Embodiment It is composed of CMOS type IC,
A variable delay circuit that gives a desired delay time to the pulse train, and B. And a rate switching circuit that counts the pulses output from the variable delay circuit with a counter and extracts the pulses output from the variable delay circuit each time the count value of the counter matches a predetermined value. Delay generation circuit.