JPH08329689A - Flash memory and its erasing method - Google Patents

Abstract

PURPOSE: To shorten the erase processing time for blocks including the one for a block to be erased which might occur additionally during the erase processing action. CONSTITUTION: Erase addition registers, Ra1 to Ra4, and erase permission registers, Rb1 to Rb4, which correspond to memory blocks, MB1 to MB4, respectively are provided. A command analyzer circuit 1 is provided which receives an erase block setting command to set an erase addition register which correspond to the erase block address and receives an erase command to output its control signal. A control circuit 2 is provided which receives the control signal to check the setting condition of the erase addition registers, Ra1 to Ra4, sets the erase permission registers which correspond to the set erase addition register to erase in a single unit of memory blocks corresponding to the set erase addition register and controls verify. Through the erase addition registers, Ra1 to Ra4, setting processing and packaged erase processing of erase blocks are parallelly conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory and an erasing method thereof, and more particularly to a flash memory having a plurality of memory blocks in a batch erasing unit and an erasing method thereof.

[0002]

2. Description of the Related Art When writing data to a flash memory, it is necessary to perform an erasing process before writing the data. This erasing process is performed for the entire chip of the flash memory or for each memory block. The method of batch erasing the entire chip is effective when renewing the data, but when rewriting part of the data, the area that does not need to be rewritten is also erased, so it is necessary to store the data again. The speed becomes slow. When erasing in memory block units, there is no need to erase and re-store areas that do not require rewriting, and therefore, the rewriting time can be shortened and the number of times of erasing can be reduced. In addition, when erasing a predetermined memory block of the plurality of memory blocks, a device is devised to simultaneously erase the plurality of selected memory blocks to be erased.

In the case of simultaneously erasing a plurality of selected memory blocks to be erased, a method of tagging the plurality of memory blocks is disclosed in JP-A-57-150178 and JP-A-2-292798. It is disclosed.

FIG. 6 is a block diagram of a flash memory (first example) summarized with reference to Japanese Patent Laid-Open No. 2-292798, which is a new technique among them.

In this flash memory, when a plurality of memory cells are arranged and the corresponding erase enable signals (EE1 to EE4) are at the activation level, the plurality of memory cells are collectively erased in accordance with the applied erase voltage pulse Ve and read. A plurality of memory cell blocks MB1 to MB4 in a batch erase unit for writing / reading data to / from a memory cell at an address (this addressing means is not shown) specified according to a write control signal (not shown), and a plurality of these memory cell blocks MB1 to MB4. Corresponding to the memory blocks MB1 to MB4, and the erase enable signals (EE1 to EE1) of the activation level in the set state.
A plurality of erase enable registers Rb1 to Rb4 for supplying EE4) to the corresponding memory block, the controller 31,
Serial interface 32, command register 33,
An erase block address AEB transmitted when the command CMD transmitted from the host system is an erase block setting command, including a command decoder 34, an address register 35, an address decoder 36 and a logic gate 37.
The erase enable registers (Rb1 to Rb4) corresponding to the above are set, the erase voltage pulse Ve is output according to the global erase command, and the erase corresponding to the memory block for which the verify of the erase state is determined to be good by the verifying means (not shown). The control unit 30 terminates the erase processing operation when the permission register is cleared and all the erase permission registers are cleared.

Next, the operation of this flash memory and the data erasing method will be described with reference to the flowchart shown in FIG.

The selection of the memory block to be erased and the erase processing operation are performed under the control of the controller 31. The command information from the controller 31 is transferred to the command register 3 via the serial interface 32.
3 and is decoded by the command decoder 34, the command decoder 34 outputs various control signals. Similarly, the address information is stored in the address register 35.
And is decoded by the address decoder 36.

When the erase block setting command is decoded by the control unit 30, the erase processing operation is started in step S51, and the address (erase block address) of the memory block to be erased is transmitted. The erase permission register (erase tag) corresponding to is set (steps S52 and S53). If there are other memory blocks to be erased, steps S51 and S52 are repeated, and if not, the process proceeds to the next step (S53). An erase enable signal of an activation level is output from the set erase enable register, and the memory block to be erased is selected.

Next, when the global erase command is decoded by the control unit 31, the erase operation is started (S5
5) The erase voltage pulse Ve is applied from the control unit 30 to the memory blocks MB1 to MB4 and corresponds to the set erase enable registers (for example, Rb1 and Rb3) (that is, to the activation level erase enable signals EE1 and EE3). The memory cells of the memory blocks (MB1, MB3) are simultaneously erased (S56).

Next, the control section 30 outputs a control signal for verifying the erased state to a verifying means (not shown), and the verifying means reads the data of the memory blocks (MB1, MB3) to be erased. Verify is performed (S57). And the verify result is good (O
K), the erase enable register corresponding to the memory block is cleared (S58 to S60), and the operation from step 56 is repeated for the memory block determined to have a bad verify result.

All the memory blocks (MB1 to MB1)
When MB4) is verified OK (erasure permission register is in a clear state), the global erase command is pulled up to end the erase processing operation (S61 to S63), and if at least one memory block is not verified OK, step S56.
The operation from is repeated. Here, verify OK
The reason why the erase enable register corresponding to the memory block is cleared is to protect the memory block from stress caused by application of an erase voltage pulse more than necessary.

By the way, in this flash memory, the erasing processing operation is roughly divided into an erasing block setting operation for setting a memory block to be erased and a batch erasing to the set memory block to be erased and its verification is performed. It consists of two operations, an erase operation and its verify operation. Prior to the erase operation and its verify operation, pre-program is performed to write predetermined data to all the memory cells of the memory block to be erased. A flash memory has also been proposed in which the memory contents of the respective memory cells are made the same and the variation in threshold voltage of the memory cells after the erase processing operation is suppressed.

An example of such a flash memory (second
8) is a block diagram of FIG.

Each of the memory arrays MA1 to MAn is
When a plurality of memory cells are arranged and in the activated state, the plurality of memory cells are collectively erased according to the erase voltage pulse Ve applied, and data is written to or read from the memory cell at the specified address.

The address buffer circuit 11 takes in and outputs an address signal AD from the outside. Similarly, the control signal buffer circuit 15 also takes in and outputs CMD such as external control signals and commands.

The control circuit 16x has a memory cell array MA.
1 to MAn corresponding to the erase permission registers Rb1
.About.Rbn (erase tag), receives an erase command from the outside, starts the erase command process, sets the erase enable register corresponding to the erase block address from the address buffer circuit 11, and sets the erase enable register. The block selection signal for selecting the corresponding memory array is output and the pre-program control signal and the pre-program verify control signal are sequentially output at a predetermined timing, and it is set when the pre-program verify control result is good. After the erase enable signals (EE1 to EEn) are output from the erase enable register and the erase voltage pulse Ve is output, the erase / verify control signal is output, and when the erase / verify determination result is good, the corresponding erase enable register is cleared. All erase enable registers Rb1 to Rbn To end the erase command processing to be cleared accepts the following command.

Address latch circuit 12x, X decoder D
The X, Y decoder 13 and the Y selector 14 activate a predetermined memory cell array of the plurality of memory arrays MA1 to MAn according to the address signal from the address buffer circuit 11, the block selection signal and the control signal from the control circuit 16x, It also specifies the addresses of these memory cell arrays.

The source line switches SS1 to SSn apply the erase voltage pulse Ve to the memory cell array corresponding to the erase enable signals (EE1 to EEn) of the activation level.

The input / output buffer circuit 17 takes in and outputs write data DI from the outside, and outputs the amplified read data to the outside.

The latch circuit 18 is provided in the input / output buffer circuit 1 in accordance with the preprogram control signal from the control circuit 16x.
The pre-programming data from 7 is latched and output, and the erase level data is latched and output according to the erase verify control signal.

The write circuit 19 transfers the data from the latch circuit 18 to the Y selector 14 according to the preprogram control signal.
Are supplied to the memory cell arrays MA1 to MAn via.

The sense amplifier 20 amplifies the read data of the memory cell arrays MA1 to MAn transmitted through the Y selector 14 according to the preprogram / verify control signal and the erase / verify control signal, and transmits the amplified data to the input / output buffer circuit 17. To do.

The comparator 21 compares the data from the latch circuit 18 with the data from the sense amplifier 20, and when they match, transmits a verify establishment signal of a good level to the control circuit 16x.

Next, the data erasing operation and the erasing method of this flash memory will be described with reference to the flow chart shown in FIG.

When the control circuit 16x receives the erase command (when the erase command is decoded), it starts the erase command processing (steps S71 and S72). First, the erase block address is input from the address buffer circuit 11 to erase the erase block. The erase enable register corresponding to the address is set (S73, S74). If there is another memory cell array to be erased, the process returns to step S73 and the same operation is repeated. If not (if all erase enable registers corresponding to the memory cell array to be erased are set), (Step S75).

Next, the memory cell arrays corresponding to the set erase enable registers are designated (selected) one by one, and predetermined data is written in all the memory cells to perform pre-programming, and the state of this pre-programming is verified. Do (S
76, S77). This pre-programming and verification are continued until verification is OK (S78, S7).
7). When all the memory cell arrays corresponding to the set erase enable register have been verified OK and pre-programming is completed (S79), the process proceeds to the next step S80.

In step S80, the source line switches (SS1 to SSn) are supplied to all the memory cell arrays corresponding to the set erase enable register, that is, all the memory cell arrays corresponding to the erase level enable signals (EE1 to EEn) at the activation level. An erasing voltage pulse Ve is applied to erase the memory cells of these memory cell arrays at once. Then, in step S81, the erase state is verified by designating the memory cell arrays corresponding to the set erase permission registers one by one, and if the verification is OK, the corresponding erase permission register is cleared (S82, S8).
3) Then, it is confirmed whether or not the verification of all the memory cell arrays corresponding to the set erase enable register is completed (S84). If the verification is not OK, it is confirmed whether all the verifications have been completed without clearing the erase enable register.

If all the verifications have not been completed in step S84, the process returns to step S81 and the operation from this step is repeated. If all the verifications have been completed, has all erase enable registers been cleared? It is confirmed (S85), and if all are cleared, the erase command processing is terminated and the next command is waited (S86).
If there is something that has not been cleared, it means that it is not in the erased state, and the process returns to step S80 and the operation from this step is repeated.

The description of these flash memories mainly relates to the erasing process, but it goes without saying that these flash memories have the functions of normal data writing and reading.

In the above-described flash memory erasing method, since a large number of memory cells can be erased at one time because the erase operation is performed in block units, the erase voltage pulse is applied for a certain period and the erase state is confirmed ( The erase process is performed by repeating (verify),
It takes a very long time as compared with the read and write cycles of general microprocessors. In particular, these flash memories and their erasing methods cannot add new erase blocks until the erase processing operation by one erase command is completed.

For this reason, various measures have been conventionally made. For example, referring to Japanese Unexamined Patent Application Publication No. 5-54682, by providing a read X decoder for each block, the read operation can be performed in parallel for blocks other than the erase block. According to the Intel 28F016SA user's manual, when a specific command is accepted during the execution of the erase operation, the erase processing operation is suspended and the blocks other than the block in which the erase processing is being executed are read / written, and then the erase processing is performed. It has the function of restarting the erase processing operation by the command for operation restart. Further, according to the user's manual of 28F016SA, it has a command queue and has a function of accepting the next command during the erase processing operation.

However, even with these flash memories,
It is not possible to add a block to be newly erased in addition to the block in which the erase processing operation is being executed, and the erase processing of a new erase block must be executed unless the erase processing of the block in the erase processing operation is completed. I can't.

[0033]

In the above-described conventional flash memory and its erasing method, even if a block to be erased is newly generated in addition to the block in which one erase processing operation is being executed, this block is still being executed. Cannot be added to the erase processing operation of, and the erase processing of a new block cannot be executed until the erase processing operation in progress is completed.
There is a problem that the erase processing time including a new block becomes long.

An object of the present invention is to provide a flash memory and an erasing method thereof which can shorten the erasing processing time including the new block when a new block to be erased occurs during execution of the erasing processing operation. To do.

[0035]

In a first flash memory of the present invention, a plurality of memory cells are arranged and the plurality of memory cells are arranged in accordance with an erase voltage pulse applied when a corresponding erase enable signal is at an activation level. A plurality of memory blocks in a batch erase unit for performing batch erase and writing / reading data to / from a memory cell at an address specified according to a read / write control signal, and a plurality of erases provided corresponding to each of the plurality of memory blocks An additional register and an erase enable register, and a command analysis unit that sets the erase additional register corresponding to the erase block address transmitted when the transmitted command is an erase block setting command and outputs an erase command processing signal when the erase command is an erase command. Receiving the erase command processing signal, the plurality of erase additional registers If there is any one in the set state, the erase enable register corresponding to the erase add register in the set state is set to output the erase enable signal at the activation level and the erase add register is cleared to When the erase enable register has a set state, the erase voltage pulse is applied to the plurality of memory blocks, and then the read / write control signal is output to verify-control the erase state of the collectively erased memory blocks. And a control unit that clears the erase enable register corresponding to this memory block when the result of this verification is determined to be good.

A first flash memory erasing method of the present invention comprises a plurality of memory blocks in a batch erasing unit and a plurality of erasing addition registers and erasing permission registers provided corresponding to the plurality of memory blocks, respectively. A method of erasing a flash memory, comprising: a first step of setting the erase additional register corresponding to an erase block address transmitted when the transmitted command is an erase block setting command; At the time of a command, if there is a set state among the plurality of erase addition registers, the erase enable register corresponding to the set erase addition register is set and the erase addition register is cleared to set the erase addition register. If there is not, the second procedure to proceed directly to the next procedure and If one of the memory cells is in the set state, an erase voltage pulse is supplied to the plurality of memory blocks to collectively erase the memory blocks corresponding to the erased additional registers in the set state. And a fourth procedure for verifying the erased state of the memory blocks collectively erased by the third procedure, and a memory block for which the result of the verification by the fourth procedure is determined to be good. And a fifth step of returning to the second step when it is not determined that the erasure permission register corresponding to is cleared.

According to the second flash memory of the present invention, when a plurality of memory cells are arranged and in an activated state, the plurality of memory cells are collectively erased in accordance with the applied erase voltage pulse to become a memory cell of a designated address. A plurality of memory blocks in a batch erase unit for writing and reading data, and a plurality of erase additional registers and valid flags corresponding to each of these memory blocks are provided, and an erase command is accepted to clear the plurality of valid flags. If so, the erase addition register corresponding to the transmitted erase block address is set, the memory blocks corresponding to the erase addition register in the set state are sequentially activated one by one, and the pre-program control signal is sequentially output to verify-verify. Set by setting the valid flag corresponding to the judgment level that the signal is good A first control unit that completes the processing of the erase command and becomes ready to receive the next erase command when all the valid flags corresponding to the erase addition register of the state are set, and according to the preprogram control signal. When a pre-program is executed to write data of a predetermined level to all the memory cells of the activated memory block and the pre-program state is verified according to a verify control signal and the result is judged to be good. If there is a set state among the plurality of valid flags, the pre-program / verify unit that outputs the verify determination signal of the determination level and a plurality of erase enable registers corresponding to each of the plurality of memory blocks are provided. Set the valid flag in the set state and the corresponding erase enable register to enable this Lag and corresponding erase addition register are cleared, the erase enable register in this set state and the corresponding memory block are activated, the erase voltage pulse is applied, the erase verify control signal is output, and the erase verify determination signal is determined to be good. A second control unit that clears the erase enable register corresponding to the level, and the erase state of the activated memory block is verified according to the erase verify control signal, and when the result is determined to be good, the result is determined to be good. And an erase verify unit that outputs the erase verify determination signal of the level.

A second flash memory erasing method of the present invention comprises a plurality of memory blocks in a batch erasing unit and a plurality of erasing addition registers, a valid flag and an erasing permission register corresponding to each of the plurality of memory blocks. A method of erasing a flash memory, comprising: a first step of receiving an erase command and setting the erase addition register corresponding to the transmitted erase block address if the valid flags are in a clear state; A second procedure for activating the memory blocks corresponding to the erase additional registers one by one to perform pre-programming and its verification, and if the result of the verification by the second procedure is good, set the corresponding valid flag. All valid flags corresponding to the additional registers in the set state have been set When the processing of the erase command is completed, the next erase command is accepted, and the verification result is good, the third procedure of returning to the second procedure and the setting of the valid state of the plurality of valid flags are performed. If there is one, the valid flag in the set state and the corresponding erase enable register corresponding to the set flag are set, and the valid flag and the corresponding erase addition register are cleared. If there is no set state, the process proceeds to the next step as it is. And a fifth step of activating the memory block corresponding to the erase enable register in the set state and applying an erase voltage pulse to erase the memory block at once, and the memory block corresponding to the erase enable register in the set state Verify the erased state by specifying each one and if the result is good, clear the corresponding erase enable register and if not, The sixth step to proceed to the next step, and if the erase verify results of all the memory blocks corresponding to the set erase enable register are good, return to the fourth step and if there are some bad, the fifth step And a seventh procedure for returning to the procedure.

[0039]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the first flash memory of the present invention.

In this flash memory, a plurality of memory cells are arranged and the plurality of memory cells are collectively erased in accordance with the erase voltage pulse Ve applied when the corresponding erase enable signals (EE1 to EE4) are at the activation level, and read / write. Writing data to a memory cell at an address (address designation means not shown) designated according to the control signal RW,
Multiple memory blocks MB in batch erase unit for reading
1 to MB4 and the plurality of memory blocks MB1 to M
A plurality of erase enable registers Ra1 to Ra4 (erase add tags) provided corresponding to B4 respectively and a plurality of erase enable registers Rb1 to Rb4 (erase output) which respectively output the erase enable signals EE1 to EE4 of the activation level in the set state. Tag) and the transmitted command CMD is an erase block setting command, an erase additional register (Ra1 to Ra4) corresponding to the transmitted erase block address AEB.
Is set and an erase command processing signal is output when the erase command is issued, and an erase command register 1 receives the erase command signal from the command analysis circuit 1 and an erase additional register R
If any of a1 to Ra4 is in the set state, the erase addition register in the set state (for example, Ra1 and Ra3)
The erasure enable registers (Rb1, Rb3) corresponding to are set to clear the erasure addition registers (Ra1, Ra3), and if any of the erasure enable registers Rb1 to Rb4 is in the set state (Rb1, Rb3). ) After applying the erase voltage pulse Ve to the plurality of memory blocks MB1 to MB4, the read / write control signal RW is output to verify the erase state of the memory blocks (MB1, MB3) that are collectively erased. When VR is a good judgment level, the corresponding erase enable register (Rb
1, Rb3) are cleared, and a verify unit 3 that verifies the memory blocks collectively erased according to the read / write control signal RW and outputs a verify result signal VR.

Next, the operation and erasing method of this flash memory will be described with reference to the flow chart shown in FIG.

Command C sent from the host system
The MD is decoded by the command analysis circuit 1 (step S
1) If the command is an erase block setting command, setting of a block to be erased (erasure target block, hereinafter simply referred to as erase block) is started (S2). Then, the command analysis circuit 1 inputs the sent erase block address AEB (S3), and adds the erase block address AEB to the erase addition register (for example, Ra).
1, Ra3) is set (S4). This completes the setting of the erase block (S5). If other blocks are to be erased, the operation from step S1 is repeated according to the erase block setting command sent.

On the other hand, if the command CMD sent is an erase command (S6), the command analysis circuit 1 transmits an erase command processing signal to the control circuit 2 and the erase command processing is performed under the control of the control circuit 2. Is started (S7).

The control circuit 2 firstly, the erase addition register R
It is checked whether or not there is a set state among a1 to Ra4 (S8), and if there is a set state, the erase addition registers (Ra1, Ra3) in the set state and the corresponding erase permission registers (Rb1, Rb3). ) Is set to clear the erase addition registers (Ra1, Ra3) (S9). If not, proceed directly to the next step.

Then, the control circuit 2 checks whether or not there is a set state among the erase permission registers Rb1 to Rb4 (S10), and if there is a set state, erases the memory blocks MB1 to MB4. Voltage pulse V
is supplied to the erase enable register (Rb1,
Rb3), that is, an activation level erase enable signal (EE
1, EE3) and the corresponding memory block (MB1, MB
An erase voltage pulse Ve is applied to 3) to erase these memory blocks collectively (S11), and then the erase state is verified (S12).

Then, it is checked whether or not there is a memory block whose erase state verification is OK (S1
3) If there is a memory block for which verification is OK, the erase permission register corresponding to this memory block is cleared (S14), and the process returns to step S7 to repeat the above-mentioned operation. If there is no verify-OK memory block, the process returns to step S7.

In step S10, if there is no erase enable register that has been set (if there is no such erase register), there is no need to perform erase processing, so the erase command processing ends.

Here, the command analysis circuit 1 accepts and decodes the erase block setting command and the erase command at any time regardless of the operation of the control circuit 2, and if the erase block setting command is the erase block address, the erase corresponding to the erase block address. The additional register is set, and if it is an erase command, an erase command processing signal is output to the control circuit 2. On the other hand, when the control circuit 2 receives one erase command processing signal, the control circuit 2 repeats a series of erase processing operations starting from the check of the set state of the erase additional registers Ra1 to Ra4 (S8), and the erase enable register in the set state disappears. If so, the erase command processing ends.

Therefore, even while the erase command processing operation performed under the control of the control circuit 2 is being executed, the erase block setting operation by the command analysis circuit 1 is performed in parallel with this, and the erase additional register is set. When set, the erase enable register corresponding to the set erase addition register is newly set, and the memory block to be erased is added to the erase command process being executed.

Therefore, when a memory block to be erased is newly added as in the conventional example, the erase block for the newly added memory block is deleted after the erase process of the memory block being executed is completed. Setting process,
Since it is not necessary to repeat the operation of restarting the erase processing operation, the erase processing time can be shortened accordingly, and the entire erase processing time for these memory blocks can be shortened.

FIG. 3 is a block diagram showing an embodiment of the second flash memory of the present invention.

The flash memory of this embodiment is different from the conventional flash memory shown in FIG. 8 in that instead of the X decoder DX, X decoders DX1 to DXn corresponding to the memory blocks MA1 to MAn are also provided and controlled. Instead of the circuit 16x, a plurality of erase additional registers Ra1 to Ra corresponding to the memory cell arrays MA1 to MAn, respectively.
n and valid flags F1 to Fn, the erase command is received, and if the valid flags F1 to Fn are in the clear state, the erase additional register corresponding to the transmitted erase block address is set to correspond to the erase additional register in this set state. The memory cell arrays are sequentially activated one by one, and the pre-program control signal and the verify control signal are sequentially output, and the valid flag corresponding to the verify level of the verify determination signal is set to correspond to the erase addition register in the set state. When all the valid flags to be set are in the set state, the first control circuit 16a which finishes the erase command processing and enters the next erase command acceptance state is provided, and the input / output buffer circuit 17 and the latch circuit 18 corresponding to FIG. , The write circuit 19a, the sense amplifier 20a, and the comparator 21a are controlled by the control circuit 16a. Based on the above, a circuit for supplying a verify determination signal to the control circuit 16a by writing predetermined data to the memory cell array corresponding to the erase addition register in the set state and performing pre-programming is performed. Erasing enable registers Rb1 to Rbn corresponding to the cell arrays MA1 to MAn are provided, and if any of the valid flags F1 to Fn is in the set state, the valid flag in the set state and the corresponding erase enable register are set to set the valid flag. And, the corresponding erase additional register is cleared, the erase enable register in the set state and the corresponding memory cell array are activated, the erase voltage pulse Ve is applied through the source line switch circuits (SS1 to SSn), and the erase verify control signal is output. Then, the erase verify determination signal corresponds to a good determination level. A second control circuit 16b for clearing the allowed registers provided, and write circuit 19b, sense amplifier 20b, the comparator 21b, and these circuits provided Y decoder 13b, the control circuit 16
According to the erase verify control signal from b, the erase state is verified with respect to the activated memory cell array, and when the result of the determination is determined to be good, the erase verify determination signal of the good determination level is transmitted to the control circuit 16b. In point.

That is, this flash memory is the first
The control circuit 16a and the input / output buffer circuit 17, the latch circuit 18, the write circuit 19a, the sense amplifier 20a, and the comparator 21a perform setting of the erase target block, pre-programming and verification thereof, and set a valid flag, and thereafter. The processing is performed by the second control circuit 16b and the writing circuit 1.
9b, the sense amplifier 20b, and the comparator 21b, and the erase operation and its verification by these circuits are performed.

Next, the operation and erase operation of this flash memory will be described with reference to the flow charts shown in FIGS.

First, when the control circuit 16a receives an erase command, the erase command process is started (step S21,
S22), the state where the valid flag is cleared (S2
Go to the next step in 3). Then, the transmitted erase block address is input and the corresponding erase additional register is set (S24, S25). Further, if there is a memory cell array to be erased, the erase additional register corresponding to the transmitted erase block address is set (S24, S2).
5) If not, proceed to next step (S26).

Next, the memory cell arrays corresponding to the erase addition registers in the set state are designated one by one (S27), pre-programming and verification thereof are performed (S28), and pre-programming and verification thereof are performed until verification OK (S29). To execute.

When the verification of all the memory cell arrays corresponding to the erased additional register in the set state becomes OK and the pre-programming ends, the corresponding valid flag is set (S30, S31), the erase command processing ends, and the next erase is performed. Wait for a command (S32). That is, when the pre-programming by one erase command is completed (including its verification), the valid flag is set, and the subsequent processing is moved to the second control circuit 16b, and the first control circuit 16a.
Waits for the next erase command.

On the other hand, the second control circuit 16b starts the erase operation when the power is turned on (S33), and the valid flag R is set.
It is checked whether or not a1 to Ran are set (S34), and the erase enable register corresponding to the set erase add register (valid flag) is set to clear the erase add register and the valid flag (S35, S).
36). If the valid flag is not set, the process directly proceeds to the next step.

Next, the erase voltage pulse Ve is applied to the memory cell array corresponding to the set state erase enable register via the source line switch to erase all at once (S37), and the memory cell array corresponding to the set state erase enable register. Are specified one by one to verify the erased state (S
38) If the verify is OK, it is determined that the erase is completed and the corresponding erase enable register is cleared (S40) so that the next erase voltage pulse Ve is not applied. Also,
If verification is not OK, the next step (S4)
Proceed to 1).

In step S41, it is checked whether or not the verification of all the memory cell arrays corresponding to the erase enable register in the set state has been completed. If not, that is, the verification has not been completed yet. If there is, the process returns to step S38 to perform the verification, and if all have been completed, the process returns to step S34 to repeat the operation from step S34.

In this flash memory and its erasing method, when the power is turned on, under the control of the second control circuit 16b, the set state of the valid flag is checked and the set state is transferred to the erase enable register. Instead, the batch erasing of the memory cell array corresponding to the erase register in the set state and the verification thereof are constantly repeated, while the erase command is accepted under the control of the first control circuit 16a. Erase command processing including setting of the erase block, pre-programming and setting of its verify valid flag is performed in parallel regardless of the operation of the first control circuit 16b.

Therefore, the processing for one erase command is only performed under the control of the first control circuit 16a, and the erase operation and its verification performed under the control of the second control circuit 16b. Is not included, so 1
Even if a processing time for one erase command becomes short and a memory cell array (memory block) to be erased is newly added, this erase command with a short processing time can be incorporated in a series of erase processing operations. .

Therefore, the erase processing time can be shortened even for the newly added memory cell array to be erased, and the erase processing time of the entire memory cell array can be shortened.

X decoders DX1 to DXn are provided corresponding to the memory cell arrays MA1 to MAn, respectively.
By providing two Y decoders 13a and 13b, erase block setting, pre-program and its verify processing operation, erase operation (erase voltage pulse application) and its verify operation performed under the first and second controls. And can be done independently.

[0066]

As described above, according to the present invention, the processing operation including the setting of the memory block to be erased through the erase addition register and the valid flag, and the processing operation including the erase operation to the memory block to be erased. Since the configuration is performed in parallel, there is an effect that the erase processing time including the newly added memory block to be erased can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a first flash memory of the present invention.

2 is a flowchart illustrating an operation and an erasing method of the flash memory shown in FIG.

FIG. 3 is a block diagram showing an embodiment of a second flash memory of the present invention.

4 is a first flowchart illustrating an operation and an erasing method of the flash memory shown in FIG.

5 is a second flowchart illustrating an operation and an erasing method of the flash memory shown in FIG.

FIG. 6 is a first block diagram of a conventional flash memory.

FIG. 7 is a flowchart illustrating an operation and an erase method of the flash memory shown in FIG.

FIG. 8 is a block diagram of a second example of a conventional flash memory.

9 is a flowchart illustrating an operation and an erasing method of the flash memory shown in FIG.

[Explanation of symbols]

 1 Command Analysis Circuit 2 Control Circuit 3 Verify Section 11 Address Buffer Circuit 12, 12x Address Latch Circuit 13, 13a, 13b Y Decoder 14 Y Selector 15 Control Signal Buffer Circuit 16a, 16b, 16x Control Circuit 17 Input / Output Buffer Circuit 18 Latch Circuit 19, 19a, 19b Write circuit 20, 20a, 20b Sense amplifier 21, 21, 21a, 21b Comparator 30 Control section DX, DX1 to DXn X decoder F1 to Fn valid flag MA1 to MAn Memory cell array MB1 to MB4 Memory block Ra1 to Ra4 , Ran Erase additional register Rb1 to Rb4, Rbn Erase enable register SS1 to SSn Source line switch

Claims (4)

[Claims] 1. A memory having a plurality of memory cells arranged therein, wherein the plurality of memory cells are collectively erased in accordance with an erase voltage pulse applied when a corresponding erase enable signal is at an activation level, and a memory having an address designated by a read / write control signal. Multiple memory blocks in batch erase unit for writing / reading data to / from cells, multiple erase addition registers and erase enable registers provided corresponding to each of these multiple memory blocks, and erased transmitted commands A command analysis unit that sets the erase addition register corresponding to the erase block address transmitted in the case of a block setting command and outputs an erase command processing signal in the case of an erase command; and a plurality of erase additions that receive the erase command processing signal. If any of the registers is in the set state, clear that set state. When the erase enable register corresponding to the last erase enable register is set to output the erase enable signal of the activation level and the erase add register is cleared, and there is a set state among the plurality of erase enable registers. After applying the erase voltage pulse to the plurality of memory blocks, the read / write control signal is output to verify the erase state of the collectively erased memory blocks. When the result of the verify is determined to be good, the memory A flash memory comprising a block and a control unit for clearing a corresponding erase enable register. 2. A method of erasing a flash memory, comprising: a plurality of memory blocks in a batch erase unit; and a plurality of erase addition registers and erase enable registers provided corresponding to the plurality of memory blocks, respectively. A first step of setting the erase additional register corresponding to an erase block address transmitted when the transmitted command is an erase block setting command; and a plurality of erase additional registers of the plurality of erase additional registers when the transmitted command is an erase command. If there is one in the set state, the erase enable register corresponding to the erase additional register in the set state is set and the erase additional register is cleared, and if there is no one in the set state, the process proceeds to the next step as it is. Procedure, and if there is a set state among the erase enable registers, A third procedure for supplying an erase voltage pulse to a certain number of memory blocks to erase all the memory blocks corresponding to the erase addition registers in the set state and ending the erase command processing if there is no one in the set state. The fourth procedure of verifying the erased state of the memory blocks collectively erased by the procedure of 1. and the clearing of the erase enable register corresponding to the memory block for which the result of the verification by the fourth procedure is determined to be good. And a fifth step of returning to the second step when the determination is not made. 3. When a plurality of memory cells are arranged and in an activated state, the plurality of memory cells are collectively erased in accordance with an applied erase voltage pulse, and data is written to or read from a memory cell at a designated address. An erase block having a plurality of memory blocks in a batch erase unit, a plurality of erase addition registers corresponding to each of the plurality of memory blocks, and a valid flag, and receiving an erase command and transmitting the plurality of valid flags if the valid flags are in a clear state. The erase additional register corresponding to the address is set, and the memory blocks corresponding to the erase added register in the set state are sequentially activated one by one, and the pre-program control signal is sequentially output, and the verify determination signal corresponds to the good determination level. Set the valid flag to A first control unit that completes the processing of the erase command when all the effect flags are in the set state and is ready to receive the next erase command; and the memory block in the activated state according to the pre-program control signal. When a preprogram for writing a predetermined level of data to all of a plurality of memory cells is executed and the state of the preprogram is verified according to a verify control signal and the result is judged to be good, the verify decision signal of a good decision level And a plurality of erase enable registers corresponding to each of the plurality of memory blocks, and if any of the plurality of valid flags is in the set state, it corresponds to the valid flag in the set state. The erase enable register is set to set this valid flag and the corresponding erase add register. The erase enable register in the set state is activated to activate the memory block, the erase voltage pulse is applied, the erase verify control signal is output, and the erase enable determination signal corresponds to a good determination level. A second control unit that clears a register, and the erase verify determination signal having a good determination level when the erase state of the activated memory block is verified according to the erase verify control signal and the result is determined to be good. And an erase verify unit for outputting 4. A method of erasing a flash memory, comprising: a plurality of memory blocks in a batch erase unit; and a plurality of erase additional registers, a valid flag, and an erase enable register corresponding to each of the plurality of memory blocks. If the plurality of valid flags are in the clear state, the first step of setting the erase additional register corresponding to the transmitted erase block address, and the memory block corresponding to the erase additional register in the set state are set to 1 A second procedure of activating each one and performing pre-programming and its verification, and if the result of the verification by this second procedure is good, the corresponding valid flag is set to set the valid flag corresponding to the additional register in the set state. When all are in the set state, the processing of the erase command is terminated and the next erase is performed. Corresponds to the third procedure for accepting the command and returning to the second procedure if the result of verification is not good, and the valid flag in the set state if any of the valid flags is in the set state. If the erase enable register is set and the valid flag and the corresponding erase addition register are cleared, and there is no one in the set state, the procedure proceeds to the next step as it is, and the memory corresponding to the erase enable register in the set state. The fifth step of activating blocks and applying an erase voltage pulse to erase all the memory blocks at once, and verifying the erase state by designating the memory blocks corresponding to the erase enable registers in the set state one by one If the result is good, clear the corresponding erase enable register and if it is not good, proceed directly to the next step. If the erase verify results of all the memory blocks corresponding to the erase enable register are good, the procedure returns to the fourth procedure, and if there is a bad result, the seventh procedure returns to the fifth procedure. How to erase flash memory.