JPH08329680A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To prevent malfunction and to reduce current consumption in an internally synchronizing type semiconductor storage device. CONSTITUTION: For example, NOR gate A0 transmits a logical change of an address pin A0 to EXOR circuit 420 , which outputs an pulse signal ϕ A0 of which a pulse width is set at a delay circuit 410 . A chip select circuit 50, based on an external chip select signal CS/, generates signals CS2/ and CS2 indicating an operating time state and a waiting time state respectively and also outputs a pulse signal S5 of the same pulse width as the signal ϕ A0. Here, a delay circuit 54 in the chip select circuit 50 synchronizes the timing of the pulse signal S50 with that of the pulse signal ϕ A0, and OR circuit 60 outputs clock ϕ of a desired pulse width. A gate part 70 supplies clock ϕ to each part of the semiconductor storage device only in an operating time state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as an internal synchronous static random access memory (hereinafter referred to as SRAM) having an address transition detection circuit.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference: Japanese Patent Publication No. 61-6471. In the above reference, the internal clock φ is provided by detecting a change in the logic level of at least one of the plurality of address pins A _{0 to} A _n provided in the semiconductor memory device. An internal clock generation circuit for generating is shown. The internal clock generation circuit includes a plurality of exclusive OR circuits (hereinafter, EX circuits) each having a logic level of each of the address pins A _{0 to} A _n and a signal obtained by delaying the logic level by a predetermined time Td as an input.
-OR circuit) and an OR circuit (hereinafter referred to as an OR circuit) that receives the output signals of the plurality of EX-OR circuits as inputs, and the clock φ is sent from the OR circuit. For example, when the logic level of the address pin A ₀ changes, the EX-OR circuit which receives it changes to output the “H” level during the period corresponding to the time Td.
This “H” level output is output as the clock φ via the OR circuit. Even _if the logic levels of the other address pins A _{1 to} A _n change, the same clock φ is ORed.
It is output from the circuit. The inside of the semiconductor memory device is controlled by this clock φ, and the semiconductor memory device operates in the same manner as an external synchronous type which gives a clock from the outside. For example, the clock φ can be applied to the equalize pulse and the precharge pulse, and further, the clock φ can be applied to the auto power down technique.

[0003]

However, the conventional semiconductor memory device has the following problems. In an actual low current consumption type SRAM or the like, a NOR gate or a NAND gate is adopted as an input buffer connected to an address pin in order to suppress a through current during standby. In the standby state, the chip select signal CS1 / (/ indicates level inversion) or the chip select signal CS
When 1 goes to "H" level or "L" level, a through current does not flow in the input buffer. FIG. 2 shows a NOR gate and N constituting an input buffer.
It is a figure which shows an AND gate. These NOR gate and N
The AND gates are both 2-input gates. One address pin A _x (x
Is a configuration in which a level of 0 ≦ x ≦ n) is input and the chip select signal CS1 / or CS1 is input to the other input terminal. The input buffer is, for example, N in FIG.
If it is composed of OR gates, address pins A _{0 to} A _0
When all the logic levels in _n are "H", even if the level of the chip select signal CS1 / changes from "H" during standby to "L" during operation, the output A _x o of the NOR gate
ut remains at “L” level. That is, there is a problem that the internal clock φ is not generated, and the following configuration is considered.

FIG. 3 is a circuit diagram showing an internal clock generating circuit using a conventional NOR gate. This internal clock generation circuit is a circuit for generating the clock φ even when the logic level at all the address pins A _{0 to} A _n is "H", and the plurality of address pins A _{0 to} A _n.
Of a plurality of NOR gates 10 ₀ whose level is one input
It has 10 to 10 _n . Each NOR gate 10 ₀ to 10 _n
The output side of is connected to the delay circuits 11 _{0 to} 11 _n and the EX-OR circuits 12 _{0 to} 12 _n , respectively. The delay circuits 11 _{0 to} 11 _n delay the output signals S10 _{0 to} S10 _n of the NOR gates 10 ₀ to 10 _n by a predetermined time Td, and the output sides of the delay circuits 11 _{0 to} 11 _n are also E
They are respectively connected to the input side of the X-OR circuit 12 ₀ to 12 _n. The output signal CS1 / of the chip select circuit 20 is connected to the other input terminal of each NOR gate 10 ₀ to 10 _n.
Is a common input connection. The chip select circuit 20 is for generating the chip select signal CS1 / and is provided with an inverter 21 which receives the chip select signal CS / from the outside. An inverter 22 is connected to the output side of the inverter 21, and the output signal CS1 / is output from the inverter 22. The output side of the inverter 21 is connected to the inverter 23
Is connected to one input terminal of a 2-input AND circuit 24 (hereinafter referred to as an AND circuit). The output side of the inverter 23 is connected to the delay circuit 25, and the output side of the delay circuit 25 is connected to the other input terminal of the AND circuit 24. The output sides of the AND circuit 24 of a plurality of EX-OR circuit 12 ₀ to 12 _n is connected to the OR circuit 30.

4 and 5 are waveform diagrams (Nos. 1 and 2) for explaining the problem of FIG. In the case of the configuration shown in FIG. 3, the following problems (i) and (ii) occur. (I) When the chip select signal CS / changes from the “L” level to the “H” level, that is, when the operating state changes to the standby state, any one of the address pins A _{0 to} A _n If it is at the "L" level, even if there is no logical change in the address pin, it operates as if the address changed internally. For example, as shown in FIG. 4, time t5
When the chip select signal CS / changes to "H",
EX-OR corresponding to "L" level address pin A _x
Circuit 12 _x output signal .phi.A _x of the time t7 from the time t6
It goes high during the time Td. In response to this, the OR circuit 30 outputs the "H" level. That is, a valid clock φ is generated even in the standby state, and an equalize pulse, a precharge pulse, etc. are generated. This includes a risk of malfunction and leads to extra current consumption.

(Ii) When the chip select signal CS / changes from "H" level to "L" level, that is,
When the standby state is changed to the operating state, the output signal S20 of the AND circuit 24 in the chip select circuit 20 is set to "H" between time t9 and time t10 shown in FIG.
Level pulses are formed. Then, a delay due to chip select circuit 20, by the delay due to the gate capacitance of the wiring resistance wiring capacitance and NOR gate 10 ₀ to 10 _n, corresponding to the "L" level of the address pins A _x EX-
In the output signal φA _x of the OR circuit 12 _x , a pulse of “H” level is formed from time t9 to time t12 after the delay time Tdca. Here, during the period when the level of the output signal φA _x is the “H” level,
Since it is time Td, the level of the output signal of the OR circuit 30 becomes the effective “H” level during Td + Tdca. That is, the width of the clock becomes wider by Tdca, and the width of the equalizing pulse and the precharge pulse becomes wider. In this case as well, including the risk of malfunction of the semiconductor memory device,
This will lead to extra current consumption.

[0007]

In order to solve the above problems, the present invention detects a logic change of an address input to generate an internal clock, and a state designated by a given chip select signal is in a standby state. An internal synchronous semiconductor memory device having an internal clock generating circuit for detecting the change from the state to the operating state and generating the clock has the following configuration. That is, the internal clock generation circuit in the semiconductor memory device of the present invention is a delay circuit that corrects the time lag between the clock generated based on the logical change of the address input and the clock generated based on the change of the state indicated by the chip select signal. And a gate unit configured to detect the state instructed by the chip select signal and stop the generation of the clock when the state becomes the standby state.

[0008]

According to the present invention, since the semiconductor memory device is configured as described above, the internal clock generating circuit operates when the logic of the address input changes or when the state designated by the chip select signal changes from the standby state to the operating state. Generates an internal clock when the state changes. The semiconductor memory device is synchronously controlled by the internal clock generated by the internal clock generation circuit. Here, the time lag between the internal clock generated by the logical change of the address input and the internal clock generated by the change of the state designated by the chip select signal is corrected by the delay circuit. Therefore, even if both internal clocks are generated, the clock output from the internal clock generation circuit has a desired pulse width. Further, the state instructed by the chip select signal is detected by the gate section, and when the state becomes the standby state, the generation of the clock is stopped. Therefore, in the standby state, the internal clock generation circuit does not generate the internal clock.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing an internal clock generating circuit showing a first embodiment of the present invention. The internal clock generating circuit is formed inside the semiconductor memory device and outputs a clock φ for controlling each part inside the semiconductor memory device based on the level change of the plurality of address pins A _{0 to} A _n .
Each address pin A ₀ to A _n are connected to one input terminal of the NOR gate 40 ₀ to 40 _n of the two inputs of the input buffer. The output side of each NOR gate 40 ₀ to 40 _n has a plurality of delay circuits 41 _{0 to} 41 _n and a plurality of EX-.
It is connected to each of the OR circuits 42 _{0 to} 42 _n .
Each of the delay circuits 41 _{0 to} 41 _n includes NOR gates 40 ₀ to 4 _0.
The output signals of 0 _n are each delayed by a predetermined time Td, and the output sides of the delay circuits 41 _{0 to} 41 _n are also E
It is connected to the input side of each of the X-OR circuits 42 _{0 to} 42 _n .

The chip select signal CS2 / output from the chip select circuit 50 is commonly input to the other input terminals of the NOR gates 40 ₀ to 40 _n .
The chip select circuit 50 includes an inverter 51 that inputs a chip select signal CS / from the outside. The inverter 52 is connected to the output side of the inverter 51. The chip select signal CS2 / is output from the output side of the inverter 52, and the chip select signal CS2 is output.
/ Is a configuration provided to each of the NOR gates 40 ₀ to 40 _n . An inverter 53 is further provided on the output side of the inverter 52, and from the output side of the inverter 53,
The chip select signal CS2 is output. The output side of the inverter 51 is also connected to the delay circuit 54. The output terminal of the delay circuit 54 is the inverter 5
5 input terminal and one input terminal of the 2-input AND circuit 56. A delay circuit 57 is connected to the output side of the inverter 55, and the output terminal of the delay circuit 57 is
It is connected to the other input terminal of the AND circuit 56.

The output signals φA _{0 to} A _{n of the} EX-OR circuits 42 _{0 to} 42 _n and the output signal S50 of the AND circuit 56 are connected to the OR circuit 60. OR
The output side of the circuit 60 is connected to the gate unit 70. The gate unit 70 has a function of preventing the clock φ from being generated when the chip select signal CS / indicates a standby state, and includes one PMOS 71 and two NMOSs 72 and 73. The output side of the OR circuit 60 has PMOS 71 and N
Commonly connected to the sources of the MOS 72. PMOS
The chip select signal CS2 / is input to the gate electrode of 71, and the chip select signal CS2 is input to the gate electrode of the NMOS 72. PMOS 71 and NMOS
The drain of 72 is connected to a node N1 which is an output terminal of the clock φ, and the drain of the NMOS 73 is connected to the node N1. The gate electrode of the NMOS 73 is connected to input the chip select signal CS2 /, and the source of the NMOS 73 is connected to the ground potential VSS.

FIG. 6 is a structural block diagram showing a semiconductor memory device using the internal clock generating circuit of FIG. In this semiconductor memory device, address pins A _{0 to} A _n for inputting an address are connected to the internal clock generation circuit 100 and the address buffer 110 of FIG. The address decoder 120 is connected to the output side of the address buffer 110, and the memory cell array 130 is connected to the output side of the address decoder 120. Memory cell array 1
An input / output buffer 140 is connected to 30, and the input / output buffer 140 is connected to the input / output terminal I / O.
The clock φ output from the internal clock generation circuit 100 is
The internal clock is supplied to the address decoder 120, the memory cell array 130, and the input / output buffer 140. FIG. 7 is a waveform diagram showing the operation of FIG. 1. The operation of the internal clock generating circuit of FIG. 1 will be described with reference to FIG. FIG. 7 shows an address input, a chip select signal CS / input from the outside, and a chip select signal CS2 /, output from the chip select circuit 50.
The CS2 and the output signal S50, the output signal φA _{x of} the EX-OR circuit 42 _x corresponding to a certain address A _x pin, and the clock φ are shown. The vertical axis represents the level and the horizontal axis represents the time.

First, at time t20, the address input changes, the levels of the address pins A _{0 to} A _n change logically, and the chip select signal CS / changes from "H" to "L" level. That is, when the standby state is changed to the operating state, the wiring resistance, the wiring capacitance, the NOR gate 40 ₀ to
Due to the delay due to the gate capacitance within 40 _n , the chip select signal CS2 / will be delayed from time t20 to time Tdca.
After that, at time t21, the “H” level changes to the “L” level. Similarly, the chip select signal CS2 changes from "L" level to "H" level at time t21 after time Tdca from time t20. Due to this logic change, the NOR gate 4 is connected to the address pin A _x of “L” level.
The output signal φA _x of the EX-OR circuit 42 _x connected via 0 _x becomes “H” level at time t22. The output signal φA _x returns to the “L” level again after the delay time Td due to the delay circuit 41 _x . That is, a pulse having a width of time Td is formed in the output signal φA _x . On the other hand, the delay circuit 54
Delay time is adjusted in advance, and signal S50 is "H".
It is set so that the time when the level becomes the same as the time when the output signal φA _x becomes “H”. The change in the chip select signal CS is delayed by the delay time of the delay circuit 54 and input to the AND circuit 56. This gives A
The level of the output signal S50 of the ND circuit 56 becomes "H" level at time t22. The output signal S50 returns to the "L" level again after the delay time Td by the delay circuit 57. A pulse having a width of time Td is formed in the output signal S50.
That is, there is no time difference between the pulse formed in the signal S50 and the pulse formed in the signal φA _x . Therefore, O
The R circuit 60 outputs a clock φ having a pulse width Td. Since the chip select signal CS2 / is "L" and the chip select signal CS2 is "H", P of the gate unit 70 is
The MOS 71 and the NMOS 72 are turned on, and the NMOS
73 is turned off. The gate unit 70 outputs the output pulse of the OR circuit 60 as the clock φ.

Clock φ output from internal clock generation circuit 100 is applied to address decoder 120, memory cell array 130 and input / output buffer 140, and FIG.
The function of each unit of the semiconductor memory device is controlled. Time t2
If the level of the chip select signal CS / changes from "L" to "H" level at 3, that is, when the operating state changes to the standby state, at time t24 after the time Tdca from the time t23, the chip select The signal CS2 / changes from "L" level to "H" level. Similarly, the chip select signal CS2 changes from "H" level to "L" level. Due to this change in logic, time t25
Then, the output signal φA _x of the EX-OR circuit 42 _x becomes the “H” level, and the delay time Td set by the delay circuit 41 _x.
After that, it becomes the "L" level. That is, a pulse having a pulse width Td is formed in the output signal φA _x . However, since the chip select signal CS2 / is "H" and the chip select signal CS2 is "L", the PMOS 71 and N
Both the MOS 72 are in the off state, and only the NMOS 73 is in the on state. Therefore, the output level of the internal clock generation circuit is forcibly set to the ground potential VSS, and the clock φ is not output.

As described above, in the present embodiment, since the delay circuit 54 is provided in the chip select circuit 50, the signal S
There is no deviation between the pulse formed in 50 and the pulse formed in the signal φA _x , and the clock φ having a desired width Td can be generated. Therefore, it is possible to prevent malfunction in the semiconductor memory device and reduce extra current consumption. Further, since the gate section 70 is provided on the output side of the OR circuit 60 that generates the clock φ, the clock φ is not generated in the standby state. This also makes it possible to prevent malfunctions in the semiconductor memory device and reduce extra current consumption.

Second Embodiment A feature of the internal clock generating circuit of this embodiment is that a gate portion 80 is provided in place of the gate portion 70 of the first embodiment, and the other portions are the same as those of FIG. It has the same configuration. FIG. 8 is a circuit diagram showing the gate portion of the second embodiment of the present invention. The gate unit 80 is connected to the output side of the OR gate 60, and has one PMOS 81, two NMOSs 82 and 83, and two delay circuits 84 and 8.
5 and. The output terminal of the OR gate 60 is P
Commonly connected to the sources of MOS81 and NMOS82,
The drains of the PMOS 81 and the NMOS 82 are both
It is connected to the node N2 which is an output terminal of the clock φ. The drain of the NMOS 83 is connected to the node N2, and the source of the NMOS 83 is connected to the ground potential VSS. The chip select signal CS2 / from the chip select circuit 50 of FIG. 1 is input to the delay circuit 84,
The delay circuit 85 is configured to receive the chip select signal CS2. The output side of the delay circuit 84 is the PMOS 81
Is commonly connected to the gate electrode of the NMOS 83, and the output side of the delay circuit 85 is connected to the gate electrode of the NMOS 82.

FIG. 9 is a waveform diagram showing the operation of the internal clock generating circuit having the gate portion of FIG. The operation of the internal clock generating circuit of this embodiment will be described with reference to FIG. When the state from the standby state to the operating state,
This internal clock generating circuit performs the same operation as in the first embodiment and outputs the clock φ. After that, at time t30 shown in FIG. 9, the chip select signal CS / becomes "H".
It becomes the level, and it becomes the “L” level at time t33. However, this standby state is assumed to be a period as short as the pulse width Td of the clock φ. The chip select signal CS2 / is connected to the wiring resistance, the wiring capacitance, and the NOR gate 4
Due to the delay due to the gate capacitance within ₀ to 40 _n ,
At time t31 after time Tdca from time t30,
The "L" level changes to the "H" level. Similarly, the chip select signal CS2 changes from "H" level to "L" level at time t31. The signals CS2d / and CS2d output from the delay circuits 84 and 85 are output to the delay circuit 8
With a delay of 4,85, at time t32 from time t31 to time Tdd, respectively, from “L” to “H” level,
The level changes from "H" to "L". Here, time t3
Since the signal CS2 / is at "H" level at 1,
EX-OR corresponding to "L" level address pin A _x
An “H” level pulse is formed in the output signal φA _x of the circuit 42 _x .

On the other hand, at time t33, the chip select signal C
Since S / goes to "L" level, the chip select signals CS2 /, CS2 are set at time t34 after time Tdca.
Then, it changes from "H" to "L" level and from "L" to "H" level, respectively. The signal CS2d / and the signal CS2d change from "H" to "L" level and from "L" to "H" level at time t35 after time t34, respectively. Here, at time t34, the signal CS2 / is set to the “L” level, so that the “H” level pulse is formed again in the output signal φA _x . In the case where the delay circuits 84 and 85 are not provided as in the first embodiment, when a short-time pulse is input as the chip select signal CS /, the standby state is first set as shown by the broken line waveform in FIG. Time t which is the rear end of the pulse of the output signal φA _x
A clock φ is output from 34. That is, the clock φ having the pulse width Td lengthened by the delay time Tdd in FIG. 9 is output. In this embodiment, the gate unit 80
Are provided with delay circuits 84 and 85. Delay circuits 84 and 8
By setting the delay time by 5 to Tdd, the clock φ is generated only by the pulse of the output signal φA _x when the second operating state is reached.

As described above, in the second embodiment, the delay circuit 84, and the internal clock generating circuit of the first embodiment are added.
Since 85 is provided, the clock φ having the desired pulse width Td can be output even when the input chip select signal CS / is a short pulse, that is, when a short standby state is given. it can. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the first and second embodiments, the gate parts 70 and 80 are connected to the output side of the OR circuit 60, respectively, but they are omitted and the outputs of the EX-OR circuits 42 _{0 to} 42 _n are output. Similar effects can be obtained even if the same gates as the gate portions 70 and 80 are provided on the respective sides. However, the delay time of the delay circuits corresponding to the delay circuits 84 and 85 in the gate unit 80 needs to be set corresponding to this configuration. (2) Gate portions 70, 8 in the first and second embodiments
0 turns the output signal of the OR circuit 60 on and off in the form of a transfer gate, but there is no problem if it is changed to a clocked inverter to output the clock φ / of the “L” level pulse. . Further, in the modified example of (1), the gate part on the output side of each EX-OR circuit is changed from the transfer gate form to the clocked inverter form, and an AND circuit is used instead of the OR circuit to generate a clock φ / May be output. However, in this case, it is necessary to invert the output signal S50 of the chip select circuit 50 by some method and input the inverted signal S50 / to the AND circuit.

[0020]

As described in detail above, according to the present invention, an internal clock generating circuit provided in an internal synchronous semiconductor memory device is provided with a clock and a chip select generated based on a logical change of an address input. Since the delay circuit that corrects the time lag with the clock generated based on the change in the state indicated by the signal and the gate unit that stops the clock generation when the chip select signal enters the standby state are provided, It is possible to generate a clock having a desired pulse width, and further, in the standby state, the clock is not erroneously generated. Therefore, malfunction of the semiconductor memory device can be eliminated, and extra current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an internal clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a NOR gate and NAN forming an input buffer.
It is a figure which shows a D gate.

FIG. 3 is a circuit diagram showing an internal clock generation circuit using a conventional NOR gate.

FIG. 4 is a waveform diagram (1) for explaining the problem of FIG.

FIG. 5 is a waveform diagram (2) explaining the problem of FIG.

FIG. 6 is a configuration block diagram showing a semiconductor memory device using the internal clock generation circuit of FIG.

FIG. 7 is a waveform diagram showing the operation of FIG.

FIG. 8 is a circuit diagram showing a gate unit according to a second embodiment of the present invention.

9 is a waveform diagram showing an operation of the internal clock generation circuit having the gate unit of FIG.

[Explanation of symbols]

40 ₀ to 40 _n NOR gate 41 _{0 to} 41 _n , 54, 57, 84, 85 Delay circuit 42 _{0 to} 42 _n EX-O
R circuit 50 Chip select circuit 56 AND circuit 60 OR circuit 70, 80 Gate unit A _{0 to An} Address pins CS, CS /, CS2, CS2 / Chip select signal φ clock

Claims (2)

[Claims] 1. An internal clock is generated by detecting a logical change of an address input, and the internal clock is detected by detecting that a state indicated by a given chip select signal has changed from a standby state to an operating state. In an internal synchronous semiconductor memory device having a clock generation circuit for generating, the internal clock generation circuit generates based on a change in a state indicated by the clock and a chip select signal generated based on a logical change of the address input. And a gate circuit configured to detect a state indicated by the chip select signal and stop generation of the clock when the state becomes the standby state. And a semiconductor memory device provided. 2. The semiconductor memory device according to claim 1, wherein the gate section is provided with a delay circuit that delays a detecting operation of a state instructed by the chip select signal in the gate section for a predetermined time.