JPH0832870A - Video signal processing method - Google Patents

Abstract

PURPOSE:To modify plural video signals with one special device and to synthesize them into one video signal by applying sub-sample processing to plural input video signals in the unit of picture elements, storing the result to a common memory and reading and outputting the video signal after it is stored. CONSTITUTION:A received video signal is written to a right half and a left half of an image memory for each picture element. When the video signal in the image memory 111 is read sequentially, the video signal is a signal in which two input video signals are reduced to 1/2 in the horizontal direction and synthesized into one video signal. That is, the two video signals having been spatially dispersed are in existence in continuous areas when viewing from an interpolation processing circuit 113 through wipe synthesis. A read address generating circuit 112 generates read addresses when the video signal is reduced to a half in the vertical direction. Thus, the interpolation processing circuit 113 implements reduction processing and the video signal being the synthesis of the two video signals is outputted from a video signal output terminal 114.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing method for synthesizing and transforming a television video signal.

[0002]

2. Description of the Related Art Conventionally, there is a video special effect device as a video signal processing device for converting the shape of a video signal. this is,
The television signals are converted into various shapes by writing the television signals in the memory in the raster scan order and reading out the contents of the memory in an arbitrary order as the television signals in the raster scan order. .

FIG. 13 shows the structure of a conventional image special effect device. In FIG. 13, as the constituent elements 1301
Is a video signal input terminal, 1302 is a horizontal low-pass filter, 1303 is a vertical low-pass filter, 1304
Is a memory, 1305 is an interpolation processing circuit, 1306 is a filter control circuit, 1307 is a read address generation circuit, 1
Reference numeral 308 is a video signal output terminal.

Next, the operation of the conventional image special effect device including the above-mentioned components will be described. In FIG. 13, the television signal input to the video signal input terminal 1301 is subjected to removal of high frequency signal components by the horizontal low-pass filter 1302 and the vertical low-pass filter 1303, and is written in the memory 1304 in raster scan order. The television signal written in the memory 1304 is several pixels from the memory 1304 in accordance with a memory address (hereinafter referred to as a read address) that is generated by the read address generation circuit 1307 and represents the input video coordinate corresponding to the output video coordinate. The minute signal is read out and transmitted to the interpolation processing circuit 1305. Interpolation processing circuit 1305
Then, according to the read address generated by the read address generation circuit 1307, the signal for several pixels read from the memory 1304 is subjected to interpolation processing, and is output from the video signal output terminal 1308 as an output signal. The filter control circuit 1306 calculates the reduction rate of the video signal from the read address generated by the read address generation circuit 1307, and performs filter control according to this reduction rate. The reason why the filtering process is performed on the input video signal is that aliasing distortion occurs in the output video signal unless the high frequency component of the video signal is removed in advance when the input video signal is reduced and output.

Next, the video switcher device will be described. 2. Description of the Related Art Conventionally, there is a video switcher device as a device that selects a video signal designated by a user from a plurality of video input signals or synthesizes a plurality of selected video signals and outputs them as one video signal. Such a conventional video switcher device is described in, for example, the 1992 Television Society Annual Conference Proceedings, items 271 to 272.

FIG. 14 shows the configuration of a conventional video switcher device. In FIG. 14, 140 is shown as a component.
1 is a video signal input terminal 1, 1402 is a video signal input terminal 2, 1403 is an MK circuit 3, 1408 is an MK circuit 4, 1
409 is the special effect device 1, 1410 is the special effect device 2,
1411 is a video signal output terminal. It should be noted that although a large number of video input terminals are prepared, the number of video input terminals is three here for simplification of description.

Next, the operation of the conventional video switcher device comprising the above-mentioned components will be described. In FIG. 14, the video signals input from the video signal input terminal 1, the video signal input terminal 2, and the video signal input terminal 3 are selected by the matrix switch 1404 to be desired video signals, and the MK circuit 1, the MK circuit 2, and the MK circuit are selected. 3, MK circuit 4
And a video signal output terminal 1411. Here, as the input signal of the matrix switch 1404, not only the video signal input terminal but also the video signal synthesized by each MK circuit is input. In this conventional example, the selected video signal is output from the device to the video signal output terminal 1411.

In each MK circuit, the matrix switch 1
A synthesis process of the two video signals selected by 404 is performed. The MK circuit of this conventional example can perform wipe composition, super composition, key composition, and chroma key composition as composition processing. Here, an operation of wipe combination, which is necessary for explaining the present invention as a combination process, will be described.

FIG. 15 shows an MK when performing wipe combination.
It is a processing block diagram of a circuit. In the wipe combination, a wipe key is generated by a wipe key generation circuit inside the MK circuit and is output as a key signal to the key combination circuit. The key combination circuit combines the two signals (input A and input B) selected by the matrix switch with the key signal.
Assuming that the key signal is normalized from 0 to 1, the output OUT of the key combination circuit can be calculated as follows.

OUT = A.times.Key + B.times. (1-Key) Therefore, for example, as shown in FIG. 16, the input A is made by the circular key signal (the key signal level inside the circle is 1 and the key signal level outside is 0). , When the video signal of the input B is wipe-combined, a composite signal as shown in FIG. 16D is obtained.

Further, as shown in FIG. 15, each MK circuit is provided with an input / output interface of a special effect device for input / output of a key combination circuit, so that the special effect device can be inserted before and after key combination. . That is, it is possible to process the video signal with the special effect device and then perform the wipe combining process, or process the video signal with the special effect device after the wipe combining process.

Next, a method of synthesizing two input video signals by adding special effects using the video special effect device and the video switcher device shown in the above-mentioned conventional example will be described.
Here, as shown in FIG. 17, a case will be described in which two video signals A and B are respectively subjected to reduction processing, combined, and a video signal C is output.

To obtain the output video signal C of FIG. 17,
The video switcher device and the video special effect device may be set as shown in FIG. In FIG. 18, the video signal input as the input A is input to the special effect device 1 through the MK circuit 1 by the selection of the matrix switch. In the special effect device 1, the video signal is reduced to 1/2 and moved in parallel to the left side of the screen. The video signal transformed by the special effect device 1 is input to the KeyMIX circuit (A) of the MK circuit 1. Similarly, the video signal input to the input B is input to the special effect device 2 through the MK circuit 1 by the selection of the matrix switch. In the special effect device 2, the video signal is reduced to 1/2 and moved in parallel to the right side of the screen. The video signal transformed by the special effect device 2 is
It is input to the KeyMIX circuit (B) of the MK circuit 1. M
In the wipe key generation circuit of K circuit 1, the right half of the screen is 1
Then, a Key signal whose left half is 0 is generated.
As a result, the signal after KeyMIX becomes a desired video signal, which is selected by the matrix switch and output from the video switcher device.

As described above, the transformation and synthesis of the two input video signals can be realized by connecting two special effect devices to the video switcher device.

[0015]

However, in the synthesis of video signals by the above-mentioned conventional video switcher device and video special effect device, in order to transform a plurality of video signals and synthesize them into one video signal, a plurality of video signals are required. The special effects device of must be connected to the video switcher device.

The present invention solves such a conventional problem, and is an excellent video signal that can be transformed into a single video signal by deforming a plurality of video signals with only one special device. It is intended to provide a processing method.

[0017]

In order to achieve the above object, the present invention performs a sub-sampling process on a plurality of input video signals in pixel units or line units, stores them in a common random access memory, and stores them in a memory. By reading out the latter signal, a plurality of video signals are respectively transformed so that one video signal can be combined.

In order to achieve the above object, the present invention performs a low-pass filter process adapted to the sub-sample process before the sub-sample process,
A plurality of video signals are respectively transformed so that one video signal can be combined.

[0019]

According to the present invention, since a plurality of input video signals are stored in a common random access memory in the above method,
It is possible to realize transformation of a plurality of video signals and composition into a single video signal by using only one special effect device.

Further, in the above-mentioned method according to the present invention, the generation of aliasing distortion is suppressed by the low-pass filter processing before the sub-sampling processing, and a plurality of video signals are respectively transformed by one special effect device to obtain one video. Combining into a signal can be realized.

Further, in the above-mentioned method according to the present invention, since a plurality of video signals are combined into one video signal by the wipe combining process and input to the video special effect device, a plurality of video signals can be obtained by only one special effect device. Deform each signal,
It is possible to realize synthesizing into one video signal.

Further, in the above method according to the present invention, since each video signal is moved in parallel to a desired position by the delay processing before the wipe combining processing, one unit of the input video signal is not noticed. It is possible to realize the transformation of a plurality of video signals into a single video signal by using only the special effect device.

Further, in the above method according to the present invention, a plurality of video signals are respectively transformed by only one special effect device by the slit-shaped wipe combining process without damaging the signals in the entire range of the input video signal. It is possible to realize synthesizing into one video signal.

Further, in the above method according to the present invention, a special effect can be obtained by suppressing the generation of aliasing distortion by the low-pass filter processing before the wipe combining processing and without damaging the signal in the entire range of the input video signal. It is possible to realize that the plurality of video signals are respectively transformed and combined into one video signal only by the device.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a video signal processing device of a first embodiment for carrying out the method of the present invention.

In FIG. 1, 101 is a video signal input terminal and 102 is a video signal input terminal as constituent elements. 1
Reference numeral 03 is a horizontal low-pass filter, 104 is a horizontal low-pass filter, 105 is a wipe key generation circuit, 106
Is a KeyMIX circuit, and these constitute an MK circuit. 107 is a filter control circuit, 108 is a horizontal low-pass filter, 109 is a vertical low-pass filter, 110 is a write address generation circuit, 111 is an image memory, 112 is a read address generation circuit, and 113 is an interpolation processing circuit. Is a special effect device. Reference numeral 114 is a video signal output terminal.

In the video signal processing apparatus according to the first embodiment including the above-mentioned components, the key MIX circuit 106 and earlier correspond to the MK circuit shown in the conventional example, and the horizontal low-pass filter 107 and subsequent ones have the special effects shown in the conventional example. Corresponds to the device.
Therefore, when actually constructed as a system, the connections are made as shown in FIG. 14 described above.

Next, the operation of the video signal processing apparatus of the first embodiment will be described with reference to FIGS. It is assumed that the video signals shown in FIGS. 2A and 2B are input to the video signal input terminal 101 and the video signal input terminal 102, respectively. Each video signal is low-pass filtered by the horizontal low-pass filters 103 and 104. At this time, the characteristic of the low-pass filter is that the cutoff frequency of the filter is 1 of the Nyquist frequency fN of the video signal.
Set it to be / 2. The video signal after the filter processing is wipe-synthesized by the KeyMIX circuit 106. The key signal generated by the wipe key generation circuit 105 is shown in FIG.
The signal has a vertical slit shape as shown in (c). In the first embodiment, each slit (where the key signal is 1 and 0
Width) is set to 1 pixel. The video signal of the wipe combined signal is filtered by the horizontal low-pass filter 108. In the first embodiment, as shown in FIG. 3, the horizontal low-pass filter 108 is realized by an FIR filter, and the delay amount of the delay device inside the filter is 2 clocks (2 pixels). The filter coefficient is determined according to the reduction rate of the video signal calculated by the filter control circuit 107. The video signal after the horizontal filter processing is filtered by the vertical low pass filter 109. The control of the vertical low-pass filter 109 is as follows.
Similar to the conventional example, it is determined according to the reduction rate of the video signal calculated by the filter control circuit 107. The video signal after the vertical filter processing is written in the image memory 111. In the first embodiment, the image memory 111 is written according to the write address output from the write address generation circuit 110.
Is written. Writing to the image memory in the conventional example is performed simply and sequentially with the input video signal, as shown in FIG. On the other hand, in the first embodiment, as shown in FIG. 4B, each pixel of the input video signal is written in the right half and the left half of the image memory. Therefore, when the video signals on the image memory 111 are sequentially read, the two input video signals are horizontally reduced to 1/2 as shown in FIG. It becomes a signal that is combined with the signal. That is, the two video signals spatially dispersed by the wipe synthesis are present in a continuous area as viewed from the interpolation processing circuit 113. In the first embodiment, the read address generation circuit 112 generates a read address when the video signal is reduced to 1/2 in the vertical direction. Therefore, the interpolation processing circuit 113 performs reduction processing, and the video signal output terminal 114 outputs
As shown in FIG. 2E, a video signal obtained by combining the two video signals is output.

As described above, in the first embodiment, although there is only one video special effect device, it is the same as the composite video signal obtained by two video special effect devices as in the conventional example. The video signal of can be obtained.

In the first embodiment, the image memory 11
The writing order to 1 is set so as to be arranged as shown in FIG. 4B, but this is a conceptual one, and when the hardware is created, it is not always necessary to write the data in FIG. It is not necessary to use the same physical address order of the memory as in b).

In the first embodiment, the read address generating circuit 112 halves the video signal in the vertical direction.
The read address is generated when it is reduced to
By dividing the output image into two continuous areas and generating the read address so that the left half of the image memory is read in one area and the right half of the image memory is read in the other area, It is possible to combine two different screens.

Further, in the first embodiment, the delay amount of the delay device of the horizontal low-pass filter 108 is set to 2 pixels, but by inserting a coefficient value 0 into the filter coefficient, the delay amount of the delay device is set. May be one pixel.

Further, in the first embodiment, the horizontal low-pass filter 108 is controlled by the output of the filter control circuit 107, but the filter control circuit 107 controls the horizontal low-pass filters 103 and 104 in the MK circuit. Therefore, the horizontal low-pass filter 108 may be simplified or omitted.

If the aliasing distortion due to the wipe composition does not cause a problem, the horizontal low-pass filter 103 is used.
And 104 may be omitted. Next, FIG. 5 is a diagram showing a configuration of a video signal processing apparatus of a second embodiment for carrying out the method of the present invention.

In FIG. 5, 501 is a video signal input terminal and 502 is a video signal input terminal as constituent elements. 5
Reference numeral 03 is a vertical low-pass filter, 504 is a vertical low-pass filter, 505 is a wipe key generation circuit, and 506.
Is a KeyMIX circuit, and these constitute an MK circuit. Reference numeral 507 is a filter control circuit, 508 is a horizontal low-pass filter, 509 is a vertical low-pass filter, 510 is a write address generation circuit, 511 is an image memory, 512 is a read address generation circuit, and 513 is an interpolation processing circuit. Is a special effect device. Reference numeral 514 is a video signal processing terminal.

The video signal processing apparatus shown in the second embodiment is
The KeyMIX circuit 506 and earlier correspond to the MK circuit shown in the conventional example, and the horizontal direction low-pass filter 507 and later correspond to the special effect device shown in the conventional example. Therefore, when actually constructed as a system, the connections are made as shown in FIG.

Next, the operation of the video signal processing apparatus comprising the above-mentioned respective components of the second embodiment will be described with reference to FIGS. 6 to 8. It is assumed that the video signals shown in FIGS. 6A and 6B are input to the video signal input terminal 501 and the video signal input terminal 502, respectively. Each video signal is low-pass filtered by vertical low-pass filters 503 and 504. At this time, the characteristics of the low-pass filter are set so that the cutoff frequency of the filter is 1/4 of the horizontal synchronizing frequency fH of the video signal. The video signal after the filter processing is wipe-synthesized by the KeyMIX circuit 506. The key signal generated by the wipe key generation circuit 505 is a horizontal slit-shaped signal as shown in FIG. In the second embodiment, the width of each slit (the part where the key signal is 1 and the part where the key signal is 0) is set to 1 line. The video signal of the wipe composite number is filtered by the horizontal low-pass filter 508. In the second embodiment, the horizontal low-pass filter processing is similar to the conventional example.
The filter coefficient is determined according to the reduction ratio of the video signal calculated by the filter control circuit 507. The video signal after the horizontal filtering is processed by the vertical low-pass filter 50.
Filtered by 9. As shown in FIG. 7, the vertical low-pass filter 509 is realized by an FIR filter, and the delay amount of the delay device inside the filter is set to 2 lines. The control of the vertical low-pass filter is determined according to the reduction rate of the video signal calculated by the filter control circuit 507, as in the conventional example. The video signal after the vertical filter processing is written in the image memory 511. In the second embodiment, writing to the image memory is performed according to the write address output from the write address generation circuit 510. Writing to the image memory in the conventional example is simply performed sequentially with the input video signal as shown in FIG. On the other hand, in the second embodiment, as shown in FIG. 8B, each line of the input video signal is written in the upper half and the lower half of the image memory. Therefore, when the video signals on the image memory are sequentially read, the video signals are as shown in FIG.
As described above, the two input video signals are vertically reduced to ½ to be a signal combined into one video signal. That is, the two video signals spatially dispersed by the wipe synthesis are present in a continuous area as viewed from the interpolation processing circuit 513. In the second embodiment, in the read address generation circuit 512, in the left half area of the output video signal, the video signal is horizontally reduced to 1/2 and a read address is generated when the image signal is translated in the lower left direction. To do. In the right half area of the output video signal, the read address is generated when the video signal is horizontally reduced to 1/2 and moved in parallel to the lower right. Therefore, the interpolation processing circuit 5
In 13, the reduction / parallel movement processing is performed, and the video signal output terminal 514 outputs a video signal in which the two video signals are combined as shown in FIG.

As described above, in the second embodiment, although there is only one video special effect device, it is the same as the composite video signal obtained by the two video special effect devices as in the conventional example. The video signal of can be obtained.

In the second embodiment, the writing order to the image memory is set so as to be arranged as shown in FIG. 8B. However, this is a conceptual one, and the hardware At the time of creation, it is not always necessary to use the same physical address order of the memory as in FIG.

Further, in the second embodiment, in the read address generation circuit 512, in the left half area of the output video signal, the video signal is horizontally reduced to 1/2 and moved in parallel to the lower left. The read address is generated, but the output image is decomposed into two continuous areas, the upper half of the image memory is read in one area, and the lower half of the image memory is read in the other area. By thus generating the read address, various two screens can be combined.

Further, in the second embodiment, the delay amount of the delay device of the vertical low-pass filter 509 is set to 2 lines, but by inserting the coefficient value 0 into the filter coefficient,
The delay amount of the delay device may be one line.

In the second embodiment, the output of the filter control circuit 507 controls the vertical low-pass filter 508, but the filter control circuit 507 controls the vertical low-pass filters 503 and 504 in the MK circuit. Therefore, the vertical low-pass filter 508 may be simplified or omitted.

If the aliasing distortion due to the wipe composition does not pose a problem, the vertical low-pass filter 503 is used.
And 504 may be omitted. Next, FIG. 9 is a diagram showing the configuration of a video signal processing device of a third embodiment for carrying out the method of the present invention.

In FIG. 9, as components, 901 is a video signal input terminal and 902 is a video signal input terminal.
903 is a variable delay device, 904 is a variable delay device, 905 is a wipe key generation circuit, and 906 is a KeyMIX circuit.
These constitute the MK circuit. 907 is a filter control circuit, 908 is a horizontal low-pass filter 909 is a vertical low-pass filter, 910 is a write address generation circuit, 911 is an image memory, 912 is a read address generation circuit, and 913 is an interpolation processing circuit. It constitutes the effect device. Reference numeral 914 is a video signal output terminal. The video signal processing device shown in the third embodiment is a Ke
The yMIX circuit 906 or earlier corresponds to the MK circuit shown in the conventional example, and the horizontal low-pass filter 907 or later corresponds to the special effect device shown in the conventional example. Therefore, when actually constructed as a system, the connections are made as shown in FIG.

Next, the operation of the video signal processing apparatus of the third embodiment, which comprises the above-mentioned respective components, will be described with reference to FIG. It is assumed that the video signals shown in FIGS. 10A and 10B are input to the video signal input terminal 901 and the video signal input terminal 902, respectively. The video signal of FIG. 10A is subjected to the parallel movement processing of the video signal by the variable delay unit 903. At this time, the delay amount of the variable delay device 903 is
The necessary portion in the video signal is set to move to the left half of the screen as shown in FIG. FIG.
The video signal of (b) is subjected to parallel movement processing of the video signal by the variable delay unit 904. At this time, the variable delay device 9
As for the delay amount of 04, the necessary portion in the video signal is shown in FIG.
As shown in (d), it is set to move to the right half of the screen. The video signal after the delay processing is the KeyMIX circuit 90.
The wipe composition is performed in step 6. The key signal generated by the wipe key generation circuit 905 is such that the left half of the screen is 1 and the right half is 0 as shown in FIG. The video signal after the wipe combination is the horizontal low-pass filter 90.
8 is low-pass filtered. In the third embodiment, the horizontal low-pass filter processing is the same as in the conventional example.
The filter coefficient is determined according to the reduction rate of the video signal calculated by the filter control circuit 907. The video signal after the horizontal filtering is processed by the vertical low-pass filter 909.
Filtered by. In the third embodiment, in the vertical direction low-pass filter processing, the filter coefficient is determined according to the reduction rate of the video signal calculated by the filter control circuit 907, as in the conventional example. The video signal after the vertical filter processing is written in the image memory 911. In the third embodiment, writing to the image memory is performed according to the write address output from the write address generation circuit 910. In the third embodiment, the write address generated by the write address generation circuit 910 is an address in which the input video signal is simply and sequentially written, as in the conventional example. In the third embodiment,
In the read address generation circuit 912, the video signal is used as an invalid area outside the screen in the upper area and the lower area of the output video signal, and an address is generated in the other area without being deformed. Therefore, the interpolation processing circuit 9
In No. 13, reduction / translation processing is not performed, and the video signal output terminal 914 outputs a video signal in which two video signals are combined as shown in FIG.

As described above, in the third embodiment, although there is only one video special effect device, it is the same as the composite video signal obtained by the two video special effect devices as in the conventional example. The video signal of can be obtained.

In the third embodiment, the read address generation circuit 912 generates a read address that does not modify the video signal, but the output image is decomposed into two continuous areas. By generating a read address so that the left half of the image memory is read in one area and the right half of the image memory is read in the other area, various two screens can be combined.

Further, in the third embodiment, the variable delay device is 2
The two input video signals are set so that they can be divided into the left and right sides of the screen, but the two input video signals are set so that they can be divided into two arbitrary areas of the screen, and the wipe key signal corresponding to these two areas is set. May be generated, and further, the read address may be generated in correspondence with the two areas to achieve the same effect as that of the third embodiment.

FIG. 11 is a diagram showing the construction of a video signal processing apparatus of the fourth embodiment for carrying out the method of the present invention. Figure 11
In the figure, 1101 is a video signal input terminal and 1102 is a video signal input terminal. Reference numeral 1103 denotes a horizontal low-pass filter, 1104 horizontal low-pass filter, 1105 a multiplexer circuit, 1106 a filter control circuit, 1107 a horizontal low-pass filter, 1108 a vertical low-pass filter, 1109 a write address generation circuit, 1110 an image memory, 1
Reference numeral 111 is a read address generation circuit, and 1112 is an interpolation processing circuit, which constitute a special effect device.
Reference numeral 1113 is a video signal output terminal.

Next, the operation of the video signal processing apparatus according to the fourth embodiment having the above components will be described. The video signals input to the video signal input terminal 1101 and the video signal input terminal 1102 are low-pass filtered by the horizontal low-pass filters 1103 and 1104. At this time, the characteristics of the low-pass filter are set so that the cutoff frequency of the filter is 1/2 of the Nyquist frequency fN of the video signal. The video signal after the filter processing is selected by the multiplexer circuit 1105 from the output signal of the horizontal low-pass filter 1103 and the output signal of the horizontal low-pass filter 1104 for each pixel. Therefore, the output signal of the multiplexer circuit 1105 is the KeyMIX circuit 106 in the first embodiment.
Becomes the same as the output signal of. The operation after the horizontal low-pass filter 1107 is the same as in the first embodiment. Therefore, the interpolation processing circuit 1112 performs reduction processing, and the video signal output terminal 1113 outputs a video signal in which the two video signals are combined.

As described above, in the fourth embodiment, one video special effect device can obtain the same video signal as the composite video signal obtained by the two video special effect devices as in the conventional example. it can.

In the fourth embodiment, the output of the filter control circuit 1106 is used as the horizontal low-pass filter 1107.
However, the horizontal low-pass filter 1107 is simplified by controlling the horizontal low-pass filters 1103 and 1104 with the filter control circuit 1106.
Alternatively, it may be omitted.

If the aliasing distortion generated in the multiplexer circuit does not pose a problem, the horizontal low-pass filters 1103 and 1104 may be omitted. FIG.
FIG. 2 is a diagram showing a configuration of a video signal processing device of a fifth embodiment for carrying out the method of the present invention.

In FIG. 12, 1201 is shown as a constituent element.
Is a video signal input terminal, and 1202 is a video signal input terminal. 1203 is a vertical low-pass filter, 1204 is a vertical low-pass filter, 1205 is a multiplexer circuit, 1206 is a filter control circuit, 1207 is a vertical low-pass filter, 1208 is a vertical low-pass filter, 1209 is a write address generation circuit, and 1210.
Is an image memory, 1211 is a read address generation circuit,
Reference numeral 1212 is an interpolation processing circuit, which constitutes a special effect device. Reference numeral 1213 is a video signal output terminal.

Next, the operation of the video signal processing apparatus of the fifth embodiment will be described. The respective video signals input to the video signal input terminal 1201 and the video signal input terminal 1202 are the vertical low-pass filters 1203 and 1
Low-pass filtering is performed by 204. At this time,
The characteristics of the low-pass filter are set so that the cutoff frequency of the filter is 1/4 of the horizontal synchronizing frequency fH of the video signal. The output video signal of the vertical low-pass filter 1203 and the output signal of the vertical low-pass filter 1104 are selected for each line by the multiplexer circuit 1205 from the filtered video signal. Therefore, the output signal of the multiplexer circuit 1205 becomes similar to the output signal of the KeyMIX circuit 506 in the second embodiment. The operation after the vertical low-pass filter 1207 is the same as that of the second embodiment. Therefore, the interpolation processing circuit 1212 performs reduction / parallel movement processing, and the video signal output terminal 1213 outputs a video signal obtained by combining the two video signals.

As described above, in the fifth embodiment, one video special effect device can obtain the same video signal as the composite video signal obtained by the two video special effect devices as in the conventional example. You can

In the fifth embodiment, the output of the filter control circuit 1206 is used as the vertical low-pass filter 1207.
The vertical low-pass filter 1207 is simplified by controlling the vertical low-pass filters 1203 and 1204 by the filter control circuit 1206.
Alternatively, it may be omitted.

If the aliasing distortion generated in the multiplexer circuit does not pose a problem, the vertical low pass filters 1203 and 1204 may be omitted.

[0059]

As is apparent from the description of the above embodiments, the present invention provides a wipe combining process using a slit-shaped key signal,
By controlling the memory writing and the memory read address calculation in the special effect device adapted to the slit shape, one video special effect device
A plurality of video signals can be transformed respectively to synthesize one video signal.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a video switcher device and a video special effect device in a video signal processing method according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a video signal processing procedure in the embodiment.

FIG. 3 is a configuration diagram of a horizontal low-pass filter in the example.

FIG. 4 is a schematic diagram for explaining a writing order of the image memory in the embodiment.

FIG. 5 is a schematic block diagram of a video switcher device and a video special effect device in a video signal processing method according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram for explaining a video signal processing procedure in the embodiment.

FIG. 7 is a configuration diagram of a vertical direction low-pass filter in the example.

FIG. 8 is a schematic diagram for explaining the writing order of the image memory in the embodiment.

FIG. 9 is a schematic block diagram of a video switcher device and a video special effect device in a video signal processing method according to a third embodiment of the present invention.

FIG. 10 is a schematic diagram for explaining a processing procedure of a video signal in the embodiment.

FIG. 11 is a schematic block diagram of a video special effect device in a video signal processing method according to a fourth embodiment of the present invention.

FIG. 12 is a schematic block diagram of a video special effect device in a video signal processing method according to a fifth embodiment of the present invention.

FIG. 13 is a schematic block diagram of a conventional image special effect device.

FIG. 14 is a schematic block diagram of a conventional video switcher device.

FIG. 15 is a block diagram illustrating a process during a wipe combining operation in the MK circuit of the conventional video switcher device.

FIG. 16 is a schematic diagram for explaining processing during a wipe combining operation in the MK circuit of the conventional video switcher device.

FIG. 17 is a schematic diagram for explaining a processing procedure for synthesizing a plurality of screens by a conventional video switcher device and a video special effect device.

FIG. 18 is a block diagram for explaining a processing procedure for synthesizing a plurality of screens by a conventional video switcher device and video special effect device.

[Explanation of symbols]

 101 video signal input terminal 102 video signal input terminal 103 horizontal low-pass filter 104 horizontal low-pass filter 105 wipe key generation circuit 106 KeyMIX circuit 107 filter control circuit 108 horizontal low-pass filter 109 vertical low-pass filter 110 write address generation circuit 111 image memory 112 Read-out address generation circuit 113 Interpolation processing circuit 114 Video signal output terminal

Claims (11)

[Claims] 1. A video signal processing method for converting a shape of a video signal by storing an input video signal in a random access memory, reading out and outputting the video signals stored in the random access memory in a different order from the time of storage. A video signal processing method in which a plurality of input video signals are subsampled in pixel units, the subsampled video signals are stored in a common memory, and the video signals stored in the memory are read and output. 2. A video signal processing method for converting a shape of a video signal by storing an input video signal in a random access memory, reading out and outputting the video signals stored in the random access memory in a different order from the time of storage. A video signal processing method of sub-sampling a plurality of input video signals line by line, storing the video signals after the sub-sampling processing in a common memory, and reading out and outputting the video signals stored in the memory. 3. The video signal processing method according to claim 1, wherein before the input video signal is sub-sampled, the input video image is processed according to a conversion ratio of a sampling frequency in the sub-sampling process. A video signal processing method for low-pass filtering a signal. 4. A plurality of input video signals are wipe-synthesized into a single video signal, the wipe-synthesized video signal is stored in a random access memory, and the video signal stored in the random access memory is different from the storage time. A video signal processing method that transforms the shape of a digital video signal by reading and outputting it in order. 5. The video signal processing method according to claim 4, wherein the input video signals are individually delayed before being wipe-synthesized with each other. 6. The video signal processing method according to claim 4, wherein a wipe key signal used when two input video signals are wipe-combined is synthesized such that the two input video signals are replaced every other sample. Video signal processing method set to wipe key signal. 7. The video signal processing method according to claim 6, wherein the input video signal is subjected to horizontal low-pass filtering before the input video signal is wipe-combined. 8. The video signal processing method according to claim 4, wherein a wipe key signal used when two input video signals are wipe-synthesized is synthesized by replacing the two input video signals every other line. Video signal processing method set to wipe key signal. 9. The video signal processing method according to claim 8, wherein the input video signal is subjected to vertical low-pass filter processing before the input video signal is wipe-combined. 10. The video signal processing method according to claim 1, claim 2, claim 3, claim 4, claim 6, claim 7, claim 8, or claim 9 When writing the video signal of to the random access memory,
A video signal processing method for controlling a memory write address so that a plurality of input video signals are respectively written in logically continuous areas. 11. The video signal processing method according to claim 1, wherein a special effect is applied to the plurality of video signals.