JPH08328690A - Time management system device - Google Patents

Abstract

PURPOSE: To use a new processor for a time master with a priority different from that at system start revised in on-line by providing a master priority revision means and a master management means selecting again the time master to the system device. CONSTITUTION: The device is provided with a master management means 12a deciding a sole time master based on a master 1st priority and a master 2nd priority among processors whose master flag is set to 'master enable' and a master priority revision means 16a revising the master 2nd priority of an optional processor. Then a sole time master is selected among processors whose flag is set to 'master enable' based on the master 1st priority and the master 2nd priority and when the master end priority is revised in on-line from an optional processor, a new time master is again selected based on the master 1st priority and the master 2nd priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time management system device for controlling the time synchronization between the processors on a multiprocessor system consisting of a plurality of processors connected by a network.

[0002]

2. Description of the Related Art Time management in a network environment depends on how to synchronize the time among a plurality of computers connected by a network, and various methods have been conventionally proposed. FIG. 19 is a block diagram showing a configuration of a conventional time management system device in a multiprocessor system disclosed as a time management system of a data transmission device in Japanese Patent Laid-Open No. 4-233015. In the figure, 1
111n are processors, 112 is a network connecting the processors 111a, 111b, ... 111n, 129a, 129b, ... 129n are CPUs for monitoring the entire processors, 110a, 110b, ... 1
10n is clock means for measuring the time in the processor, 12
Reference numerals 7a, 127b ... 127n are network control means for controlling transmission and reception of data on the network 112, and 128a, 128b ... 128n are assigned reception data such as time information by the network control means 127a, 127b ... 127n to each processor. Buffers 130a, 130b for storing at specified addresses
... 130n is a time information update monitoring timer for measuring a monitoring time for monitoring the update of time information, 131a, 131b ...
Reference numeral 131n is a back-off monitoring timer that counts a fixed time when the system is started and then issues a timeout notification to the CPUs 129a, 129b ... 129n.

Next, the operation will be described. FIG. 20 is a flow chart showing the time synchronization processing operation by this conventional time management system device. According to this flowchart, each of the processors 111a, 111b ... 111n receives the reception buffers 128a, 128n after the system is started.
b ... 128n is monitored for update of time information, and whether or not the time is updated within the monitoring time of the backoff monitoring timers 131a, 131b ... 131n (steps ST100, ST101), and when not updated, the time is updated. Becomes master and clock means 110 of its own processor
a, 110b ... 110n are read, and the read time information is output to the network 112 (step ST10).
5). Note that the operation in which the processor outputs the time information to the network and distributes the time information to other processors in this way is referred to as broadcasting hereinafter. The time information broadcast to the network 112 is stored in a predetermined area in the reception buffer of another processor.

When a plurality of processors broadcast the time information in their own processor, as in the case of the processor, a plurality of areas allocated to each processor in the reception buffer are updated. Therefore, the respective time information update monitoring timers 130a, 130b ... 130n
It is monitored whether or not a plurality of areas in the reception buffer are updated within the monitoring time of (step ST106, step ST107), and if a plurality of areas are updated, step ST
Return to 100. Since the timeout time of the backoff monitoring timer is set to a different value for each processor,
When a plurality of processors try to become time masters at the same time, each processor monitors the update of the time information in the reception buffer until the backoff monitoring timer times out in step ST100, and if there is one update of the time information, it is a slave. Therefore, the processor that broadcasts the time information earliest becomes the time master.

As described above, when the slave becomes a slave by updating the time information detected in step ST101, the time information in the reception buffer is referred to and the time information is set in the clock means in the processor itself (step ST102). ). Then, it is monitored whether or not the time information is updated within the monitoring time of the time information update monitoring timer (steps ST103 and ST104), and if the time information is not updated, the process returns to step ST100. If the time information is updated, the process returns to step ST102.

Next, ti used for time management in an environment where a plurality of UNIX workstations are operated.
A system called med will be described based on the flowcharts shown in FIGS. 21, 22, and 23. The time master broadcasts a master notification message at regular time intervals (step ST110), and the other processors monitor whether or not the master notification message transmitted from the time master is transmitted within the constant time (step ST111). , Step ST112), if it is not sent within a fixed time, it is determined that an abnormality has occurred in the time master, and re-arbitration of the master is started (Step ST1).
13).

After the master arbitration is started, it is determined whether or not the own processor is already set as a master candidate at the time of startup (step ST120), and if it is not set as a master candidate, it becomes a slave (step ST127).
If it is set as a master candidate, its own processor tries to become a new time master and broadcasts a master request message to other processors (step ST1).
22), and determines whether there is a rejection response from another processor (step ST123, step ST124). If there is no refusal response, the processor itself becomes the time master (step ST126).

When a plurality of processors try to become the time master at the same time, a refusal response is returned from the other processors trying to become the time master. Step ST
When it is determined in 124 that the rejection response has been returned, the process waits until the time calculated by the random function has elapsed (step ST125). Step ST12
During the wait in 5, the slave remains as it is, and when a master request message is sent from another processor during the wait, a permission message is returned to that processor, so the wait time is the shortest in step ST125. The processor becomes the time master. After that, the process returns to step ST111 shown in FIG.

[0009]

Since the conventional time management system device is configured as described above, the candidates for the time master are determined at system startup and cannot be changed flexibly, so they are determined at system startup. There was a problem that it was necessary to stop the system when changing the priority order of the time master.

In the former time management system device in the above-mentioned prior art, the time master of the time master is judged based on whether the time master updates the time at regular time intervals or whether the update time is different from the previous time. When an abnormality is detected, the latter time management system device adopts a criterion to determine whether or not a master notification message is sent from the time master at regular intervals, and it seems that the time master's time progress is not normal. In this case, there is a problem that the abnormality occurring in the time master cannot be detected.

Further, in the latter time management system device, in a system in which a plurality of networks are connected by gateways, when the time master disappears on one network, the processor acting as a gateway itself becomes a new time master. However, there is a problem that it is necessary to stop the system in order to select a time master from processors on other plural networks.

Further, if the time is synchronized when there is a time difference between the internal time in the processor on the receiving side of the synchronization and the reference time of the time master, the continuity of the internal time is lost and, as a result, the internal time is lost. Software that uses a clock also has problems such as affecting operation.

The present invention has been made in order to solve the above-mentioned problems, and the time master can be flexibly selected without stopping the system, and the operation of the software is affected by synchronizing the time. In some cases, it is an object of the present invention to obtain a time management system device that can flexibly deal with the influence.

[0014]

According to another aspect of the present invention, there is provided a time management system apparatus, wherein the time in a time setting request message periodically sent from a processor which is a time master is set by a clock means of its own processor. The time setting means for setting the master second priority order of each processor set to "masterable" by the master flag from any processor online, Only one time master is selected based on the master first priority order and the master second priority order of the processor set to “possible”, and the master second priority order is changed by the master priority order changing means. When the system is started, based on the master first priority and the changed and newly set master second priority, It is obtained by configured with a master management unit for selecting a time master by different priorities again.

A time management system device according to a second aspect of the present invention is provided with a structure for setting the master second priority within a range of three stages of high / medium / low.

A time management system device according to a third aspect of the present invention periodically broadcasts a master notification message to the network on condition that the own processor is the time master, and on the condition that the own processor is not the time master. A master management unit that monitors whether or not a master notification message is sent within a certain period of time, and if it is not sent, reselects a new time master from among the processors set to "master enabled" and the time of day. Time setting request rejection messages are sent from a certain number or more of processors on the network until the fixed time elapses in response to the time setting request message broadcast by the master that has a compulsory setting flag indicating "not forcibly set". Depending on whether it comes or not, the time master processor Reselect the time master with the second priority set to the lowest level, or set the compulsory setting flag to "compulsively set" assuming that the requests were permitted by many processors, and then try again. Or a time synchronization control means for performing either control.

In the time management system device according to the invention of claim 4, when the time setting is requested via the interface means provided in each processor and interfacing with the host application or the external clock device, "time setting" is carried out. The external time synchronization control means for broadcasting the time setting request message including the compulsory setting flag indicating the above is provided.

In the time management system device according to the fifth aspect of the present invention, in the processor which is the gateway between the networks, the master flag is "slave" for one network and "master capable" for the other network. , And the master first priority and the master second priority are set to values higher than those of other networks for the network set to “master enabled”, the reference time between networks is set. When the time master disappears for a network in which the gateway processor is a slave, the master flag is changed to "masterable" for that network, and the gateway processor is used until then. For the network that was the time master After the master second priority set change to an intermediate level, it is obtained as comprising a master management unit for performing reselection time master.

In the time management system device according to the sixth aspect of the present invention, the processor that receives the time setting request message synchronizes the time information in the time setting request message with the time by the clock means in its own processor. And a time synchronization control function for controlling the time synchronization control function, time synchronization control function selection means for selecting control by the time synchronization control means, upper software for controlling the time synchronization control function selection means, and the time setting request message. A time setting request receiving means for notifying the time setting request reception event to the higher-level software and a time setting means for setting the reference time of the time master read from the higher-level software to the clock means of its own processor are provided. It is a thing.

[0020]

According to the time management system of the present invention, only one time master is selected from the processors set to "masterable" based on the master first priority and the master second priority. If the master second priority is changed online from an arbitrary processor, a new time is set based on the master first priority and the changed and newly set master second priority. Since the master is selected again, the priority set at system startup can be changed online, and a specific processor can be set as a new time master from the processors set to "master enabled", and the system can be stopped. Flexible selection of the time master without involving.

According to a second aspect of the present invention, there is provided a time management system device based on a master first priority order and a master second priority order set by values in a three-step range of high / middle / low.
Only one of the processors set to "masterable"
Number of time masters, and when the master second priority is changed online from an arbitrary processor, the master first priority and the changed high / medium / low three-level range are selected. A new time master is selected again based on the newly set master second priority, so the priority set at system startup is changed online and specified from the processors set to "masterable". The processor can be used as a new time master, and the time master can be flexibly selected without stopping the system.

According to another aspect of the present invention, in the time management system device, if the master notification message is not sent within a fixed time when the own processor is not the time master, a new processor is selected from among the processors set to "masterable". Re-selects the time master, and broadcasts the time setting request message that has the forced setting flag that indicates "not forcibly set" when the self-processor is the time master, and waits until the fixed time elapses. If a time setting request reject message is sent from a certain number or more of the above processors, the time master is re-selected with the second master priority of the processor of the time master set to the lowest level. The time setting request rejection message sent from the processor on the network before the time elapses. If the number of messages is less than a certain number, it is considered that requests have been accepted from many processors and the compulsory setting flag is set to "compulsory setting" and the time setting request message is broadcast again. For a failure that occurs in the time master that is not normal, the normal time master ensures the reference time.

According to the fourth aspect of the invention, when the time management system device requests the time setting from the host application or the external clock device, the processor which has received the request has a compulsory setting flag which indicates "forced setting". It broadcasts a time setting request message to the network and enables setting of non-contiguous times for all processors in the network.

In the time management system device according to the invention of claim 5, the master flag of the processor acting as a gateway is set to "slave" for one network and "masterable" for the other network, and By setting the master first priority and the master second priority to be higher than the processors of other networks for the processors of the network set to "masterable", the processor that becomes the gateway between the networks can be Slave for one network,
For the other network, the reference time of the other network is made to flow to the one network so as to become the time master, and when the time master of the network in which the processor that is the gateway is a slave disappears, By changing the master flag of the network to “master possible” and changing the second priority of the master to an intermediate level and reselecting the time master for the network in which the processor was the time master, Even if all the time master processors disappear, the time master is selected from master candidates on other networks, and the time master candidates can be arranged on a plurality of networks.

In the time management system device according to the invention of claim 6, when the time setting request message is received through the time setting request control means, it is determined whether the time synchronization control means synchronizes the clock means with the designated time. The time setting request receiving means notifies the upper software of the time setting request receiving event.
The time setting means sets the reference time of the time master to the clock means of its own processor by the above-mentioned upper software. Therefore, when the higher-level software is using the internal time, the higher-level software waits for the specified time when the time setting request message is received via the time synchronization control function selection means and the synchronization processing with the clock means. The synchronization can be executed at a desired timing, and the influence of synchronizing the time on the operation of the host software can be avoided.

[0026]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a time management system device according to a first embodiment of the present invention. In the figure, 9
Is a network, 10a ... 10n are processors connected to the network 9, 11a is clock means for measuring the internal time of the processor 10a, and 12a is a master first among processors whose master flag is set to "masterable".
It is a master management means for determining only one time master based on the priority order and the master second priority order. Reference numeral 13a is the master flag set in the processor 10a and indicating either "master possible" or "slave". 1
4a is the master first priority order that is initially set to a different value for each processor, and 15a is a master second priority order that is initially set in each processor in the range of three levels of high / middle / low and can be changed online. is there.

Reference numeral 16a denotes a master priority changing means for changing the master second priority of an arbitrary processor, 17a reads master information managed by the master managing means 12a, and only when the own processor is a time master, the network is read. 9 is a time synchronization means (time synchronization control means) for broadcasting the time setting request message to 9; and 18a is a time setting request receiving means for receiving the time setting request message sent from the processor which is the time master.
19a, when receiving the time setting request, the clock means 11
It is a time setting means for setting the time to a.

Processor 1 connected to network 9
The internal configuration of the processor 10n other than 0a is the same as the internal configuration of the processor 10a.
Each block that is the same as the above is denoted by the same numeral with different subscripts of the alphabet.

Next, the operation will be described. 2, 3 and 4 are flowcharts showing the operation of the time management system device, FIG. 2 is a master arbitration processing operation, FIG. 3 is a time setting request message output processing operation, and FIG. 4 is a time information setting processing operation. It is a flowchart showing. Of the plurality of processors 10a ... 10n, the master flag of the processor that is a candidate for the time master is set to “master possible”. As a result, the set value of the master flag is stored in the non-volatile memory of each processor. Further, for the processor whose master flag is set to "masterable", the master first priority order is initially set to a different priority order value for each processor. Furthermore, the master second priority is initialized to the intermediate level.

The prioritization of the time master is initialized by the master priority 1 which is initialized to a different value for each processor and the master second priority which is initialized to an intermediate level. Then, as shown below, the master second
Change the time master by changing the priority online. That is, the master management means 12a ... 12n
Reads the master flag held internally and checks whether or not the master flag is set to "master possible" (step ST10, step ST
11). If the master flag is set to "master possible", master arbitration processing is started (step ST1).
2). In this master arbitration processing, the master first priority order and the master second priority order of all the processors whose master flag is set to “master possible” are acquired and are higher than the master second priority order of the own processor. It is checked whether or not there is a processor having the value master second priority (step ST14, step ST15). Then, if there is a processor having a master second priority higher than that of its own processor, it becomes a slave (step ST
20) Further, it is determined whether or not there is a change in the master second priority, and when there is no change, the master arbitration processing is ended.

When it is determined in steps ST14 and ST15 that the master second priority of the processor itself is the highest, it is checked whether or not there is another processor having the highest master second priority (step ST16). ), Otherwise, it becomes the time master (step ST19).

Since the master second priority of each processor is initially set to the medium level, the master first priority is set in steps ST17 and ST18 in the initial state.
The time master is determined by the priority order.

When it is determined in step ST16 that there is another processor having the highest master second priority, the master first priority is compared in the following steps ST17 and ST18, and if the own processor is not the highest. It becomes a slave (step ST20), and if it is the maximum, it becomes a time master (step ST19). After the master arbitration process for the time master or slave is completed in step ST19 or step ST20, it is monitored whether or not the master second priority has been changed (step ST21), and if there is a change, the process returns to step ST10, The master arbitration process is performed again.

On the other hand, the time synchronization means 17a of each processor
... 17n periodically reads the master information held by the master management means 12a ... 12n, and if the processor itself is a time master, reads out the clock means 11a ... 11n (step ST31), and the time including the read time. The setting request message is broadcast to the network 9 (step ST32). The slave processor receives this time information (step ST3
3), set to internal clock means (step ST3)
4).

As described above, in the conventional time management system device, only one master priority order is prepared, and it is not possible to change online. In contrast, in this embodiment, the master first priority order and the master first order are set. 2 of 2 priority
By preparing one master priority and making it possible to change the master second priority online, the time master can be changed even while the system is operating. Even when the master second priority is set to the same level for a plurality of processors, only one time master can be selected according to the master first priority initially set to a different value for each processor. .

Example 2. Embodiment 2 of the present invention will be described below with reference to the drawings. FIG. 5 is a block diagram showing the configuration of the time management system device according to the second embodiment. 5, parts that are the same as or correspond to those in FIG. 1 are assigned the same reference numerals and explanations thereof are omitted. In the figure, 21a is a time setting request check means for checking the compulsory setting flag in the received time setting request message, and judging whether or not the designated time is set in the clock means 11a in its own processor, and 22a is It is a time setting request response receiving means for receiving a time setting request rejection message returned from another processor after broadcasting the time setting request message. Here, the compulsory setting flag is a flag indicating whether the time is compulsorily set or not set when the slave processor receives the time setting request message. Is a flag specified when the time setting request message is broadcast to the network 9.

Next, the operation will be described. 6 and 7,
8 and 9 are flowcharts showing the operation of the time management system device of this embodiment. FIG. 6 is a master notification message output processing operation, FIG. 7 is a time master re-arbitration start processing operation, and FIG. 8 is a master. FIG. 9 is a flowchart showing a time synchronization control processing operation performed by the management means and the time synchronization means, and FIG. 9 is a time synchronization processing operation on the slave side. Note that the master arbitration process is the same as that in the first embodiment, and therefore its explanation is omitted.

In this embodiment, the processors 10a ... 10
Among a plurality of processors such as n, the master flag of the processor that is the candidate for the time master is set to “masterable”. Further, with respect to the processor whose master flag is set to "masterable", the master first priority order is initially set to a value that gives a different priority order for each processor. Further, the master second priority is set to the intermediate level.

After such settings are made, in each processor such as the processors 10a ... 10n, the respective master management means 12a ... 12n check whether or not the own processor is the time master and become the time master. If so, a master notification message is broadcast to the network 9 at regular intervals (step ST4).
0).

The slave processor monitors whether or not the notification message is transmitted from the time master within a fixed time (steps ST41 and ST42), and when it is transmitted, the notification message is transmitted to step ST41.
Return to and continue monitoring. If it is not transmitted, re-arbitration of the master is started (step ST43).

Each of the time synchronization means 17a ... 17n periodically reads the master information held by the respective master management means 12a ... 12n, and if the own processor is the time master, the clock means is read (step ST50). ), The time setting request message with the forced setting flag set to “not forcibly set” is broadcast to the network 9 (step ST51). After that, it is monitored whether or not a time setting request rejection message is transmitted until a fixed time has elapsed (step ST52). If more than a certain number of refusal messages (a value determined by the number of processors on the network and stored in a non-volatile memory by a setting tool, etc.) are sent, the time master becomes the time master. Since there is a possibility that the clock means of its own processor is abnormal, the master second arbitration processing is set to a low level and then the re-arbitration processing of the master is started (step ST55). If the number of reject messages is less than a certain number in step ST53, it is determined that the requests have been permitted by a large number of processors, the time is read again, and the force setting flag is set to "force setting". Broadcast a setting request message to the network 9 (step ST5)
4).

When the slave processor receives the time setting request message sent from the time master (step ST60), the processor 21
The time setting request check means indicated by a ... 21n checks the compulsory setting flag in the message (step ST
61) If the compulsory setting flag is "compulsory setting", the designated time is set in the internal clock means (step ST62). If the forced setting flag is set to "not forcibly set", the internal clock means is read and compared with the time information in the message (step ST63). If there is an abnormal time difference in this comparison result for a certain period of time (a value determined by the performance of the clock means or the communication delay of the network and stored in the non-volatile memory by a setting tool, etc.), the time master It is determined that the clock means is abnormal, and a time setting request rejection message is transmitted to the time master (step ST65).

Even when there is an abnormality in the clock means of the processor that is the time master, the time setting request message is transmitted, but the time master returns a certain number or more of rejection response messages in steps ST52 and ST53. When it is determined that the clock has not arrived, it is determined that the clock means of the processor itself is normal, the force setting flag is set to "force setting" in step ST54, and the time setting request message is broadcast again to the network 9.

As described above, in this embodiment, the time master first broadcasts a time setting request message with the compulsory setting flag set to "not forcibly set" to the network 9. In the slave processor, the compulsory setting flag in the time setting request message sent from the time master is "not compulsory", so check the time difference between the internal time and the specified time in the message. , If the time difference exceeds a certain value, a time setting request rejection message is returned. If there is a certain number or less of rejection responses that are this time setting request rejection message, the time setting request message is broadcast again to the network 9 with the force setting flag set to "force setting" again. As a result, if the time master tries to set a time with no continuity, all other processors will return a reject message, and the time with no continuity cannot be set.

Example 3. The third embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a block diagram showing one of a plurality of processors connected to the network for explaining the time management system device of the third embodiment. In FIG. 10, parts that are the same as or correspond to those in FIG. Only the processor 11a of the plurality of processors connected to the network 9 is shown in FIG. In the figure, 31 is an external clock device that measures the time outside the processor 11a, 32 is host software, and 33 is an external clock device 3.
1 or a time setting interface means (interface means) for transmitting a time setting request from the upper software 32 to the time synchronizing means 17a, and 34 is an external time synchronizing control means.

Next, the operation will be described. FIG. 11 is a flow chart showing the external time synchronization control processing operation by the external time synchronization control means 34 of the time management system device of this embodiment, and the master arbitration processing of the master management means 12a is the same as in the second embodiment. Therefore, the description is omitted. In this embodiment, when the time setting interface means 33 receives a time setting request from the external clock device 31 or the host software 32, the time setting request is transmitted to the time synchronizing means 17a and the external time synchronizing control means 34. The time synchronization means 17a receives the time setting request from the time setting interface means 33 (step ST
70), it is judged whether or not the own processor is the time master (step ST71), and if it is the time master, the compulsory setting flag is set to "compulsory setting", and the external time synchronization control means 34 sends a time setting request message to the network 9. Is broadcast (step ST72). In this case, the operation of the time synchronizing means 17a and other components are the same as those in the second embodiment, and therefore their explanations are omitted.

In the second embodiment, the time master first broadcasts a time setting request message with the compulsory setting flag set to "not forcibly set" to the network 9. A time setting request message is broadcast to the network 9 with the setting flag set to “force setting”. On the other hand, in the slave processor, if the compulsory setting flag in the time setting request message sent from the time master is "not forcibly set", the time difference between the internal time and the specified time in the message is set. Check it and return a time setting request rejection message if there is a certain time difference. As a result, when the time master tries to set a time with no continuity, all other processors return a reject message, and a time with no continuity cannot be set. When there is a time setting request through the setting interface unit 33, the time master broadcasts a time setting request message in which the compulsory setting flag is set to “force setting” from the beginning, so that the time master sets even a non-continuous time. it can.

Further, the time setting interface means 33
On the other hand, “check time continuity” or “do not check time continuity” for checking whether the set time from the external clock device 31 has continuity with the internal time.
The time setting request may be disregarded when an abnormal time is input from the external timepiece device by providing a flag indicating "and checking the time continuity".

Example 4. Embodiment 4 of the present invention will be described below with reference to the drawings. FIG. 12 is a block diagram showing a configuration of a processor which is a gateway connected between two networks for explaining the time management system device of the fourth embodiment. FIG. 13 and FIG. 14 are system configuration diagrams showing a processor which is the gateway and a plurality of processors which are connected to each network, which constitute the time management system device.

In FIG. 12, 9a and 9b are two different networks, 41 is a processor, 42 is clock means for measuring the internal time of each processor, and 43 and 44.
Is a "master capable" set for each network
Alternatively, a master flag indicating either "slave",
45 and 46 are first master priority levels that are initially set for each network, and 47 and 48 are initially set in each of the three levels of high / middle / low levels for each network, and the second master priority that can be changed online. Ranks, 49 and 50 are master management means for determining the only time master based on the master first priority order and the master second priority order among the processors whose master flag is set to "masterable", 51.
Is a time synchronization means, 52 and 53 are each network 9
Time setting request receiving means for receiving a time setting request message from the time masters on a and 9b, and 54 is a time setting means for setting the time to the internal clock means 42 when the time setting request message is received.

Further, 41a in FIGS.
To 41g are processors, and particularly 41d is a processor which serves as a gateway between the two networks 9a and 9b.

Next, the operation will be described with reference to FIGS. The operation of the master managing means is almost the same as that of the first embodiment, and therefore its explanation is omitted. Of the processors shown in FIGS. 13 and 14, the master flag of the processor which is the candidate for the time master, that is, the master flag 4 for the processor 41 shown in FIG.
3, 44 are set to “master possible”. However, in the processor acting as a gateway, that is, the processor 41d in FIGS. 13 and 14, the master flag for one network 9a is the slave and the other network 9 is the master flag.
The master flag for b is set to "masterable". Further, for the processor whose master flag is set to "masterable", the master first priority order is initially set to a different priority value for each processor on each network. Further, the master second priority is initially set to the intermediate level. However, for the processor 41d serving as a gateway, the master second priority is set to a high level for the network 9b in which the master flag is set to "master possible".

By performing the initial setting in this way, FIG.
As shown in FIG.
The other processors 41a are time masters, and the processor 41d, which is a gateway on the network 9b, is the time master, and time information can be sent from the network 9a to the network 9b.

Further, the processor 41 serving as a gateway
In d, when the time setting request message is received from the time master processor 41a on the network 9a which is the slave (step ST80), the processor 41
For network 9b where d is the time master,
A time setting request message including the received time information is broadcast (step ST81). In addition, the master management means of the processor 41d monitors whether or not a master notification message is transmitted from the time master processor 41a on the slave network 9a within a fixed time (step ST82, step S82).
T83), when it is not transmitted within a fixed time, it is determined that the time master has disappeared, the master flag for the network 9a that has been a slave is changed to "master possible" (step ST84), and the master for the network 9b is set. The master is re-arbitrated after the second priority is set to the intermediate level (step ST85).

As a result, the network 9 in which the processor 41d serving as a gateway has been the time master until now.
On b, another processor 41f serves as a time master as shown in FIG. 14, and the time information can be sent from the network 9b to the network 9a using the processor 41d as a gateway.

Example 5. Embodiment 5 of the present invention will be described below with reference to the drawings. FIG. 17 is a block diagram showing one of a plurality of processors connected to the network for explaining the time management system device of the fifth embodiment. In the figure, 62 is a time synchronization means (time synchronization control means) for controlling whether or not the processor receiving the time setting request message synchronizes the time of the internal clock means with the designated time, and 63 is the time synchronization control means 62. It is a time synchronization control function selecting means for selecting a function and is controlled by the upper software 66. Reference numeral 64 is a time setting request receiving means for receiving the time setting request message and passing it to the time synchronization control means 62, and notifying the upper software 66 of the time setting request receiving event, and 65 is a master time reading means for reading the reference time from the hour master, 67 is a time setting means for setting the time in the clock means 42.

Next, the operation will be described. FIG. 18 is a flowchart showing the time setting processing operation in the time management system device of this embodiment. When the time setting request receiving means 64 receives the time setting request message (step ST90), it notifies the upper software 66 of the time setting request receiving event (step ST91). When the time setting request message of the time master is received from the host software 66 via the time synchronization control function selecting means 63 to the time synchronization controlling means 62, the designated time in the message is set in the internal clock means 42. It is possible to select "Yes" or "Not set", and the time synchronization control means 62 judges "Set" or "Not set" according to the selection (step ST92), and if "Set". The designated time is set in the internal clock means 42 (step ST93).

Further, the clock means of the time master can be read from the upper software 66 through the master time reading means 65 and set in the clock means 42 through the time setting means 67.

Therefore, according to this embodiment, even if the higher-order software receives the time setting request message while using the time of the internal clock means, the higher-order software receives the time synchronization control function selecting means 63. The internal clock means 42 for setting the designated time in the time setting request message.
You can select “Set” or “Not set” to the above, and when it adversely affects the higher-level software that uses the time, delay the timing of setting the reference time of the time master and It can be avoided.

[0060]

As described above, according to the first aspect of the present invention, the master second of each processor set to "masterable"
Master priority changing means for changing the priority online from an arbitrary processor, and only one among the processors set to "masterable" based on the master first priority and the master second priority of each processor. Of the time master, and when the master second priority is changed by the master priority changing means, the master first
Since the master management unit reselects the time master based on the priority order and the changed and newly set master second priority order, the priority order is different from that at the time of system startup changed online. There is an effect that a time management system device capable of selecting a new processor as a time master depending on the rank is obtained.

According to the invention of claim 2, high / medium / low 3
A master second priority set by a value in a range of stages,
Master priority changing means for changing the master second priority of each processor set to "masterable" online from an arbitrary processor; and a master priority of each processor among the processors set to "masterable" Only one time master is selected based on one priority and the master second priority, and when the master second priority is changed by the master priority changing means, the master first priority is selected. Since it is configured to include a master management unit that re-selects the time master based on the rank and the changed and newly set master second priority,
There is an effect that a time management system device can be obtained in which a new processor can be selected as a time master with a priority different from that at the time of system startup changed online.

According to the third aspect of the present invention, it is monitored whether or not the master notification message is transmitted within a fixed time on the condition that the own processor is not the time master, and when it is not transmitted, "master is possible". A certain time elapses when a time setting request message having a master management means for re-selecting a new time master from among the processors set to "1" and a time setting request flag indicating "not forcibly set" is broadcast. It is judged whether a time setting request reject message is sent from a certain number or more of processors on the network, until the master second priority of the time master processor is set to the lowest level before Reselect, or set the compulsory setting flag to "compulsory setting" and then repeat the time setting request message. Since it is configured to include a time synchronization control unit that executes the broadcast of the message, when an abnormality occurs in the time master and the master notification message cannot be broadcast, or when an abnormality occurs in the clock unit in the time master. Is the time at which a new time master can be re-selected from another processor that is set to "master enabled", and an accurate reference time by the re-selected time master can be stably supplied without stopping the system. The management system device can be obtained.

According to the fourth aspect of the present invention, when the time setting is requested through the interface means provided in each processor that interfaces with the host application or the external clock device, the "forced setting" is performed. Since the external time synchronization control means for broadcasting the time setting request message having the compulsory setting flag is provided, it is possible to set the time in the network even in the case of non-continuous time in addition to the effect of the second aspect. The time management system device is effective.

According to the fifth aspect of the present invention, a master flag indicating "masterable" or "slave" that can be set for each network and can be changed online, and set for each network The possible master first priority and master second priority, and the processor that serves as a gateway between the networks, sets the master flag to "slave" for one network and "master" for the other network. For the network that is set to "possible" and set to "master possible", the master first priority and the master second
By setting the priority to a higher value than other networks, the reference time of the other network becomes the reference time of one network, and the time master disappears for the network where the gateway processor is the slave. In this case, after changing the master flag of the network to "master possible", and changing the master second priority to the intermediate level for the network where the gateway processor has been the time master until then. Since it is configured to have a master management means for reselecting the time master,
When all the time masters on a certain network disappear, a new time master can be selected from the master candidates on other networks, and a time management system device that can allocate the time master candidates to a plurality of networks is provided. There is an effect obtained.

According to the sixth aspect of the present invention, it is controlled whether or not the processor that receives the time setting request message synchronizes the time information in the time setting request message and the time by the clock means in its own processor. Since the time synchronization control means and the time synchronization control function selection means for selecting control by the time synchronization control means are provided, and the time synchronization control function selection means is configured to be controlled by the host software, the higher software is When the time by the clock means in the processor itself is being used, the synchronization of the time can be made to wait, and the time synchronization has a discontinuity that affects the operation of the higher-level software. There is an effect that a time management system device capable of avoiding the above is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a time management system device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a master arbitration processing operation in the time management system device according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing an output processing operation of a time setting request message in the time management system device according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a time information setting processing operation in the time management system device according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a time management system device according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing a master notification message output processing operation in the time management system device according to the second embodiment of the present invention.

FIG. 7 is a flowchart showing a time master re-arbitration start processing operation in the time management system device according to the second embodiment of the present invention.

FIG. 8 is a flowchart showing a time synchronization control processing operation in the time management system device according to the second embodiment of the present invention.

FIG. 9 is a flowchart showing a time synchronization processing operation on the slave side in the time management system device according to the second embodiment of the present invention.

FIG. 10 is a block diagram showing one of a plurality of processors connected to a network for explaining a time management system device according to a third embodiment of the present invention.

FIG. 11 is a flowchart showing an external time synchronization control processing operation of the time management system device according to the third embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a processor serving as a gateway connected between two networks for explaining a time management system device according to a fourth embodiment of the present invention.

FIG. 13 is a network configuration diagram including a processor serving as a gateway connected between two networks for explaining a time management system device according to a fourth embodiment of the present invention.

FIG. 14 is a network configuration diagram including a processor serving as a gateway connected between two networks for explaining a time management system device according to a fourth embodiment of the present invention.

FIG. 15 is a flowchart showing a time setting request message output processing operation in the time management system device according to the fourth embodiment of the present invention.

FIG. 16 is a flowchart showing a master re-arbitration processing operation in the time management system device according to the fourth embodiment of the present invention.

FIG. 17 is a block diagram showing one of a plurality of processors connected to a network for explaining a time management system device according to a fifth embodiment of the present invention.

FIG. 18 is a flowchart showing a time setting processing operation in the time management system device according to the fifth embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of a conventional time management system device.

FIG. 20 is a flowchart showing a time synchronization processing operation in a conventional time management system device.

FIG. 21 is a flowchart showing a master notification message output processing operation in a conventional time management system device.

FIG. 22 is a flowchart showing a master re-arbitration start processing operation in a conventional time management system device.

FIG. 23 is a flowchart showing a master rearbitration processing operation in the conventional time management system device.

[Explanation of symbols]

9 networks, 10a ... 10n processors, 11
a ... 11n, 42 clock means, 12a ... 12n, 49,
50 master management means, 13a ... 13n, 43, 44
Master flag, 14a ... 14n, 45, 46 Master first priority, 15a ... 15n, 47, 48 Master second
Priority, 16a ... 16n Master priority changing means,
17a ... 17n, 62 time synchronization means (time synchronization control means), 18a ... 18n, 64 time setting request receiving means,
19a ... 19n, 67 time setting means, 21a ... 21n
Time setting request check means, 31 external clock device, 3
2, 66 host software, 33 time setting interface means (interface means), 34 external time synchronization control means, 63 time synchronization control function selection means.

Claims (6)

[Claims] 1. A time management system apparatus configured on a multiprocessor system composed of a plurality of processors connected by a network, for reading out set clock means to synchronize the time between the respective processors, wherein A master flag for setting either "master possible" or "slave", a master first priority set to a different value for each processor, and a master second that can be changed online. A priority setting and a time setting means for receiving a time setting request message periodically sent from the processor that is the time master, and setting the time in the time setting request message in the clock means of the own processor, Is the master second priority of each processor set to "masterable" any processor? And a master priority changing means for changing the master priority, and only one time master is selected based on the master first priority and the master second priority of each processor among the processors set to “master enabled”. When the master second priority is changed by the master priority changing means, based on the master first priority and the changed and newly set master second priority,
A time management system device comprising: master management means for re-selecting a time master in a priority order different from that at system startup. 2. The time management system apparatus according to claim 1, wherein the master second priority is set with a value in a three-step range of high / medium / low. 3. A master notification message is periodically broadcast to the network on condition that the own processor is the time master, or a master notification message is transmitted within a fixed time on condition that the own processor is not the time master. The master management means that monitors whether or not it comes and if it does not send it, re-selects a new time master from among the processors that are set to "master possible", and the time that the processor that is the time master regularly sends. A flag provided in the setting request message. Whether or not a processor other than the time master receiving the time setting request message forcibly sets the time information in the time setting request message to the clock means in its own processor. And a forced setting flag indicating that If the compulsory setting flag indicates “forcibly set” when the request message is received, the time information in the time setting request message is set to the clock means of the own processor, and the compulsory setting flag is set. If “not forcibly set” is indicated, the time of the clock means of its own processor is compared with the time information, and when the time difference is a fixed time, a time setting request reject message is transmitted to the time master. At first, the time means broadcasts a time setting request message having a compulsory setting flag indicating that the time master does not forcibly set the time, and the time is transmitted from a certain number or more processors on the network until a certain time elapses. When the setting request reject message is sent, the master second priority of the time master processor is set to the lowest. After re-selecting the time master after setting the bell, and when the number of time setting request rejection messages sent from the processors on the network is less than a certain number until the above-mentioned certain time elapses, request from multiple processors. 3. The time management system apparatus according to claim 2, further comprising: time synchronization control means for setting the forcible setting flag to “forcibly set” as being permitted and again broadcasting the time setting request message. . 4. Interface means provided in each processor for interfacing with a higher-level application or an external clock device, and said force indicating "forced setting" when time setting is requested via the interface means. 4. The time management system apparatus according to claim 1, further comprising: an external time synchronization control unit that broadcasts a time setting request message having a setting flag. 5. A multiprocessor system comprising a plurality of processors connected by a network and a processor acting as a gateway between the networks, which can be set in the processor for each network and can be changed online. A master flag indicating “master possible” or “slave” which can be set, a master first priority order and a master second priority order that can be set for each network, and a gateway serving as a gateway between the networks. In the processor, the master flag is "slave" for one network,
Set "masterable" for the other network, and set the master first priority and master second priority to higher values than other networks for the network set to "masterable" By doing
When the reference time of one network is set as the reference time of the other network, and when it is detected that the time master has disappeared for the network in which the processor serving as the gateway is the slave, the master flag is set to “master” for the network. Master management that reselects the time master after changing the setting of the master second priority to the intermediate level for the network in which the processor as the gateway has been the time master until then. The time management system apparatus according to claim 1 or 2, further comprising: means. 6. A time synchronization control means for controlling whether or not the time information in the time setting request message and the time by the clock means in its own processor are synchronized in the processor which has received the time setting request message,
Time synchronization control function selection means for selecting control by the time synchronization control means, upper software for controlling the time synchronization control function selection means, and time setting request reception to the higher software when the time setting request message is received 3. The time setting request receiving means for notifying an event, and the time setting means for setting the reference time of the time master read from the higher-level software to the clock means of its own processor, according to claim 1 or 2. Time management system device.