JPH08328034A - Liquid crystal light valve and projection type liquid crystal display formed by using the same - Google Patents

Abstract

PURPOSE: To provide a liquid crystal light valve for a projection type display which has light shielding performance to withstand irradiation with several million lux and displays image with high fineness and high quality. CONSTITUTION: Pixel circuit regions 101 arranged with plural switching elements 10la in a matrix form, driving circuit regions l02 arranged with driving circuit elements l02a and periphery regions are formed on the surface of a semiconductor substrate 100 and metallic layers 140, 160, 180 are disposed via insulating layers thereon. Reflection electrodes 181 to be formed as the output ends of the switching elements 101a are segmented by slits and are arranged on the metallic layer 180 of the uppermost part. Liquid crystals 200 are packed between transparent electrodes 302 which are formed on a glass substrate 302 and face the reflection electrodes 181 and the semiconductor substrate 100. Light shielding layers 163 of the pixel circuit regions 101 for shutting off the incident light from the slits 181 and light shielding layers for shutting off the irradiation of the peripheral regions and the driving circuit regions 102 are formed on the metallic layer 160.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display in which the intensity of light is controlled by the amplitude value of a voltage, and more particularly to a liquid crystal light valve suitable for a projection type display.

[0002]

2. Description of the Related Art A liquid crystal display using an active matrix system in which a switching element and a liquid crystal are laminated to control light is disclosed in US Pat. No. 3,862,360 and IE80-81 of IEICE Technical Report (1980). Has been done. All of these displays are of a direct view type in which an image controlled by a switching element is directly viewed. For the switching element, MO formed on a single crystal silicon substrate
An S (metal oxide-semiconductor) transistor is used.

When the MOS transistor is irradiated with light,
A photocurrent is generated at the PN junction forming the source and drain. When this photocurrent is generated in the switching element unit that controls the liquid crystal, the voltage applied to the liquid crystal changes and the image quality deteriorates. Furthermore, when a photocurrent flows through the switching element or a drive circuit section that controls the switching element, a phenomenon called latch-up is caused, a large current flows through the power supply, and circuit operation is hindered or the chip is broken.

FIG. 15 shows C for explaining the latch-up phenomenon.
The schematic diagram of MOSLSI is shown. PMO on the surface of n-type substrate
S and NMOS are formed in the p-well region. The substrate is VDD (for example, + 5V) through the n + diffusion layer, p
The well is connected to VSS (eg GND) via the p + diffusion layer.
Power to each. The sources of the PMOS and NMOS transistors are respectively connected to VDD and VSS, the gates are commonly connected to the input terminal Vin, and the drains are commonly connected to the output terminal Vout to form an inverter circuit.

In this CMOS LSI, parasitic bipolar transistors Tr1 and Tr2 and parasitic resistors R1 to R1 are used.
R4 can be done. Tr1 is an NMOS source for the emitter,
An npn transistor having a p-well as a base and a substrate as a collector, Tr2 is a PMOS source as an emitter,
It is a pnp transistor having a substrate as a base and a p-well as a collector. In addition, R1 and R2 are p wells, R3 and R
Reference numeral 4 is a resistance formed by the volume resistance of the substrate.

Parasitic bipolar transistors Tr1 and T
r2 has a thyristor structure as shown. When the voltage between the terminals is increased by the trigger current Ip flowing through the parasitic resistance R1 or R4, the parasitic npn or pnp bipolar transistor is turned on, the on-current flows through the parasitic resistance R1 or R4, and is rapidly increased to VDD and VSS. A large current flows between them, resulting in latch-up. This latch-up phenomenon may reduce the voltage inside the circuit to hinder the circuit operation, or may melt the wiring or the silicon substrate to destroy the chip.

The trigger current that causes latch-up is caused by light irradiation around the MOS transistor, in addition to power supply noise. Electrons or holes generated in the substrate due to light irradiation move to the PN junction between the high electric field substrate and the p well, and become a photocurrent Ip. The photocurrent Ip flows between the n + diffusion layer of the substrate and the p + diffusion layer of the p well and becomes a trigger current of the thyristor structure.

In the above technical report of the Institute of Electronics and Communication Engineers,
In order to reduce the photocurrent generated in the MOS transistor and prevent latch-up, the source region of the MOS transistor is arranged as far away from the light incident region as possible in the switching region of the semiconductor substrate, and the stopper diffusion for recombining the generated carriers is performed. It describes how to provide layers.

[0009]

A conventional liquid crystal display using MOS transistors is a direct-viewing type, and the light resistance required for a display panel is about tens of thousands of lux at most. However, in the projection type display, since the control image is enlarged and projected on the screen, the light emitted to the liquid crystal light valve becomes several million lux. Therefore, the conventional light shielding structure is not sufficient, and a structure in which the semiconductor substrate is completely covered by incident light is required. Furthermore, it is necessary to improve the light resistance of not only the switching area for controlling the image but also the drive circuit section and the like arranged in the peripheral area thereof.

In view of such a current situation, an object of the present invention is to
An object of the present invention is to provide a highly reliable liquid crystal light valve capable of preventing the latch-up by improving the light shielding property against strong irradiation light.

Another object of the present invention is to provide a projection type liquid crystal display which displays a high quality image with a brightness of about 5 million lux.

[0012]

A liquid crystal light valve that achieves the above-mentioned object of the present invention includes a pixel circuit region formed of a plurality of switching elements arranged in a matrix on one surface and an element for driving the switching element. A semiconductor substrate having a drive circuit region and peripheral regions thereof, a plurality of metal layers having wiring means hierarchically configured with an insulating layer on the one surface of the semiconductor substrate, and at the top. Formed by dividing the resulting metal layer with a slit,
A first reflective electrode that is an output end of the switching element, and a metal layer that is a lower layer of the uppermost portion, and is formed so as to overlap the plane space of the uppermost slit.
And a second light shielding means in which at least one of the metal layers is formed so as to cover the surface space of the drive circuit area and the peripheral area, and the reflective electrode is provided on the opposite surface to which light is irradiated. And a transparent counter substrate having a counter electrode facing each other, and a gap between the semiconductor substrate and the counter substrate filled with liquid crystal.

The metal layer is formed by providing a metal silicide layer such as WSi ₂ or MoSi ₂ on the upper surface and / or the lower surface of at least one layer.

Further, carrier absorption means is provided which is formed in the peripheral region of the pixel circuit region and the drive circuit region of the semiconductor substrate and absorbs carriers generated by light irradiation.

There is provided another electrode formed in an area corresponding to the peripheral region of the pixel circuit region at the uppermost portion, and means for keeping the counter electrode and the other electrode at the same voltage.

[0016]

The light-shielding means provided in the peripheral region, together with the reflective electrode, protects the pixel circuit region, the drive circuit region and the peripheral region thereof from the light of several million lux or its stray light.
It has a light resistance that almost completely reflects or absorbs light, can prevent a latch-up phenomenon occurring in a semiconductor substrate, and has an effect of preventing deterioration of image quality due to deterioration and damage of circuit elements. This reflection / absorption effect is further enhanced by the metal silicide layer.

Further, since the carrier absorption means provided in the peripheral region can absorb the carriers generated by the light reaching the semiconductor substrate, the photocurrent in the drive circuit region and its peripheral region can be greatly reduced, and the light shielding means can be provided. Combined with the light resistance.

Another electrode, which reflects light around the pixel circuit region, is set to the same potential as the counter electrode, that is, 0.
Since the brightness of the periphery of the screen can be reduced, the image quality can be improved.

Further, since the light shielding means can be formed over a plurality of metal layers, the semiconductor substrate can be made compact.

By applying such a liquid crystal light valve, up to about 5 million lux light source, high definition and bright,
It is possible to provide a projection display that displays a high quality image.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 9 shows a general circuit configuration of a liquid crystal light valve. The liquid crystal light valve includes a pixel circuit 1, a sample circuit 2, a horizontal scanning circuit 3, a vertical scanning circuit 4, and an AND gate 5. Each of these circuits is formed on the surface of the semiconductor substrate.

In the pixel circuit 1, M MOS transistors 1a and M storage capacitors 1b are arranged in the horizontal direction and N in the vertical direction. The scanning signals Vg1 to Vg from the AND gate 5 are applied to the gate electrode of the MOS transistor 1a.
The luminance signal V from the sample circuit 2 is applied to the N and drain electrodes.
One end of the storage capacitor 1b and the liquid crystal 1c are connected to the source electrodes d1 to VdM. The other end of the storage capacitor 1b is connected to the voltage VSS that supplies the substrate voltage via the light shielding layer.
The liquid crystal 1c is an equivalent capacitance of a liquid crystal element mounted between the pixel circuit 1 and the counter substrate.

The horizontal scanning circuit 3 receives the clock signal CLK and the start signal STA and receives the M-phase multiphase signal PH1.
~ Output PHM. The sample circuit 2 is composed of a MOS switch, and its gate electrode has the output signals PH1 to P1.
The HM and the drain electrode are connected to the video signal VI1 or VI2 having different polarities. Luminance signals Vd1 to VdM are output from the source electrode of the MOS switch.

The vertical scanning circuit 4 receives the clock signal CKV and the start signal FST and inputs the N-phase multi-phase signal PV1.
~ PVN is output. The AND gate 5 inputs the multiphase signals PV1 to PVN and the control signal CNT and outputs the scanning signals Vg1 to VgN.

FIG. 10 shows a timing chart for explaining the operation of the liquid crystal light valve. The start signal FST of the vertical scanning circuit 4 indicates the head of the frame of the video to be displayed, and the clock signal CKV indicates the scanning line switching timing. The vertical scanning circuit 7 takes in the start signal FST at the rising timing of the clock signal CKV and outputs the multiphase signals PV1 to PVN. The AND gate 5 inputs the multiphase signals PV1 to PVN and the control signal CNT and outputs the scanning signals Vg1 to VgN of the pixel circuit 1. In the case of sequential scanning in which each line is scanned, by setting CNT to “H”, the scanning signals Vg1 to VgN are changed to the multiphase signals PV1 to PV1.
Pixel circuits 1 that are equal to PVN and are arranged in a matrix are sequentially selected in the vertical direction. Video signals VI1 and VI2
Is a signal that changes with the voltage COM of the counter electrode as a reference, the polarities of which are opposite to each other and inverted every frame.

Similar to the vertical scanning circuit 4, the horizontal scanning circuit 3 takes in the start signal STA indicating the beginning of the scanning line at the rising timing of the clock signal CLK and outputs the multiphase signals PH1 to PHM. The sample circuit 2 converts the video signals VI1 and VI2 into phase signals PH1 to PHM.
Are sequentially sampled at the timing of
Output VdM. The luminance signals Vd1 to VdM are input to the pixel circuits 1 arranged in a matrix for each column. At this time, since only the MOS transistors of the pixel circuit 1 in the row selected by the scanning signals Vg1 to VgN are turned on, the luminance signals Vd1 to VdM are written and held in the storage capacitor 1b of the pixel circuit in the selected row. To be done. Since the voltage held in the storage capacitor 1b is applied to the liquid crystal 1c, the liquid crystal light valve displays an image according to the image signals VI1 and VI2.

FIG. 11 shows an example of the configuration of the horizontal and vertical scanning circuits of the liquid crystal light valve. In the figure, when symbols not enclosed in parentheses are used, horizontal operation circuits are used, and when symbols in parentheses are used, vertical operation circuits are used. This circuit is composed of a D-type flip-flop FF, an inverter INV, and a level conversion circuit LS. Flip flop F
A shift register is configured by connecting F in series, and the horizontal scanning circuit has M stages and the vertical scanning circuit has N stages.

The level conversion circuit LS includes two PMOS transistors MP1 and MP2 whose sources are connected to VDD.
And two NMOS transistors MN1 and MN2 whose sources are connected to VSS, and a flip-flop FF.
The output of is connected to the gate of MP1 and is connected to the gate of MP2 in the opposite phase by the inverter INV.
The gates of MN1 and MN2 are connected to each other and M
It is also connected to the drains of N1 and MP1. Furthermore, MN2
And the drains of MP2 are connected to each other, and this connection point is used as the output PH (PV) of the scanning circuit.

With this configuration, when the output of the FF is "H", MP1 and MN2 are turned off, MP2 is turned on, and the output PH (PV) becomes VDD. On the other hand, the output of FF is "
When L (= GND) ”, MP1 and MN2 are on, MP
2 is turned off, and the output PH (PV) becomes VSS. In this way, the level conversion circuit LS outputs the signal of 0-VDD to V
Convert to SS-VDD signal. The level conversion circuit LS is composed of high-voltage CMOS transistors that operate with a VDD (+ 5V) -VSS (-15V) power supply, and FF and INV are low-voltage CMOS transistors that operate with a VDD (+ 5V) -0 power supply. I am configuring.

1A and 1B show the structure of a liquid crystal light valve according to an embodiment of the present invention. FIG. 1A is a sectional view taken along the line AA of the plan view, and FIG. 1B is a semiconductor viewed from the light irradiation direction. It is a top view of a substrate.

In the liquid crystal light valve of this embodiment, a semiconductor substrate 100 on which a pixel circuit and a driving circuit are formed, and a counter electrode made of a transparent conductive material such as ITO (Indium-tin-oxide) on the surface of a transparent glass substrate 301. The counter substrate 300 includes a counter substrate 300 and a sealing material 510 for filling the liquid crystal 200 between them and bonding the substrate 100 and the substrate 300 together.

Single crystal silicon substrate 1 of semiconductor substrate 100
On the surface of 10, the first metal layer 140,
Forming a second metal layer 160 and a third metal layer 180,
Pixel circuit region 101 in which a plurality of switching elements 101a formed by enhancement type NMOS transistors are arranged
And a drive circuit region 102 composed of a circuit element 102a such as an enhancement type NMOS or PMOS, and a wire bonding region 108. A sample circuit 2, a horizontal scanning circuit 3, a vertical scanning circuit 4 and an AND circuit 5 are formed in the drive circuit area 102.

In the pixel circuit region 101, the pixel electrode 181 and the second metal layer 16 formed on the third metal layer 180 are masked so as to mask the surface of the silicon substrate 110 from light irradiation.
The light shielding layers 163 formed to 0 are arranged so as to overlap each other. Further, a light shielding layer 191 formed on the third metal layer 180 is arranged on the surface of the drive circuit region 102 and the other peripheral portion of the silicon substrate 110. Light-shielding layers 163, 19
Reference numeral 1 denotes a pattern formed on the metal layer, which reflects or absorbs incident light to block light reaching the semiconductor elements constituting each circuit and the semiconductor substrate in the peripheral region thereof.

Next, the device structure of the liquid crystal light valve of this embodiment will be described in detail. FIG. 2 is a cross-sectional view showing a part of the pixel circuit area of the liquid crystal light valve. One pixel circuit 1 is a MOS formed by an enhancement type NMOS transistor on the surface of a single crystal silicon substrate 110.
It is composed of a transistor 1a, a MOS capacitor 1b, a reflective electrode, and the like.

The semiconductor substrate 100 has a MOS on one surface.
An n-type silicon substrate 111 that forms a source region and a drain region that form the transistor 1a and one electrode region of the storage capacitor 1b, a polysilicon layer 120 that is selectively formed on the substrate 111, and a polysilicon layer. 120
The first insulating layer 130 formed on the first insulating layer 1 and the first insulating layer 1
30 formed on the insulating layer 130 and penetrating the insulating layer 130.
The first metal layer 140 that contacts the surface of the type silicon substrate 111 and the polysilicon layer 120, and the first metal layer 1
A second insulating layer 150 formed on the second insulating layer 150, and a second metal layer 1 formed on the second insulating layer 150 and penetrating the insulating layer 150 and contacting the first metal layer 140.
60, a third insulating layer 170 formed on the second metal layer 160, and a second insulating layer 170 formed on the third insulating layer 170 and penetrating the insulating layer 170 to contact the second metal layer 160. It is composed of the third metal layer 180. First
The metal layer 140, the second metal layer 160, and the third metal layer 180 are formed of, for example, aluminum.

The pixel circuit area 101 includes an n-type substrate layer 111.
A p-type well layer 112, n + regions 113 and 116 formed on the surface of the p-type well layer 112, an n region 114,
It is composed of a p + region 117 and an element isolation region 118. In the unit pixel circuit indicated by the one-dot chain line, a pair of n
The + region 113 becomes the source region and the drain region of the MOS transistor 1a, respectively. The n region 114 serves as one electrode of the storage capacitor 1b. n + region 116 and n region 11
4, the p + region 117 and the p-type well layer 112 are electrically connected to each other.

The polysilicon layer 120 is selectively formed on the surface of the n-type silicon substrate 111 via the silicon oxide layer 115. Specifically, the MOS transistor 1
The gate electrode 123 of a is formed on the p-type well layer 112 between the pair of n + regions 113, and the other electrode 124 of the storage capacitor 1b.
Are formed on the n region 114. The storage capacitor 1b is formed by the n region 114, the polysilicon layer 124, and the silicon oxide layer 115 interposed therebetween.

The first metal layer 140 is divided into a plurality of parts by a slit 144, a wiring 141 connecting the MOS transistor 1a and the storage capacitor 1b, a drain wiring 142 of the MOS transistor 1a, and one electrode of the MOS capacitor 1b. A wiring 146 for supplying power to the p-type well layer 112 is configured.

The wiring 141 is a contact hole 131 provided in the first insulating layer 130 and one of the pair of n + regions 113 and the polysilicon layer 124, and the drain wiring 142 is a contact hole 131 provided in the first insulating layer 130. On the other side of the pair of n + regions 113, the power supply wiring 146 is a contact hole 131 formed in the first insulating layer 130 and is a MOS.
The n + region 116 connected to one electrode of the capacitor and the p + region 117 connected to the p-type well layer 112 are in contact with each other.

The second insulating layer 1 is formed on the first metal layer 140.
A second metal layer 160 on which a light shielding layer 163 and an intermediate electrode 164 are formed is provided via 50, and the third insulating layer 1 is formed thereon.
A third metal layer (wiring layer) 180 on which a pixel electrode (reflection electrode) 181 is formed is provided via 70. Shading layer 1
63 and the intermediate electrode 164 are separated by a slit 162, and the pixel electrodes are separated from each other by a slit 182. Shading layer 1
Reference numeral 63 is connected to the wiring 146 through the through hole 152 and supplies one voltage of the p-type well and the MOS capacitor. The wiring 141 is connected to the intermediate electrode 164 via the through hole 151 and further to the pixel electrode 181 via the through hole 171, and outputs the source voltage of the MOS transistor 1a to the pixel electrode 181.

The liquid crystal light valve configured as described above is of a reflection type in which strong light emitted from the glass substrate 300 side is reflected by the pixel electrode 181, and the intensity of this reflected light is controlled by the state of the liquid crystal 200. are doing. For example, when a polymer-dispersed liquid crystal is used as the liquid crystal 200, the liquid crystal 200 changes from the scattering state to the transparent state due to the output voltage of the pixel electrode 181, and the reflectance of each pixel is high when the liquid crystal 200 is in the transparent state and is in the scattering state. It becomes low when. In this way, an image is displayed by controlling the state change of the liquid crystal by the voltage of the pixel electrode 181.

Next, the shielding of the irradiation light will be described. A reflective electrode 181 formed of the uppermost third metal layer 180
Light incident from the inter-electrode slit 182 is blocked by the light shielding layer 163 formed of the second metal layer 160. That is, when viewed from the counter substrate 300 side, the third metal layer 1
80 and the slit 182 and the second metal layer 160
Since the slits 162 formed on the counter substrate 30 are offset from each other without overlapping each other, the counter substrate 30
Light entering from the 0 side is reflected by either the third metal layer or the second metal layer and does not reach the semiconductor substrate 110.

As described above, the direct light incident from the counter substrate 300 side can be almost completely blocked. By the way, in addition to the direct light along the normal line, a part of the light obliquely incident on the inter-electrode slit 182 and the light scattered at the non-flat portion of the light shielding layer 163 is included in the third insulation. It is reflected by the layer 170 and becomes stray light, which is reflected by the slit 164 of the second metal layer and the first metal layer.
Through the slit 144 of the metal layer of the semiconductor substrate 11
It may reach zero. The non-flat place of the light shielding layer 163 is determined by the plane pattern of the MOS transistor 1a, the MOS capacitor 1b, the first metal layer 140, and the like.

In this embodiment, the position of the inter-pixel slit 182 of the third metal layer 180 is arranged in correspondence with the flat position of the light shielding layer 163 formed of the second metal layer 160. Furthermore, at least one surface such as each surface of the first metal layer 140 and the second metal layer 160 and the lower surface of the third metal layer 180 has a reflectance of, for example, tungsten silicon (WSi) or molybdenum silicon (MoSi). It has a multi-layered structure of aluminum and a low material. Thereby, stray light reaching the semiconductor substrate 110 can be significantly reduced.

FIG. 3 is a sectional view including the pixel circuit and the peripheral portion of the liquid crystal light valve of this embodiment. Pixel circuit area 10
In No. 1, the p-type well layer 112 is formed on the n-type silicon substrate 111, and is provided therein. Pixel circuit area 101
A light shielding layer 165 formed of the second metal layer 160 is provided in the peripheral region of the third metal layer 18 which is the uppermost layer.
An electrode 183 electrically separated from the electrode 181 is formed by 0, and the same voltage as that of the counter electrode 302 is supplied to the electrode 183. As a result, the applied voltage of the liquid crystal facing the peripheral area of the pixel circuit is set to zero.

FIG. 4 is a sectional view of the drive circuit of this embodiment and its peripheral portion. PM on the surface of the n-type silicon substrate 111
An NMOS transistor is formed in each of the OS transistor and the p-type well layer 112, and these transistors are used to form a driving circuit such as the horizontal scanning circuit 3 and the vertical scanning circuit 4. A light-blocking layer 1 that blocks incident light from the counter substrate 300 side is formed on the drive circuit and the peripheral region thereof.
66 is provided by the second metal layer 160. In addition,
A light shielding layer may be provided by the other metal layer 140 or 180.

As described above, in the liquid crystal light valve of this embodiment, the light irradiating the pixel circuit region is protected by the light shielding layer 1.
At 63, the light emitted to the peripheral portion of the pixel circuit region is blocked by the light shielding layer 165, and the light emitted to the drive circuit region and its peripheral portion is blocked by the light shielding layer 166. According to this,
Even if a strong light is emitted like a projection type display,
Light incident on the silicon substrate is reliably blocked, latch-up can be prevented, and deterioration or destruction of the characteristics of the device can be avoided. Further, since the electrodes are provided above the pixel circuit peripheral portion so that the applied voltage of the liquid crystal facing the peripheral portion of the pixel circuit area becomes 0, the brightness of this portion is reduced to improve the image quality of the peripheral portion of the screen. Can be improved.

Next, a liquid crystal light valve according to a second embodiment of the present invention will be described. FIG. 5 is a plan view of the liquid crystal light valve, and FIG. 6 is a sectional view taken along line BB. The difference between this embodiment and the above-mentioned embodiments is that a carrier stopper layer is provided.

The carrier stopper layer serves as the pixel circuit region 10.
1 and the drive circuit region 102 are provided so as to surround them. Specifically, the n + region 191 provided on the surface of the n-type silicon substrate 110 and the p + region 19 provided on the p-type well layer 112.
2 and the maximum voltage (VDD) is applied to the n + region 191.
The minimum voltage (VSS) is supplied to the p + region 192.

According to this, the carriers generated by the light radiated to the periphery of the semiconductor substrate 100 are attracted to the carrier stopper region, and the n + region 191 to the p + region 19.
The photocurrent Ip flows in the direction of 2. As a result, photocurrent does not flow through the elements of the drive circuit, and latch-up can be prevented.

A liquid crystal light valve which is a modification of the second embodiment will be described with reference to the plan view of FIG. 7 and the sectional view of FIG. In this example, the carrier stopper layer is realized in the p-type well layer. Specifically, a p + region and an n region are provided in the p-type well layer 193 provided on the surface of the n-type silicon substrate 110, an n + region is further provided in the n region, and the p + region and the n + region are connected by the wiring 148. Connected.

According to this, the carriers generated by the light applied to the periphery of the semiconductor substrate 100 are the p-type well layer 19
It is converted into photocurrent Ip in the carrier stopper region of 3.
As a result, the photocurrent does not flow to the elements of the drive circuit,
Latch-up can be prevented.

Next, with respect to the mounting structure of the liquid crystal light valve described in each of the above embodiments, the plan view of FIG. 12 and FIG.
Will be described with reference to the sectional view of FIG.

The semiconductor substrate 100 on which the pixel circuit 1, the horizontal scanning circuit 3, the vertical scanning circuit 4 and the like are formed is adhered to the ceramic substrate 500 with the circuit portion facing upward with a conductive paste. Liquid crystal 200 is filled between the semiconductor substrate 100 and the counter substrate 300 provided so as to face the semiconductor substrate 100. The liquid crystal 200 is sealed by a sealing material 510 provided on the periphery of the liquid crystal 200, and is protected from humidity in the outside world. The counter electrode 302 provided on the surface of the counter substrate 300 and the wiring pattern such as the electrode 181 formed on the uppermost metal layer 180 of the semiconductor substrate 100 are connected using the conductive paste 530.

The signal terminal 550 of the counter substrate 300 is connected to the wiring pattern formed on the ceramic substrate by the wire bonding 520. The wire bonding position on the semiconductor substrate 100 and the counter electrode 302 on the surface of the counter substrate 300.
The area of the signal terminal portion of the semiconductor substrate 100 is made small by connecting only one side of the upper side portion of the substrate 100.

FIG. 14 is a schematic view showing the structure of a projection type display to which the above liquid crystal light valve is applied. The projection display includes a light source 700, a first lens 710,
It is composed of a mirror 720, a second lens 730, a liquid crystal light valve 740, a projection lens 750 and a screen 760.

The light from the light source 700 is emitted from the first lens 71.
0 is focused on the position of the mirror 720, and the first lens 73
When the light is 0, the light is collimated and the liquid crystal light valve 740 is illuminated. The liquid crystal light valve 740 controls the reflection state of the emitted light with a voltage applied to each liquid crystal pixel, and reflects the reflected light from the liquid crystal light valve to the second lens 730 and the projection lens 7.
An image is formed by enlarging and projecting on a screen 760 via the screen 50.

By splitting the light flux from the light source into three light fluxes of the three primary colors of light, providing a liquid crystal light valve for each light flux, and synthesizing and projecting the reflected light from the three liquid crystal light valves again and enlarging and projecting them. A projection display of color display can be obtained. The decomposition of light into the three primary colors and the synthesis of the reflected light from the three liquid crystal light valves can be performed simultaneously using, for example, a dichroic mirror.

In the projection type display, the light emitted to the liquid crystal light valve reaches several million lux, and the image quality is deteriorated due to the deterioration or destruction of the element due to the latch-up. However, according to the present embodiment, in the liquid crystal light valve, the light irradiation to the silicon substrate forming the image circuit area, the operation circuit area and the peripheral area is performed against the stray light due to the oblique incidence and the scattering of the metal wiring layer. Since a light-shielding means that can block even the
The light resistance could be improved up to 1 million lux. This has made it possible to put a projection type display using a liquid crystal light valve into practical use.

The liquid crystal light valve using the single crystal silicon substrate and the projection type display using the same have been described above. It goes without saying that the liquid crystal light valve of the present invention can be realized by using a substrate having a semiconductor layer formed on an insulating substrate, a compound semiconductor substrate, or the like instead of the silicon substrate.

[0062]

According to the liquid crystal light valve of the present invention, since the pixel circuit region, the drive circuit region, and the light shielding means for cutting off the light irradiation to the peripheral region thereof are provided, the photocurrent of the semiconductor substrate is reduced. Therefore, it is possible to prevent the occurrence of latch-up, prevent deterioration of the image quality due to deterioration or destruction of the element, and improve the saturation of the image.

Further, since a plurality of metal layers forming each circuit are used and a light shielding means is provided in the lower metal layer so as to mask a space that cannot be reflected by the wiring pattern of the upper reflective electrode, reliable light shielding is compact. There is an effect that can be realized.

Further, since the carrier stopper region for absorbing the carriers generated by light irradiation is provided in the peripheral region together with the light shielding layer for each circuit region, the photocurrent of the semiconductor substrate is greatly increased even when the irradiation light is strong. The effect is that the occurrence of latch-up can be reliably prevented by reducing the above.

According to the projection type display of the present invention, it is possible to apply a liquid crystal light valve that can withstand light irradiation of about 500 million lux, and it is possible to provide a high-luminance, high-definition enlarged screen.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional structure view of a liquid crystal light valve according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional structural diagram of a pixel circuit region of a liquid crystal light valve according to a first embodiment.

FIG. 3 is a sectional structural view of a pixel circuit and a peripheral region of a liquid crystal light valve according to a first embodiment.

FIG. 4 is a sectional structural view of a drive circuit region and a peripheral region of the semiconductor substrate according to the first embodiment.

FIG. 5 is a plan structural view of a drive circuit region and a peripheral region of a semiconductor substrate of a liquid crystal light valve according to a second embodiment of the present invention.

FIG. 6 is a sectional structural view of a drive circuit region and a peripheral region of a semiconductor substrate according to a second embodiment.

FIG. 7 is a plan structural view of a drive circuit region and a peripheral region of a semiconductor substrate according to a modified example of the second embodiment.

FIG. 8 is a sectional structural view of a drive circuit region and a peripheral region of a semiconductor substrate according to a modification of the second embodiment.

FIG. 9 is a circuit configuration diagram of a liquid crystal light valve.

FIG. 10 is a time chart showing a liquid crystal light valve operation.

FIG. 11 is a scanning circuit diagram of a liquid crystal light valve.

FIG. 12 is a plan view showing the mounting structure of the liquid crystal light valve of the present embodiment.

FIG. 13 is a side sectional view showing a mounting structure of the liquid crystal light valve of the present embodiment.

FIG. 14 is a schematic diagram illustrating the configuration of a projection display to which the liquid crystal light valve of the present invention is applied.

FIG. 15 is a schematic diagram illustrating a latch-up phenomenon of a parasitic bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pixel circuit, 1a ... MOS transistor, 1b ... Holding capacity, 1c ... Liquid crystal capacity, 2 ... Sample circuit, 3 ... Horizontal scanning circuit, 4 ... Vertical scanning circuit, 5 ... AND gate, 10
0 ... Semiconductor substrate, 101, 101a ... Pixel circuit region, 1
02, 102a ... Drive circuit area, 110 ... N-type silicon substrate, 112 ... P-type well layer, 120 ... Polysilicon layer, 130 ... First insulating layer, 131 ... Through hole, 1
40 ... 1st metal layer, 141, 142, 146 ... Wiring,
150 ... Second insulating layer, 151 ... Through hole, 160
... second metal layer, 163, 165, 166 ... light-shielding layer, 1
70 ... 3rd insulating layer, 171 ... Through hole, 180 ...
Third metal layer, 181 ... Pixel electrode (reflection electrode), 182
… Slits, 183 ... Other electrodes, 191,192,19
3 ... Carrier stopper part, 200 ... Liquid crystal, 300 ... Counter substrate, 302 ... Counter electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ichio Takemoto 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Device Division (72) Inventor Katsumi Matsumoto 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. Within

Claims (10)

[Claims] 1. A semiconductor substrate having, on one surface thereof, a pixel circuit region including a plurality of switching elements arranged in a matrix, a drive circuit region including an element for driving the switching element, and a peripheral region thereof, The switching element is formed on the one surface of the semiconductor substrate by forming a plurality of metal layers hierarchically configured with an insulating layer and having wiring means, and dividing the metal layer at the top by slits. A plurality of reflective electrodes which are output ends, a first light shielding means formed in the metal layer in the lower layer of the uppermost portion so as to overlap with the plane space of the uppermost slit, and the metal layer of Second light-shielding means, at least one of which is formed so as to cover the surface space of the drive circuit area and the peripheral area, and a surface opposite to the surface facing the light, facing the reflective electrode. A transparent opposing substrate having an electrode, a liquid crystal light valve formed by filling a liquid crystal into a gap of the semiconductor substrate and the counter substrate. 2. The liquid crystal light valve according to claim 1, wherein the first light shielding unit is arranged in a flat place where the metal unit does not compete with the wiring unit and the like. 3. The liquid crystal light valve according to claim 2, wherein the flat place where the first light shielding unit is arranged is secured by a plurality of metal layers. 4. The liquid crystal light valve according to claim 1, 2 or 3, wherein the metal layer is provided with a metal silicide layer such as WSi ₂ or MoSi ₂ on at least one upper surface and / or lower surface. 5. A semiconductor substrate having on one surface thereof a pixel circuit region including a plurality of switching elements arranged in a matrix and a drive circuit region including an element for driving the switching element, and the pixel on the semiconductor substrate. Carrier absorption means formed in a circuit region or a peripheral region of the drive circuit region for absorbing carriers generated by light irradiation, and wiring formed hierarchically on the one surface of the semiconductor substrate via an insulating layer. A plurality of metal layers having means, a plurality of reflective electrodes that are formed by dividing the uppermost metal layer by slits, and serve as output ends of the switching elements, and at least one metal in the lowermost layer of the uppermost layer. At least one of the metal layer and the first light shielding means formed in the layer so as to overlap with the plane space of the uppermost slit. A second light shielding means formed so as to cover a surface space of the circuit region and the peripheral region; a transparent counter substrate having a counter electrode facing the reflection electrode on a surface on the opposite side to which light is irradiated; A liquid crystal light valve in which a liquid crystal is filled in a gap between a substrate and the counter substrate. 6. The liquid crystal light valve according to claim 5, wherein the carrier absorbing means uses a well layer or a diffusion layer to which power is supplied. 7. The liquid crystal light valve according to claim 1, wherein the switching element is formed in a well, and the well is powered by a metal layer having the light shielding means. 8. A semiconductor substrate having, on one surface, a pixel circuit region including a plurality of switching elements arranged in a matrix, a drive circuit region including an element for driving the switching element, and a peripheral region thereof, On the one surface of the semiconductor substrate, a plurality of metal layers that are hierarchically configured through an insulating layer and have wiring means, and the metal layer at the top, and an area corresponding to the pixel circuit region is slit. A plurality of reflective electrodes that are formed separately and serve as output ends of the switching elements; another electrode that is formed in the area corresponding to the peripheral area of the pixel circuit area at the uppermost portion; At least one metal layer is formed so as to overlap the plane space of the uppermost slit, and at least one of the metal layers is driven by the drive circuit. A second light shielding means formed so as to cover the surface space of the region and the peripheral region; a transparent counter substrate having a counter electrode facing the reflection electrode on the surface opposite to the side irradiated with light; and the semiconductor substrate. And a liquid crystal filled in the gap between the counter substrate, and a means for keeping the counter electrode and the other electrode at the same voltage,
Liquid crystal light valve that is equipped with. 9. A light source, a liquid crystal light valve for controlling the reflection state of the radiated light by a voltage applied to a liquid crystal pixel, a screen for displaying an image, and the light from the light source for making the light into parallel light. A projection type display device comprising optical means for irradiating a bulb and enlarging and projecting the reflected light from the liquid crystal light bulb onto the screen, wherein the liquid crystal light bulb is according to any one of claims 1 to 8. A projection type liquid crystal display device, characterized by using the described liquid crystal light valve. 10. The projection type liquid crystal display device according to claim 9, wherein the brightness of the light source with which the liquid crystal light valve is irradiated reaches about 5 million lux.