JPH0832588A - Multiplexer circuit - Google Patents

Abstract

PURPOSE:To reduce the memory capacity of the entire multiplexer circuit. CONSTITUTION:With respect to a multiplexer circuit outputting input signals comprising n sets of input series with multiplexing for each information accommodation unit whose length is m, n-sets of data memories 131 to 134 storing the input signals of each input series are provided and k-th data memory (k is 1 to n) has a capacity of (1+k/n)Xm. Furthermore, the multiplexer is provided with n write address generating means 142 to 145 generating a write address signal for the capacity of corresponding data memory at all times, with n read address generating means 114 to 117 and 139 to 141 generating a read address signal by a capacity of the corresponding memory at a speed being a multiple of n of the write address signal and in which each generating period is a period decided to itself among n divisions of one period of the information accommodation unit equally divided and also with selection means 130, 140 selecting a signal read from each data memory synchronously with the read operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal multiplexing circuit, and is applied to, for example, a multiplexing circuit of an information accommodating unit (hereinafter referred to as a cell) in an asynchronous transfer mode network (hereinafter referred to as an ATM network). Is suitable.

[0002]

2. Description of the Related Art Conventionally, there is a cell multiplexing circuit shown in FIG. 2, which operates as shown in the time chart of FIG.

2 and 3 show a case where cells from four transmission lines HW1 to HW4 each having a transmission capacity of 150 Mb / s are multiplexed on a transmission line HW0 having a capacity of 600 Mb / s. In addition, the case where one cell is composed of 16 bytes is shown.

Data from the respective transmission lines HW1, ..., HW4 are respectively applied as input signals 200 to 203 to the corresponding data memories 221 to 224, temporarily stored therein, and then read from these data memories 221 to 224 at high speed. It is output, input to the selector circuit 227, selected by this selector circuit 227, converted into a multiplexed cell, and sent to the output transmission line HW0.

Each of the data memories 221, ..., 224 is a memory having two ports that can be independently accessed, and the memory capacity is a memory amount of two cells (32 bytes).

These data memories 221 to 224 include
A common write address counter 220 that operates in a binary system
The write address signal 204 is given from the input memory 2 and each of the data memories 221, ..., 224 receives the input signal 2 in the area indicated by the write address signal 204, as shown in FIG.
Write 00, ..., 203.

On the other hand, on the read side, in addition to the read address counter 225 and the selector circuit 227, a counter 228 for counting the length of one cell (16 bytes) and a value for instructing switching of the input transmission lines HW1 to HW4 are provided. The counter 226 to be created is provided in combination.
The read address counter 225 and the counter 228 are
It operates with a clock signal that is four times faster than the write address counter 220. For example, 1 cell (1
The carry signal of the counter 228 that counts the length of 6 bytes) is input as a clock signal to the counter 226 that creates a value instructing switching of the input transmission lines HW1 to HW4. The counter 226 is, for example, an octal counter (3-bit counter), and the lower 2 bits are given to the selector circuit 227 as a switching command, and the most significant bit of the counter 226 and the 4 bits of the counter 228, 5 bits in total,
Each time the value of the counter 226 changes, the read address counter 225 is preset.

That is, as shown in FIG. 3, the read address signal 209 from the read address counter 225.
Makes four cycles of "16" to "31" while the write address signal 204 changes from "0" to "15", and the write address signal 204 changes from "16" to "31". Four cycles of "0" to "15" are made between them.

In FIG. 3, the data memory 22
Each byte of the input signals 200 to 203 and the output signals 205 to 208 with respect to 1 to 224 is specified by its address. In other words, it can be said that FIG. 3 shows the write address signal 204 and the read address signal 209. This point is the same in FIG. 4 described later.

As a result, each data memory 221, ...
Although the same signal is read from the 224 at the same time four times, the selector circuit 227 determines whether any one of the data memories 221 and 221 is based on the count value of the counter 226.
... The signals from 224 are sequentially selected, and the selector circuit 22
As shown in FIG. 3, the signal sent from the output transmission line HW0 to the output transmission line HW0 is obtained by multiplexing the data from the input transmission lines HW1, ..., HW4.

[0011]

However, in the conventional multiplexing circuit, a data memory having a capacity of 2 cells per one input transmission line is required for multiplexing. In the above description, since each cell has 16 bytes, its memory capacity is at most 256 bits.
Actually, one cell is about 53 bytes, and in this case, the required capacity of one buffer memory increases to 848 bits. Moreover, since the buffer memory is required for the degree of multiplexing, the required memory capacity of the entire multiplexing circuit is considerably large.

As with other circuits, in the multiplexing circuit as well, the smaller the memory capacity, the better the size and the occupied area. Therefore, there is a demand for a multiplexing circuit having a small required memory capacity.

[0013]

In order to solve such a problem, in the present invention, a multiplexing circuit for multiplexing input signals from n input sequences for each information accommodating unit of length m and outputting The following means are provided.

That is, (1) n number of data memories corresponding to each input series for storing an input signal from each input series, where the k-th (k is 1 to n) data memory is (1+
(k / n) × m data memory with a 2-port configuration having a capacity of (2), and (2) a write address signal corresponding to the capacity of the corresponding data memory provided corresponding to each data memory is constantly generated. N write address generating means, and (3) a read address signal corresponding to the capacity of the corresponding data memory provided corresponding to each data memory is generated at a speed n times that of the write address signal. N read address generating means whose generation period is a 1 / n cycle period which is fixed to itself by dividing one cycle of the information accommodating unit into n equal parts, and (4) a signal read from each data memory. And a selecting means for selecting in synchronization with the reading operation.

Here, (1 + k) of the kth data memory
When the memory capacity determined by / n) × m is a decimal multiple of the access unit amount (for example, bytes), it is preferable to round the memory capacity up.

[0016]

In the present invention, basically, the input signals from the n input series are written in the data memory having the 2-port structure corresponding to each input series, and the next information accommodating unit (its length m) is written. The stored signal is read during the period when the input signal is being input, and the signals of the respective series that have been read are selected by the selection means to form a multiplexed signal.

Here, since the signal period of each series in the multiplexed signal is fixed, the data may be read from the data memory of each series only during that period. The area of the data memory whose reading has been completed can be immediately changed to the writing area.

Considering in this way, the inventor of the present invention has found that not all data memories need to have a memory capacity twice as large as the information accommodating unit, and a memory capacity smaller than this may be sufficient. Therefore, the k-th (k is 1 to n) data memory has a memory capacity of (1 + k / n) ×
It was decided to apply m. In accordance with the selection of the capacity, the write address generating means corresponding to each data memory always generates the write address signal corresponding to the capacity of the corresponding data memory, and the read address generation corresponding to each data memory. The means determines the read address signal corresponding to the capacity of the corresponding data memory at a speed n times as fast as the write address signal, and moreover, is determined by dividing the cycle of the information accommodating unit into n equal parts.
It was set to occur in n cycle periods.

When the length m of the information storage unit is not an integral multiple of the multiplicity n, (1 + k / n) × m is a decimal multiple of the access unit amount (byte or bit) of the data memory. However, in this case, the memory capacity may be set to a value obtained by rounding up the decimal.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multiplexing circuit according to the present invention will be described in detail below with reference to the drawings. Here, FIG. 1 is a block diagram showing a configuration of the multiplexing circuit of this embodiment, and FIG. 4 is a timing chart of each part thereof.

This embodiment also has four input transmission lines HW1 to HW1.
Output signal HW0 by multiplexing signals (cells) from HW4
The cell on the input side has 16 bytes. Further, it is an example of a circuit that processes an input and an output in parallel with 8 bits (1 byte).

In FIG. 1, this multiplexer circuit stores four input cell signals 101 to 104, respectively, and reads out and outputs the stored cell signals.
1-134, write address counters 142-145 for generating write address signals for the corresponding data memories 131-134, and corresponding data memories 131.
˜134, read address counters 135 to 138 for generating read address signals, and output cell signal 106 read from the four data memories 131 to 134.
A selector circuit 130 for selecting any of
A counter 139 that counts the signal cycle of the output cell signal from the same input transmission path in byte units, and a counter 14 that forms information defining the input transmission path of the signal selected by the selector circuit 130 together with the output of the counter 139.
0, and a decode circuit 141 that forms period information (enable signal) that allows the read address counters 135 to 138 to perform a count operation based on the output from the counter 140.
It consists of and.

In the case of this embodiment, unlike the conventional circuit, each data memory 131, ..., 134 has a different memory capacity. That is, the data memory 131 has 2
The data memory 132 has a capacity of 24 bytes, the data memory 133 has a capacity of 28 bytes, and the data memory 134 has a capacity of 32 bytes.

The count value cycles of the write address counters 142 to 145 and the read address counters 135 to 138 are selected according to the memory capacity of the corresponding data memories 131 to 134.

That is, a 20-base counter is applied as the write address counter 142 and the read address counter 135 of the data memory 131, and a 24-base counter is used as the write address counter 143 and the read address counter 136 of the data memory 132. A 28-ary counter is applied as the write address counter 144 and the read address counter 137 related to the data memory 133, and a 32-ary counter is applied as the write address counter 145 and the read address counter 138 related to the data memory 134.

The frequency of the count-up clock signal of the read address counters 135 to 138 is selected to be 4 times the multiplicity of the frequency of the count-up clock signal of the write address counters 142 to 145. Further, each read address counter 135, ..., 1
38 includes decode circuits 141 to 1 as described later.
117 are provided to indicate that the counting operation is allowed only for / 4 cell period, and the significant period of each enable signal 114, ..., 117 is shifted by 1/4 cell period. .

That is, in this embodiment, for each of the data memories 131, ..., 134, the cell signals 101, ..., 1 from the corresponding input transmission lines HW1 ,.
04 is always written and read only once in one cell period in a ¼ cell period.

Here, the memory capacity of the data memory 131 is set to 20 bytes, which means that the memory capacity of the immediately preceding cell for reading is 16 bytes.
Byte data can be stored, and 4 that were input during the 1/4 cell period that is reading the 16-byte data.
This is because byte data is also stored regardless of the read area. The memory capacity of the data memory 132 is set to 24 bytes because the reading from the data memory 132 is executed after the reading from the data memory 131.
This is because the 16-byte data of the immediately preceding cell can be stored, and the 8-byte data input during the 1/2 cell period during which the data memories 131 and 132 are reading are also stored independently of the read area. The memory capacities of the data memories 133 and 134 are 28 bytes and 32 bytes, respectively, for the same reason.

That is, even if the memory capacity is minimized, the memory capacity of each of the data memories 131, ..., 134 is required to be 20 bytes, 24 bytes, 28 bytes, and 32 bytes from the above viewpoint.

The counter 139 is a hexadecimal counter,
The same high-speed clock signal as that supplied to the read address counters 135 to 138 is input to perform a counting operation,
As described above, a value obtained by counting the signal cycle of an output cell signal from a certain input transmission path in byte units is output. In other words, the counter 139 outputs a value indicating what number byte data is in one cell (1/4 cell period) after multiplexing.

The counter 140 is a quaternary counter, and when it is given to the write address counters 142 to 145, the same low-speed clock signal is input to perform a counting operation, or the carry signal of the counter 139 is given as a clock signal to count. It operates to form the information defining the input transmission path of the signal selected by the selector circuit 130 as described above. In other words, the counter 140 outputs a value indicating a cell after being multiplexed and a cell delimiter.

The selector circuit 130, based on the count value (data selection signal) 118 from the counter 140,
Of the data memories 131 to 134, a read signal (a signal from a predetermined input transmission path) from the data memory during the read operation is selected and is output as the cell multiplexed signal 105 on the transmission path H.
Send to W0.

The decoding circuit 141, based on the count value (data selection signal) 118 from the counter 140,
The enable signal is output to the read address counter for the data memory associated with the input transmission path indicated by the count value.

The operation of the multiplexing circuit of the embodiment constructed by the above-mentioned respective parts will be described with reference to the timing chart of FIG.

At time t1, it is assumed that the write address signals from all the write address counters 142 to 145 are "0", and at this time t1, the cell signals 101, ... Road HW1,
..., corresponding data memory 131 from HW4, ..., 13
4 is given.

First, the access operation to the data memory 131 related to the input transmission line HW1 will be described.

The byte data of the first cell (hereinafter referred to as cell 1; the same applies to the following cells) from time t1 is stored in the data memory 131 based on the write address signal 120 from the write address counter 142. It is sequentially stored in the addresses "0" to "15".

From the time t2 when the byte data of the next cell 2 starts to be input, the enable signal 114 given to the read address counter 135 becomes significant, and then 1
The / 4 cell period t2 to t3 continues to be significant, and counts up based on the high-speed clock signal during this significant period. Therefore, the read address counter 13
The read address signal 110 from 5 is during this period t2.
It changes from “0” to “15” at t3, each byte data 106 of the cell 1 is read from the data memory 131, selected by the selector circuit 130, and sent to the output transmission line HW0 as the multiplexed signal 105. Writing is performed even during such reading, and at this time, the read address "0" to
Write address "16" to "19" different from "15"
Is performed on The byte data of the cell 2 continues even after the reading is completed at the time point t3, and these byte data are stored in the address "0" of the data memory 131 based on the write address signal 120 from the write address counter 142 in decimal. To “11” are sequentially stored.
That is, each byte data of the cell 2 is stored in the data memory 1
31 addresses "16" to "19" and "0" to "1"
1 "area is sequentially written.

From the time point t6 when the byte data of the next cell 3 starts to be input, the enable signal 114 given to the read address counter 135 becomes significant again, and thereafter, the quarter cell period t6 to t7 continues to be significant. .
Therefore, the read address signal 110 from the read address counter 135 in the 20-ary system changes between "16" to "19" and "0" to "11" during this period t6 to t7, and each byte data 106 of the cell 2 is changed. It is read from the data memory 131, selected by the selector circuit 130, and sent as the multiplexed signal 105 to the output transmission line HW0. Writing is performed even during such reading, and at this time, writing addresses "12" to "15" different from the reading addresses "16" to "19" and "0" to "11" are performed. Be done. The byte data of the cell 3 continues even after the reading is completed at the time point t7, and these byte data are based on the write address signal 120 from the write address counter 142 in the decimal system and the address “16” of the data memory 131. To "19" and "0" to "7" are sequentially stored. Hereinafter, the same process is repeated.

Next, an access operation to the data memory 132 related to the input transmission line HW2 will be described.

The byte data of cell 1 from time t1 is
Based on the write address signal 121 from the write address counter 143, the data is sequentially stored in the areas of addresses “0” to “15” of the data memory 132.

The enable signal 115 given from the decode circuit 141 to the read address counter 136 becomes significant from the time point t3 delayed by 1/4 cell period t2 to t3 from the time point t2 when the byte data of the next cell 2 starts to be input. After that, the 1/4 cell period t3 to t4 continues to be significant, and the count-up is performed based on the high-speed clock signal in this significant period. Therefore, the read address signal 111 from the read address counter 136
Changes from "0" to "15" during this period t3 to t4,
Each byte data 107 of the cell 1 is read from the data memory 132, selected by the selector circuit 130, and transmitted as the multiplexed signal 105 to the output transmission line HW0.

¼ cell period t2 to t3 before this read
The byte data of the cell 2 input in (in other words, the reading period of the data memory 131) is based on the write address signal 121 from the write address counter 143 in the hexadecimal notation, from the address “16” of the data memory 132.
The byte data of the cell 2 sequentially stored in the area “19” and input during the reading ¼ cell period t3 to t4 is based on the write address signal 121 from the write address counter 143 in the hexadecimal notation. Memory 132
The byte data of the cell 2 sequentially stored in the areas of the addresses "20" to "23" of the above, and input in the read half cell period t4 to t6 is the write address signal from the write address counter 143 in the hexadecimal notation. Based on 121, they are sequentially stored in the areas of addresses “0” to “7” of the data memory 132. That is, each byte data of the cell 2 has the addresses “16” to “2” of the data memory 132.
3 "and" 0 "to" 7 "are sequentially written.

The enable signal 115 given from the decoding circuit 141 to the read address counter 136 becomes significant again from the time point t7 which is delayed by 1/4 cell period t6 to t7 from the time point t6 when the byte data of the next cell 3 starts to be input. After that, the 1/4 cell period t7 to t8 continues to be significant, and the count-up is performed based on the high-speed clock signal in this significant period. Therefore, the read address signal 1 from the read address counter 136
11 changes from "16" to "23" and "0" to "7" in this period t7 to t8, and each byte data 10 of the cell 2 is changed.
7 is read from the data memory 132, is selected by the selector circuit 130, and is multiplexed on the output transmission line HW0.
Is sent as

¼ cell period t6 to t7 before this read
The byte data of the cell 3 input during the (reading period of the data memory 131) is based on the write address signal 121 from the write address counter 143 in the hexadecimal notation, and the area of the addresses “8” to “11” of the data memory 132. Are sequentially stored in the memory cell and are read out for 1/4 cell period t7 to t8.
The byte data of cell 3 input to is stored in the data memory 1
The byte data of the cell 3 which is sequentially stored in the areas of the addresses “12” to “15” of 32 and input during the half cell period t8 to t10 after reading is the addresses “16” to “23” of the data memory 132. Are sequentially stored in the area.
Hereinafter, the same process is repeated.

Next, an access operation to the data memory 133 related to the input transmission line HW3 will be described.

The byte data of cell 1 from time t1 is
Based on the write address signal 122 from the write address counter 144, it is sequentially stored in the area of addresses “0” to “15” of the data memory 133.

The enable signal 116 given from the decoding circuit 141 to the read address counter 137 becomes significant from the time t4 delayed by 1/2 cell period t2 to t4 from the time t2 when the byte data of the next cell 2 starts to be input, After that, the quarter cell period t4 to t5 continues to be significant, and the count-up is performed based on the high-speed clock signal in this significant period. Therefore, the read address signal 112 from the read address counter 137
Changes from "0" to "15" during this period t4 to t5,
Each byte data 108 of the cell 1 is read from the data memory 133, selected by the selector circuit 130 and sent to the output transmission line HW0 as the multiplexed signal 105.

1/2 cell period t2 to t4 before this read
The byte data of the cell 2 input in (in other words, the reading period of the data memories 131 and 132) is based on the write address signal 122 from the 28-ary write address counter 144, and the addresses “16” to “16” of the data memory 133. The byte data of the cell 2 sequentially stored in the area "23" and input during the reading 1/4 cell period t4 to t5 is the address "24" to the data memory 133.
The byte data of the cell 2 sequentially stored in the area “27” and input in the read quarter cell period t5 to t6 is sequentially stored in the area “0” to “3” of the data memory 133. It That is, each byte data of the cell 2 has the addresses “16” to “2” of the data memory 133.
7 "and" 0 "to" 3 "are sequentially written.

The enable signal 116 given from the decoding circuit 141 to the read address counter 137 becomes significant again from the time point t8 delayed by 1/2 cell period t6 to t8 from the time point t6 when the byte data of the next cell 3 starts to be input. After that, the quarter cell period t8 to t9 continues to be significant, and the count-up is performed based on the high-speed clock signal in this significant period. Therefore, the read address signal 1 from the read address counter 137
12 changes from "16" to "27" and "0" to "3" during this period t8 to t9, and each byte data 10 of the cell 2 is changed.
8 is read from the data memory 133, is selected by the selector circuit 130, and is multiplexed on the output transmission line HW0.
Is sent as

½ cell period t6 to t8 before this read
The byte data of the cell 3 input during the (reading period of the data memories 131 and 132) is based on the write address signal 122 from the 28-ary write address counter 144, and the addresses “4” to “1” of the data memory 133.
The byte data of the cell 3 sequentially stored in the area “1” and input during the reading ¼ cell period t8 to t9 are sequentially stored in the area “12” to “15” of the data memory 133. 1/4 cell period t9 to t after reading
The byte data of the cell 3 input to the cell 10 is sequentially stored in the areas of addresses “16” to “19” of the data memory 133. Hereinafter, the same process is repeated.

Next, the access operation to the data memory 134 related to the input transmission line HW4 will be described.

The byte data of cell 1 from time t1 is
Based on the write address signal 123 from the write address counter 145, the data is sequentially stored in the areas of addresses “0” to “15” of the data memory 134.

The enable signal 117 given from the decoding circuit 141 to the read address counter 138 becomes significant from the time point t5 delayed by 3/4 cell period t2 to t5 from the time point t2 when the byte data of the next cell 2 starts to be input. After that, the quarter cell periods t5 to t6 continue to be significant, and the count-up is performed based on the high-speed clock signal in this significant period. Therefore, the read address signal 113 from the read address counter 138
Changes from “0” to “15” during this period t5 to t6,
Each byte data 109 of the cell 1 is read from the data memory 134, selected by the selector circuit 130, and transmitted as the multiplexed signal 105 to the output transmission line HW0.

3/4 cell period t2 to t5 before this read
(In other words, the data memories 131, 132 and 133
The read byte period of cell 2 is
Based on the write address signal 123 from the 32-bit write address counter 145, the data is sequentially stored in the areas of addresses "16" to "27" of the data memory 134 and input during the reading 1/4 cell period t5 to t6. Cell 2
Byte data of the address "2" of the data memory 134.
Sequentially stored in the areas 8 "to" 31 ". That is,
Each byte data of the cell 2 is sequentially written in the area of addresses "16" to "31" of the data memory 134.

The enable signal 117 given from the decode circuit 141 to the read address counter 138 becomes significant again from the time point t9 which is delayed by 3/4 cell period t6 to t9 from the time point t6 when the byte data of the next cell 3 starts to be input. After that, the quarter cell period t9 to t10 is continuously significant, and the count-up is performed based on the high-speed clock signal in this significant period. Therefore, the read address signal 113 from the read address counter 138 is "16" to "31" during this period t9 to t10.
, Each byte data 109 of the cell 2 is read from the data memory 134, selected by the selector circuit 130, and sent to the output transmission line HW0 as the multiplexed signal 105.

3/4 cell period t6 to t9 before this read
The byte data of the cell 3 input during the (reading period of the data memories 131, 132, and 133) is based on the write address signal 123 from the write address counter 145 in binary notation, and the addresses "0" to "" of the data memory 134. The byte data of the cell 3 sequentially stored in the area "11" and input during the reading 1/4 cell period t9 to t10 is the address "12" to the data memory 134.
It is sequentially stored in the area of "15". Hereinafter, the same process is repeated.

As described above, in this embodiment, the read period from each data memory 131, ...
The read address counter 13 is divided into ¼ cell periods, and only in the divided read period.
5, ..., 138 are operated by a high-speed clock signal. In addition, the read period of the written cell is set to the input period of the next cell, and the write address immediately after the read of the 1/4 cell period is set to the head area of the read data memory. , Writing to the data memories 131 to 134 is continued.

Each of the data memories 131, ...
Through the access operation of 134 and the selection operation of the selector circuit 130, the input transmission lines HW1 to
A multiplexed signal 105 similar to the conventional one, in which the cell signals 101 to 104 from the HW 4 are multiplexed in cell units, is transmitted.

According to the above embodiment, the input transmission lines HW1 to HW1.
The total memory capacity of the four data memories 131 to 134 corresponding to HW4 can be made smaller than before, and moreover, the same multiplexed signal as before can be sent to the output transmission line HW0. Specifically, the conventional multiplexing circuit shown in FIG. 2 requires a memory capacity of 8 cells, but in the multiplexing circuit of this embodiment, the memory capacity is (5/4) + (6 /
4) + (7/4) + (8/4) = 6.5 cells,
The memory capacity can be reduced by 1.5 cells.

For example, when the multiplexing circuit is realized on an integrated circuit, the occupied area can be reduced by the smaller memory capacity.

In the above embodiment, the multiplexing unit is 16 bytes, and the cells of the 150 Mb / s transmission line are 60 bytes.
An example of multiplexing at 0 Mb / s is shown, but the length of one cell and the degree of multiplexing can be set freely.

Using a general expression, assuming that the length of one cell is m (unit may be byte or bit) and the multiplicity is n, the memory capacity of each of the n data memories is (n + 1). / N, (n + 2) / n, (n + 3) /
, (2n) / n cells are applied, and the cycle of the write address counter and the read address counter corresponding to each data memory is m (n + 1).
/ N, m (n + 2) / n, m (n + 3) / n, ..., m
(2n) / n may be selected, and when a counter having a two-stage structure for generating a data selection signal is provided as in the above embodiment, the count value of each counter may be m or n.

Here, the memory capacity of the data memory (n +
1) / n, (n + 2) / n, (n + 3) / n, ..., (2
When n) / n cells are a decimal number (when m is not an integer multiple of n), it may be rounded up and applied.

For example, since one cell in the ATM network has 53 bytes, if the multiplicity n is 4, (n + 1) n cells corresponding to the memory capacity of the first data memory is 66.2.
Although it is 5 bytes, in this case, a 67-byte data memory may be applied and the cycle of the write address counter and the read address counter may be set to 67. Similarly,
The other three data memories having capacities of 80 bytes, 93 bytes, and 106 bytes are applied, and the cycle period of each pair of the corresponding write address counter and read address counter is 80, 93,
It may be 106. Although writing and reading are not synchronized, even in this case, the operation is almost the same as that of the above embodiment.

FIG. 5 shows the timing chart in this case for reference, and is shown using the same reference numerals as those in FIG. 4 although the memory capacity and the like are different.

Although the minimum required memory capacity of the data memory has been shown in the above description of the embodiments and the general description, some offset (several bytes) may be provided. In the claims, the expression in which the minimum necessary amount of the memory capacity of the data memory is applied is used, but such expression also includes the case where there is some offset.

Further, in the above embodiment, the input cell signal and the output cell signal (multiplexed signal) are parallel one byte (8 bits). However, even if the parallel signal has another bit number, it is serial. The present invention can be applied even to a signal. In this case as well, the above general expression holds.

Further, although the multiplexing circuit of the present invention is made in consideration of the multiplexing circuit in the transmission device of the ATM network, it is needless to say that its application is not limited.

The present invention is characterized in that the memory capacities of the respective data memories are made different and that the write address signal and the read address signal are generated as shown in FIG. The means for generating the address signal and the read address signal are not limited to those in the above-mentioned embodiment as long as they can be generated as shown in FIG. For example,
It may be generated by software.

[0071]

As described above, according to the present invention, since the signal period of each series in the multiplexed signal is fixed, the data can be read from the data memory of each series only during that period, and the reading can be performed. Based on the fact that the area of the completed data memory can be immediately used as a write area, etc., the capacity of each data memory is selected to be the minimum necessary and its access is controlled. It is possible to realize a multiplex circuit that can contribute to miniaturization and the like with a small number of components.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a conventional timing chart of each part.

FIG. 4 is a timing chart of each part of the embodiment.

FIG. 5 is a timing chart of each part of a circuit that handles a cell having a different number of bytes from that of the embodiment.

[Explanation of symbols]

130 ... Selector circuit, 131-134 ... Data memory, 135-138 ... Read address counter, 139
... counter for byte position in cell, 140 ... counter for input transmission path selection, 141 ... decoding circuit, 142-1
45 ... Write address counter.

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Claims (2)

[Claims] 1. A multiplexing circuit for multiplexing and outputting input signals from n input sequences for each information accommodating unit of length m, corresponding to each input sequence storing the input signal from each input sequence. Among the n data memories, the k-th (k is 1 to n) data memory is the n-port data memory having a capacity of (1 + k / n) × m, and each of the data memories is N write address generating means, which are provided corresponding to each other, for constantly generating write address signals for the capacity of the corresponding data memory, and the corresponding data provided corresponding to each of the data memories. A read address signal corresponding to the capacity of the memory is generated at a speed n times that of the write address signal, and the generation period thereof is determined by dividing itself into n equal parts of one cycle of the information accommodating unit. Multiplexing circuit, characterized in that it comprises n number of the read address generating means is a cycle duration, and selection means for selecting and synchronizing the signal read from the respective data memory read operation. 2. The (1 + k /) of the k-th data memory
The multiplexing circuit according to claim 1, wherein when the memory capacity determined by (n) × m is a decimal multiple of the access unit amount, the memory capacity is set to a value obtained by rounding up the decimal.