JPH08322024A - Device and method for display - Google Patents

Abstract

PURPOSE: To provide a method capable of displaying the video signal of ordinary mode of PAL system and the one of wide mode with an appropriate aspect ratio and a nearly equal display rate. CONSTITUTION: One horizontal scanning period out of six horizontal scanning periods in the video signal of ordinary mode of PAL system or one horizontal scanning period out of seven horizontal scanning periods is thinned out, and it is displayed on a liquid crystal display panel 15. To make the display rate coincide, the signals of three horizontal scanning periods out of eight horizontal scanning periods in the video signal of wide mode of PAL system or the signals of five horizontal scanning periods out of 14 horizontal scanning periods are thinned out, and they are displayed on the display panel 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a display method capable of appropriately displaying video signals having different aspect ratios.

[0002]

2. Description of the Related Art A conventional liquid crystal television is configured for the NTSC system and has a screen length-width ratio of 3: 4.
And has, for example, 234 scanning lines. The number of effective scanning lines of an NTSC video signal is 241.5 per field, and a total of 7.5 scanning lines at the beginning and the end per field are thinned out for display (241.5-7). .5 = 23
4).

Further, the PAL system is known as a television system having a larger number of scanning lines than the NTSC system and capable of displaying a high quality image. The number of effective scanning lines of the PAL system television signal is 287.5 per field, and Formula 1 is established.

## EQU00001 ## 5/6 <241.5 / 287.5 = 0.84 <6/7

From this calculation, in the case of the PAL system, 6
A method is adopted in which video signals are thinned out (1/6 thinning out, 1/7 thinning out) at a rate of 1 horizontal scanning period in every ~ 7 horizontal scanning periods.

Further, the aspect ratio of the display image is 9:16.
The so-called wide mode (ID mode) television has been developed for both the NTSC system and the PAL system. When displaying a wide mode television signal on a liquid crystal television, since 3: 4 = 12: 16,
As shown in FIG. 14, the central 9/12 portion (for example,
176 horizontal scan lines) and an aspect ratio of 9:16
To display the image.

Since 9: 12 = 3: 4, in the case of the NTSC wide mode, video signals are thinned out and displayed at a rate of one horizontal scanning period in four horizontal scanning periods (1/4 thinning). That is, the video signal is displayed at a rate of 3 horizontal scanning periods in 4 horizontal scanning periods (3/4 display).

When displaying a PAL wide-mode television signal, the video signal is thinned out and displayed for one horizontal scanning period in every three horizontal scanning periods (2/3 display, 1/3 thinning).

[0008]

When each video signal is displayed using the above method, in the normal mode of the NTSC system, an image of 234 / 241.5 = 96.89% is displayed. Also, in the normal mode of the PAL system, 1
In the case of / 6 decimation, 234. (6/5) / 287.
5 = 97.67% of the image will be displayed. Also,
In the case of 1/7 decimation, 234 · (7/6) / 28
7.5 = 94.96% of the image will be displayed.

In the case of the NTSC wide mode, an image of 176 · (6/5) /287.5=97.67% is displayed. At this time, the upper and lower black bands are each composed of 29 scanning lines. In the case of PAL wide mode, 176 · (3/2) /287.5
= 91.83% of the video will be displayed.

As described above, whether the 1/6 thinning or the 1/7 thinning is adopted in the PAL system normal mode, there is a large difference in the vertical display area between the PAL system normal mode and the wide mode. Occurs. That is, 1
There is a difference of about 6% in / 6 decimation and about 3% in 1/7 decimation. Therefore, the display image is distorted unless the horizontal display area is changed according to the change of the vertical display area.

That is, as conceptually shown in FIG. 15, unless the display range in the horizontal direction is adjusted in accordance with the effective display ratio in the vertical direction, the vertical and horizontal scales of the display image are different,
The displayed image is distorted. Therefore, it is necessary to correct the dot clock or the like that determines the sampling timing of the video signal according to the change in the display ratio in the vertical direction, which complicates the configuration of the device and makes the design difficult.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a display device and a display method capable of appropriately displaying video signals in a plurality of modes. It is another object of the present invention to provide a display device and a display method capable of displaying a PAL system normal mode video signal and a wide mode video signal with a substantially equal display ratio at an appropriate aspect ratio. .

[0013]

In order to achieve the above object, a display device according to a first aspect of the present invention is a display panel, a signal supply means for supplying a video signal, the display panel and the signal supply. Connected to the means and thinning out the signal of P (N is a number other than a multiple of P) horizontal scanning period of N horizontal scanning periods of the video signal and displaying the thinned signal on the display panel. It is characterized by comprising a driving means for displaying the ratio on the display panel.

According to a second aspect of the present invention, there is provided a display device, a display panel, a first mode video signal having a first aspect ratio, and a second aspect ratio different from the first aspect ratio. Of the L horizontal scanning period of the video signal of the first mode which is connected to the display panel and the signal supplying means and is supplied from the signal supplying means, M
The signals in the horizontal scanning period are thinned out and displayed on the display panel at the first display ratio at the first aspect ratio, and P (N is a multiple of P) in the N horizontal scanning periods of the video signal in the second mode. (A number other than the above), and driving means for thinning out signals in the horizontal scanning period and displaying on the display panel at the second aspect ratio at a display ratio substantially equal to the first display ratio. To do.

Further, a display device according to a third aspect of the present invention is a display panel having a screen having a size ratio of 3: 4 in height and width, and a PAL wide mode of a display image aspect ratio of 9:16. A signal supply means for supplying a video signal, and 3 horizontals of 8 horizontal scanning periods of the PAL wide mode video signal supplied from the display panel and the signal supply means and supplied from the signal supply means. A video signal for 5 horizontal scanning periods of 8 horizontal scanning periods or a video signal for 9 horizontal scanning periods of 14 horizontal scanning periods is thinned out by thinning out 5 horizontal scanning periods of 14 scanning periods. It is characterized by comprising driving means for displaying a signal on the display panel.

A display device according to a fourth aspect of the present invention is a display panel having a screen having a size ratio of 3: 4 in height and width, and a first PAL system having a display image aspect ratio of 3: 4. Aspect ratio of video signal and display image is 9: 1
No. 6 signal supply means for supplying the second video signal of the PAL system, and six horizontal scanning periods of the first video signal supplied from the signal supply means, connected to the display panel and the signal supply means. One horizontal scanning period of the above or one horizontal scanning period of the seven horizontal scanning periods is thinned out to obtain 5 horizontal scanning periods of the six horizontal scanning periods or six horizontal scanning periods of the seven horizontal scanning periods. A video signal is displayed on the display panel, and the second video signal is thinned out by three horizontal scanning periods of eight horizontal scanning periods or five horizontal scanning periods of fourteen horizontal scanning periods to obtain five horizontal scanning periods out of eight horizontal scanning periods. It is characterized by comprising driving means for displaying on the display panel a video signal for the scanning period or for 9 horizontal scanning periods out of 14 horizontal scanning periods.

A display device according to a fifth aspect of the present invention is a display panel having a plurality of scanning lines and a plurality of signal lines intersecting with the scanning lines, a signal supplying means for supplying a video signal, and A signal side driving unit that is connected to the display panel and the signal supplying unit and supplies a signal corresponding to the video signal to the signal line, and N-P (N is a multiple of P of N horizontal scanning periods of the video signal). Other than the above) By supplying a selection signal to the scan line only during the horizontal scanning period, the scanning side drive for thinning out the signal of the P horizontal scanning period of the N horizontal scanning periods of the video signal and displaying on the display panel And a means.

Further, in the display method according to the sixth aspect of the present invention, a step of supplying a video signal, and P () of N horizontal scanning periods of the video signal connected to the display panel and the signal supply means are provided. (N is a number other than a multiple of P) and thinning out the signals in the horizontal scanning period to display the signals on the display panel, thereby displaying the video signals on the display panel at a desired aspect ratio. And

Further, in the display method according to the seventh aspect of the present invention, a signal supplying step of supplying a video signal, a step of supplying a signal corresponding to the video signal to a signal line of a display panel, and the video signal. Of the N horizontal scanning periods of the video signal by supplying a selection signal to the scan line of the display panel in the N-P horizontal scanning period of N horizontal scanning periods (N is a number other than a multiple of P). And thinning out the signals of the P horizontal scanning period to display on the display panel.

[0020]

According to the display device according to the first, second and fifth aspects of the present invention and the display method according to the sixth and seventh aspects, P (N is a multiple of P) in the N horizontal scanning periods. Signals other than the horizontal scanning period are thinned out to display signals for the N-P horizontal scanning period of the N horizontal scanning periods. For example, the video signals in the third, sixth, and eighth horizontal scanning periods of each eight horizontal scanning periods are thinned out and displayed. Therefore, it is possible to display the video signal more appropriately (appropriate aspect ratio and / or display rate) than the conventional method of thinning out the signal of one horizontal scanning period of N horizontal scanning periods and displaying.

A display device according to a third aspect of the present invention includes 8 of PAL wide mode video signals.
Three horizontal scanning periods of the horizontal scanning period or five horizontal scanning periods of the 14 horizontal scanning periods are thinned out and displayed.
By adopting these display methods, one horizontal scanning period of 6 horizontal scanning periods of the PAL system normal mode video signal or one horizontal scanning period of 7 horizontal scanning periods is thinned out and displayed. It is possible to obtain an almost equal display rate as compared with.

A display device according to a fourth aspect of the present invention thins out one horizontal scanning period of the six horizontal scanning periods of the first video signal or one horizontal scanning period of the seven horizontal scanning periods. The second video signal is displayed by thinning out 3 horizontal scanning periods of 8 horizontal scanning periods or 5 horizontal scanning periods of 14 horizontal scanning periods. Therefore, it is possible to display the first and second video signals at substantially the same display rate.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the television device of the present invention will be described. (First Embodiment) A PAL system normal mode video signal is displayed by thinning out one horizontal display period in six horizontal display periods (1
/ 6), and the aspect ratio of the display image in the normal mode is 3:
4 = 12: 16, assuming that the aspect ratio of the wide mode display image is 9:16, if the vertical side of the wide mode display image is compressed to 3/4 times, the flatness of the normal mode and wide mode display image is reduced. The rates are almost the same.

Since the vertical side of the image in the normal mode is compressed 5/6 times by thinning out, the optimum compression ratio in the wide mode is expressed by Formula 2.

[Expression 2] (5/6) · (3/4) = 5/8 Therefore, in the case where one horizontal display period is thinned out in 6 horizontal display periods of the video signal of the PAL system normal mode, the wide mode is used. An optimum display rate can be obtained by thinning out the 3 horizontal display periods from the 8 horizontal display periods of the video signal.

Therefore, in this embodiment, the conventional thinning method of thinning out one of the N scanning lines is skipped, and the P scanning line in the N scanning lines is thinned to display the L scanning line (N Is a number other than a multiple of P). That is, when displaying an image in the wide mode of the PAL system, a thinning method of thinning out 3 scanning lines out of 8 scanning lines and displaying 5 scanning lines is adopted.

Applying the 5/8 display method to a display panel of 234 scanning lines, the actual display area is 97.95% (= 176 · (8/5) /287.5) of the effective display area, and Is almost equal to the mode.

Next, a configuration example of a liquid crystal television capable of such driving will be described with reference to FIGS. FIG. 1 shows the overall configuration of the liquid crystal television of this embodiment. In FIG. 1, the television signal is the antenna 1
1 is received. The tuner 12 is the controller 2
According to the control signal VT from 1, the target signal (the signal of the reception frequency) is tuned, and the composite video signal is R
It is supplied to the GB decoder 13.

The RGB decoder 13 generates a luminance signal of each RGB color, a horizontal synchronizing signal H, and a vertical synchronizing signal V from the composite video signal, outputs the luminance signal of each RGB color to the inverting amplifier 14, and outputs the vertical synchronizing signal to the horizontal synchronizing signal H. The synchronization signal V is output to the controller 21. The inverting amplifier 14 amplifies the signal level of the luminance signal of each color of RGB with a positive or negative amplification factor according to the polarity inversion signal FRP supplied from the controller 21, and outputs it. Further, when the black display signal BK is supplied from the controller 21, the inverting amplifier 14 outputs a luminance signal of each color of RGB for displaying black.

The liquid crystal display panel (LCD) 15 is of an active matrix type and is arranged in a row direction.
The gates are connected to and correspond to 34 scanning lines (gate lines) X1 to X234, 280 signal lines (data lines) Y1 to Y280 arranged in the column direction, and corresponding scanning lines X1 to X234. A thin film transistor (TFT) whose source is connected to the signal lines Y1 to Y280, and a TFT
Of the pixel capacitance CLC connected to the drain of the. The pixel capacitor CLC is composed of a pixel electrode connected to the drain of the TFT, a counter electrode facing the pixel electrode, to which the common voltage VCOM is applied, and a liquid crystal arranged between the pixel electrode and the counter electrode.

The signal side driver 16 is a controller 21.
In accordance with the vertical control signal from, the luminance signals of RGB colors supplied from the inverting amplifier 14 are supplied to the signal lines Y1 to Y280 of the LCD 15. The scanning driver 17 sequentially applies gate pulses to the scanning lines X1 to X234 of the LCD 15 according to the vertical control signal from the controller 21.
The amplifier 18 inverts the polarity of the common voltage VCOM applied to the counter electrode of the pixel capacitor CLC according to the polarity inversion signal FRP supplied from the controller 21.

The mode detection circuit 19 detects the mode of the input signal (normal mode or wide mode) and outputs a mode signal.

The switch section 20 inputs a channel instruction signal for instructing a receiving station and a system switching signal for switching between reception of an NTSC television signal and reception of a PAL television signal.

The controller 21 supplies the tuning control signal VT for adjusting the tuning frequency to the tuner 12 in accordance with the channel signal supplied from the switch section 20. Further, the controller 21 controls the horizontal synchronization signal H
According to the vertical sync signal V, the mode detection signal, and the method switching signal, a horizontal control signal is supplied to the signal side driver 16, a vertical control signal is supplied to the scanning side driver 17, and a polarity reversal signal FRP and black display are supplied to the inverting amplifier 14. The signal BK is supplied, and the polarity inversion signal FRP is supplied to the amplifier 18.

The horizontal control signals supplied to the signal side driver 16 include the signal side start signal SSRT, the dot clock signal DCK, the clear signal CLR, and the output enable signal O.
E, including a horizontal switching signal HCNT. The vertical control signal supplied to the scanning driver 17 includes a gate start signal GSRT, a gate pulse clock signal GPCK, and a gate reset signal (gate output enable signal) GRES.
including.

The signal side driver 16 has a timing generation circuit 31, a shift register 32, a level shifter 33 and a sample hold circuit 3 as shown in the block configuration of FIG.
4 and an output buffer 35.

The timing generation circuit 31 supplies the start signal SSRT and the dot clock DCK supplied from the controller 21 to the shift register 32. FIG.
As shown in (A) and (B), the start signal SSRT
Is a signal which becomes high level for three clock periods of the dot clock DCK. The shift register 32 takes in the start signal SSRT according to the dot clock DCK and sequentially shifts it. The output of the shift register 32 is 3
It is a signal that maintains a high level during the dot clock period and shifts by one dot clock period.

The level shifter 33 includes the shift register 32.
Output signal is converted from the signal level of the signal processing system to the signal level of the drive system and output. Sample hold circuit 34
Has two systems of sample and hold circuits. The timing generation circuit 31 supplies the horizontal switching signal HCNT to the sample hold circuit 34. This horizontal switching signal H
CNT is a gate pulse clock signal GPCK described later.
Is substantially the same signal. Horizontal switching signal HCN
According to T, one of the sample and hold circuits outputs a signal sampled in the previous horizontal scanning period, and the other sample and hold circuit outputs the video of R, G, and B colors via the inverting amplifier 14 according to the output of the level shifter 33. The signal is sampled at the timings shown in FIGS.

The timing generation circuit 31 uses the clear signal C.
The LR and the output enable signal OE are output to the output buffer 35. The output buffer 35 has an output enable signal OE.
Accordingly, the output signal of the sample hold circuit 34 is supplied to the signal electrodes Y1 to Y280. Further, the output buffer 35 grounds (or pulls up) the signal electrodes Y1 to Y280 at the start of each horizontal scanning period in accordance with the clear signal CLR, and discharges (or charges) the electric charge held in the liquid crystal capacitance CLC.

The scanning side driver 17 comprises a timing generation circuit 41, a shift register 42, a gate circuit 43, a level shifter 44, and an output buffer 45, as shown in the block configuration of FIG.

As shown in FIGS. 5A and 5B, the gate pulse clock GPC supplied from the controller 21.
K has a period of one horizontal scanning period (1H), and the pulse is turned off when the gate reset signal GRES is active (low level). The timing generation circuit 41 generates a reference shift timing signal based on the gate start signal GSRT and the gate clock signal GPCK, as shown in FIG.
Supply to.

The shift register 42 sequentially generates shift pulse signals based on this shift timing signal and outputs them to the gate circuit 43. The gate circuit 43 is shown in FIG.
When the gate reset signal GRES shown in (A) is off (high level), the shift pulse is output to the level shifter 44. The level shifter 44 converts the shift pulse that has passed through the gate circuit 43 from the signal level of the signal processing system to the signal level of the driving system and outputs it. The output buffer 45 is
The output signal of the level shifter 44 is applied to the scanning lines X1 to X234 to sequentially scan the scanning lines X1 to X234 horizontally.

The controller 21 is constructed, for example, as shown in FIG. In FIG. 6, the PLL circuit 51
Is a horizontal synchronization signal H supplied from the RGB decoder 13.
The voltage of the oscillation control signal is controlled so that the phase of the oscillation control signal and the internal horizontal synchronization signal PH supplied from the horizontal decoder 54 described later match. The voltage controlled oscillator (VCO) 52 oscillates at a frequency corresponding to the voltage of the oscillation control signal and outputs the basic clock CK. The dot clock generation circuit 55
The basic clock CK is divided to generate the dot clock DCK.

The horizontal counter 53 is reset by the internal synchronizing signal PH from the horizontal decoder 54 and counts the number of pulses of the basic clock CK. Horizontal decoder 54
Decodes the output of the horizontal counter 53 and outputs an internal horizontal synchronizing signal PH when the count value reaches a predetermined value. The internal horizontal synchronizing signal PH is supplied to the reset terminal R of the horizontal counter 53, the PLL circuit 51, the vertical counter 57, the thinning counter 60, and the FRP generating circuit 62. The horizontal decoder 54 outputs the start signal SSRT at the start of each horizontal scanning period, activates the clear signal CLR, and subsequently activates the output enable signal OE.

The vertical counter 57 is reset by an internal vertical synchronizing signal PV described later, and within each vertical synchronizing period,
The number of internal synchronization signals PH is counted. Vertical decoder 5
Reference numeral 8 decodes the count value according to the method switching signal supplied from the switch unit 20, and in the case of the NTSC method, outputs a signal when the count value is 265,
In the case of the method, a signal is output when the count value is 312. The synchronization control circuit 59 synchronizes the vertical synchronization signal V supplied from the RGB decoder 13 and the signal from the vertical decoder 58, and outputs the internal vertical synchronization signal PV as a reset terminal R of the vertical counter 57 and a reset terminal R of the thinning counter 60. And FRP generation circuit 62.

Further, the vertical decoder 58 decodes the count value of the vertical counter 57 according to the mode switching signal supplied from the switch section 20 and the mode signal supplied from the mode detection circuit 19, and the gate start signal is decoded at a predetermined timing. Output GSRT.

[Table 1] Normal mode of NTSC system: 22nd horizontal scanning period Wide mode of NTSC system: 256th horizontal scanning period PAL system normal mode: 22nd horizontal scanning period PAL system wide mode : 306th horizontal scanning period

Further, the vertical decoder 58 outputs the black display signal BK at a predetermined timing.

[Table 2] NTSC system normal mode: No output NTSC system wide mode: 256th to 22nd
Horizontal scanning period PAL normal mode: No output PAL wide mode: 306th to 22nd
Horizontal scanning period

The thinning counter 60 is reset in response to the internal vertical synchronizing signal PV, and counts the number of internal synchronizing signals PH in each vertical synchronizing period. Thinning decoder 6
1 decodes the count value of the thinning counter 60 according to the method switching signal and the mode signal, and in the following cases,
Output the thinning signal.

[Table 3] Normal mode of NTSC system: No thinning signal is output. Wide mode of NTSC system: Second of each 4 horizontal scanning periods
Horizontal scanning period PAL normal mode: Second of each 6 horizontal scanning periods
Horizontal scanning period PAL wide mode: Third, sixth, and eighth horizontal scanning periods of each eight horizontal scanning periods

The FRP generation circuit 62 includes a horizontal decoder 54.
In accordance with the internal horizontal synchronizing signal PH from, the internal vertical synchronizing signal PV supplied from the synchronization control circuit 59, and the thinning signal from the thinning decoder 61, a signal whose level is inverted every horizontal scanning period and each frame is output. Further, when the thinning-out signal is supplied from the thinning-out decoder 61, the FRP generation circuit 62 stops the level inversion of the FRP signal while the thinning-out signal is active.

The horizontal decoder 54 outputs the gate pulse clock GPCK every horizontal scanning period. The horizontal decoder 54 resets the gate pulse clock GPCK and outputs a gate reset (gate disable) signal GRES at the timing when the thinning signal is supplied from the thinning decoder 61.

Next, the operation of the liquid crystal television having the above configuration will be described. (1) When displaying an NTSC system normal mode video signal. In this case, the user uses the switch unit 20 to instruct the reception of NTSC and the reception channel. According to this instruction, the controller 21 outputs the reception control signal VT to the tuner 12. The tuner 12 receives the signal instructed by the reception control signal VT. The mode detection circuit 19 outputs a mode signal indicating the normal mode.

The RGB decoder 13 separates the horizontal synchronizing signal H and the vertical synchronizing signal V from the received signal, and the controller 2
It is supplied to the PLL circuit 51 and the synchronization control circuit 59 in the No. 1 respectively. The PLL circuit 51 controls the voltage of the oscillation control signal such that the horizontal synchronizing signal H and the internal horizontal synchronizing signal PH output from the horizontal decoder 54 are in phase with each other. VC
The O52 controls the oscillation frequency according to the output of the PLL circuit 51 and outputs the basic clock CK. The dot clock generation circuit 55 divides the basic clock CK to generate a dot clock DCK.

The horizontal counter 53 has an internal horizontal synchronizing signal P.
It is reset by H and counts the basic clock CK in each horizontal scanning period. The horizontal decoder 54 outputs the start signal SSRT shown in FIG. 3A at a predetermined timing after the start of each horizontal scanning period according to the count value of the horizontal counter 53. Further, the horizontal decoder 54 outputs a clear signal CLR when each horizontal scanning period starts according to the count value of the horizontal counter 53, and outputs an output enable signal OE after a lapse of a predetermined period.

The timing generation circuit 31 of the signal side driver 16 uses the start signal SSRT and the dot clock signal D.
CK is supplied to the shift register 32. The shift register 32 takes in the start signal SSRT in accordance with the dot clock signal DCK and sequentially shifts it to output a sampling signal. The sample hold circuit 34 switches the sampling circuit according to the switching signal HCNT, and according to the sampling signal boosted by the level shifter 33, as shown in FIGS. 3C to 3E, the RGB colors supplied from the inverting amplifier 14 are supplied. Sampling the video signal. Furthermore, the sample hold circuit 34
The video signal sampled in the previous horizontal scanning period is output.

The output buffer 35 uses all the signal electrodes Y1 to Y280 as reference levels at the timing when the clear signal CLR is supplied, and responds to the video signal supplied from the sample hold circuit 34 at the timing when the output enable signal OE is supplied. Signal electrodes Y1 to Y280.

The vertical decoder 58 outputs a gate start signal GSRT in the 22nd horizontal scanning period, for example, as shown in FIGS. 7A and 7D, according to the count value of the vertical counter 57. Further, as shown in FIG. 7E, the horizontal decoder 54 outputs the gate pulse clock GPCK every horizontal scanning period. Also, in this mode,
As shown in FIGS. 7B and 7F, the black display signal BK and the gate reset signal GRES are not output.

The timing generation circuit 31 of the scanning side driver 17 outputs the gate start signal GSTR and the gate pulse clock GPCK, and the shift register 42 fetches the gate start signal GSRT and sequentially transfers it.
As a result, the gate pulse is applied to the scanning lines X1 to X234 while being shifted every horizontal scanning period. The TFTs connected to the scanning lines X1 to X234 to which the gate pulse is applied are turned on and become conductive.

As described above, the clear signal CLR becomes active at the leading timing of each horizontal scanning period, and the signal side driver 16 is stored in the liquid crystal capacitance CLC via the TFTs turned on by the gate pulse and the signal lines Y1 to Y280. Discharge the electric charge.

Subsequently, the output enable signal OE becomes active level, and the signal side driver 16 applies the video signal sampled in the previous horizontal scanning period to each of the signal lines Y1 to Y280. At the end of each horizontal scanning period,
The gate pulse is turned off, the TFT is turned off, and the voltage applied to the pixel electrode is held in the liquid crystal capacitor CLC and held until the next frame. The polarity of the video signal of each color of RGB is inverted by the inverting amplifier 14 every horizontal scanning period according to the polarity inversion signal FRP shown in FIG. 7C. Accordingly, the polarity of the common signal VCOM is also inverted every horizontal scanning period.

In this manner, the NTSC system normal mode video signal is displayed at an aspect ratio of 3: 4 on 234 horizontal scanning lines. When one vertical scanning period elapses, the count value of the vertical counter 57 becomes 262, and the vertical decoder 58 outputs the detection signal. This signal is synchronized with the vertical synchronization signal V by the synchronization control circuit 59 and supplied to the reset terminals R of the vertical counter 57 and the thinning-out counter 60. Therefore, these counters newly start counting operation. Further, the FRP generation circuit 62 outputs an FRP signal having a phase opposite to that of the previous frame. After that, the same operation is repeated.

(2) When displaying an NTSC wide mode video signal. In this case, the user uses the switch unit 20 to instruct the reception of NTSC and the reception channel. The mode detection circuit 19 detects the wide mode and deactivates the wide mode signal.

The vertical decoder 58, in accordance with the count value of the vertical counter 57, as shown in FIG. 8D, for example, in the 256th horizontal scanning period, the gate start signal GS.
Output RT. Further, as shown in FIG. 8E, the horizontal decoder 54 outputs the gate pulse clock GPCK every horizontal scanning period. Therefore, the gate pulse is applied to the first scan line X1 during the 257th horizontal scan period. Further, the vertical decoder 58 outputs a black display signal BK in the 256th horizontal scanning period, and the inverting amplifier 14 outputs an RGB video signal for displaying black. Therefore, the black display signal is held in the liquid crystal capacitance CLC of the first row, and black is displayed.

When black is sequentially displayed and the selection period of the 30th scanning line (24th horizontal scanning period) is reached, FIG. 8B is displayed.
The gate vertical decoder 58, as shown in FIG.
Turn off K. Therefore, the inverting amplifier 14 outputs the RGB video signal supplied from the RGB decoder 13 with the polarity corresponding to the signal level of the polarity inversion signal FRP. Therefore, the video signal of the 24th horizontal scanning period is displayed on the 30th scanning line.

The thinning decoder 61 outputs a thinning control signal in the third horizontal scanning period of each of the four horizontal scanning periods during the display period. According to the thinning control signal, the horizontal decoder 54, as shown in FIGS. 8 (E) and (F),
In the third horizontal scanning period of each four horizontal scanning periods, the gate clock signal GPCK is turned off and the gate reset signal G is generated.
Outputs RES (low active).

During the display period, since the gate clock signal GPCK is turned off in the third horizontal scanning period of each of the four horizontal scanning periods, the shift register 42 of the scanning side driver 17 is turned on.
Does not shift the shift pulse signal. Further, in response to the gate reset signal GRES, the gate circuit 43 stops the output of the shift clock signal. Therefore, the gate pulse is not applied to any scanning line during the third horizontal scanning period of each four horizontal scanning periods. Therefore, a video signal is output to the signal lines Y1 to Y280, but this video signal does not affect the display. At this time, the level of the polarity inversion signal FRP does not change, and the polarities of the video signal and the common voltage VCOM do not change.

In this way, the video signals of 234 scanning periods are displayed on the 176 horizontal scanning lines in the center of the screen at a rate of thinning out the signals of 1 scanning period in 4 scanning periods. Therefore, the video signal is displayed in the center of the screen with an aspect ratio of 9:16. After that, the vertical decoder 58 outputs the black display signal BK. Further, the thinning-out decoder 61 stops outputting the thinning-out signal. Therefore, the gate pulse is sequentially output, the scan lines are sequentially scanned, and 206 to 23
Black is displayed on four scanning lines (29 scanning lines). In addition, as described above, the vertical decoder 58 outputs the gate start signal GSRT during the 256th horizontal scanning period. For this reason, black is displayed on each of the upper and lower 29 horizontal scanning lines of the display screen, and the center 176 scanning lines have an N: aspect ratio of 9:16.
A TSC wide mode image is displayed.

(3) Displaying a PAL system normal mode video signal. In this case, the user uses the switch unit 20 to instruct the reception of PAL and the reception channel. The mode detection circuit 19 detects the wide mode and deactivates the wide mode signal.

The vertical decoder 58, in accordance with the count value of the vertical counter 57, as shown in FIG. 9D, for example, in the 22nd horizontal scanning period, the gate start signal GSR.
Output T. Further, as shown in FIGS. 9A and 9D, the horizontal decoder 54 outputs the gate pulse clock GPCK every horizontal scanning period. Therefore, the gate pulse is applied to the first scanning line X1 during the 23rd horizontal scanning period. Therefore, the image of the 22nd horizontal scanning period is displayed on the first scanning line.

The thinning decoder 61 outputs a thinning control signal in the second horizontal scanning period of each of the six horizontal scanning periods during the effective display period. According to this thinning-out control signal, the horizontal decoder 54 turns off the gate clock signal GPCK and the gate reset signal GRES during the second horizontal scanning period of each 6 horizontal scanning periods, as shown in FIGS. 9 (E) and 9 (F). (Low active) is output.

Since the gate clock signal GPCK is off, the shift register 42 of the scanning side driver 17 does not shift the shift pulse signal. Further, in response to the gate reset signal GRES, the gate circuit 43 stops the output of the shift clock signal. Therefore, the gate pulse is not applied to any scanning line during the second horizontal scanning period of each 6 horizontal scanning periods. Therefore, the signal line Y1
A video signal is output to Y280, but this video signal does not affect the display. Also, at this time, FIG.
As shown in (C), the level of the polarity inversion signal FRP does not change, and the polarities of the video signal and the common voltage VCOM do not change.

In this way, the signals of one scanning period are thinned out in six scanning periods on the 234 horizontal scanning lines and displayed as a video signal. Therefore, the video signal is displayed in the center of the screen with an aspect ratio of 3: 4.

(4) When displaying a wide mode video signal of the PAL system. In this case, the user uses the switch unit 20 to instruct the reception of PAL and the reception channel. The mode detection circuit 19 detects the wide mode and outputs a signal indicating the wide mode.

The vertical decoder 58, in accordance with the count value of the vertical counter 57, as shown in FIG. 10D, for example, in the 306th horizontal scanning period, the gate start signal GS.
Output RT. Further, as shown in FIG. 10E, the horizontal decoder 54 outputs the gate pulse clock GPCK every horizontal scanning period. Therefore, the gate pulse is applied to the first scan line X1 during the 307th horizontal scan period.
Further, the vertical decoder 58 outputs the black display signal BK from the 306th horizontal scanning period. Therefore, the inverting amplifier 1
Reference numeral 4 outputs an RGB video signal for displaying black, and black is displayed on the first scanning line.

When black is sequentially displayed and the selection period of the 30th scanning line (the 23rd horizontal scanning period) is reached, FIG.
As shown in (B), the gate vertical decoder 58 turns off the black display signal BK. Therefore, the inverting amplifier 14 is RG
The RGB video signal supplied from the B decoder 13 is output with the polarity corresponding to the signal level of the polarity inversion signal FRP. Therefore, the image of the 23rd horizontal scanning period is displayed on the 30th scanning line.

The thinning-out decoder 61 outputs the thinning-out control signal in the third, sixth, and eighth horizontal scanning periods of each of the eight horizontal scanning periods during the display period. According to this thinning-out control signal, the horizontal decoder 54 is shown in FIGS.
As shown in, the gate clock signal GPCK is turned off and the gate reset signal GRES (low active) is supplied during the third, sixth, and eighth horizontal scanning periods of each eight horizontal scanning period.
Is output.

In the third, sixth, and eighth horizontal scanning periods of each of the eight horizontal scanning periods, since the gate clock signal GPCK is off, the shift register 42 of the scanning side driver 17 does not shift the shift pulse signal. . Further, in response to the gate reset signal GRES, the gate circuit 43 stops the output of the shift clock signal. Therefore, the gate pulse is not applied to any of the scan lines during the third, sixth, and eighth horizontal scanning periods of each eight horizontal scanning periods. On the other hand, the signal side driver 16 outputs a video signal to the signal lines Y1 to Y280, but this video signal does not affect the display. At this time, the level of the polarity inversion signal FRP does not change, and the polarities of the video signal and the common voltage VCOM do not change.

In this way, the video signal is displayed on the 176 horizontal scanning lines in the central portion of the screen at the rate of thinning out the signals of 3 scanning periods in 8 scanning periods. Therefore, the video signal is displayed in the center of the screen with an aspect ratio of 9:16.

After that, the vertical decoder 58 outputs the black display signal B.
Output K. Further, the thinning-out decoder 61 stops outputting the thinning-out signal. Therefore, the gate pulse is sequentially output, the scan lines are sequentially scanned, and black is displayed on the 206 to 234 scan lines. Further, the gate start signal for the next frame is output during the 306th horizontal scanning period. Therefore, black is displayed on each of the upper and lower 29 horizontal scanning lines of the display screen, and a PAL wide mode image is displayed on the central 176 scanning lines with an aspect ratio of 9:16.

As described above, according to this embodiment, when a PAL system normal mode video signal is displayed by 1/6 decimation, a PAL system wide mode video signal is displayed by 3/8 decimation. To do. Therefore, 97.67% of the effective display area is displayed in the PAL normal mode, and 9% of the effective display area is displayed in the PAL wide mode.
7.95%, which is almost equal. Therefore, the flatness ratios of the images are almost equal. Therefore, the design of the television set becomes easy. Further, the frequency of the basic clock CK can be unified between the normal mode and the wide mode, and the configuration of the peripheral circuit can be simplified.

In the above embodiment, the vertical counter 57
The thinning counter 60, the vertical decoder 58, and the thinning decoder 61 are provided independently. However, as shown in FIG. 11, it is also possible to share one counter as a thinning counter and a vertical counter and use one decoder as a thinning decoder and a vertical decoder.

(Second Embodiment) In the above embodiment, P
The present invention has been described by taking as an example the case where an AL system normal mode video signal is displayed by ⅙ thinning.
The present invention can also be applied to the case where a PAL system normal mode video signal is displayed with 1/7 thinning. in this case,
As shown in FIGS. 12A to 12D, the PAL wide-mode video signal is thinned out by 5/14, that is, each 14
It is desirable to display an image at a rate of 9 horizontal scanning periods in each horizontal scanning period.

In the example of FIGS. 12A to 12D, the video signals of the third, sixth, ninth, twelve, and fourteenth horizontal scanning periods of the fourteen horizontal scanning periods are thinned out and displayed. By displaying at such a thinning rate, the NTSC normal display is 96.8.
9% display, NTSC wide mode display 97.17% display, PAL normal mode video signal display 94.96
% Display, PAL wide mode video signal display is 9
The display is 5.23%, and the difference between the display rates in both modes is very small. Therefore, the flatness ratios of the images are almost equal. Therefore, the design of the television set becomes easy. Further, the frequency of the basic clock CK can be unified between the normal mode and the wide mode, and the configuration of the peripheral circuit can be simplified.

Also in the second embodiment, as shown in FIG. 13, it is possible to use one counter as a thinning counter and a vertical counter and use one decoder as a thinning decoder and a vertical decoder. In addition,
In this case, it is desirable to configure the lower 4 bits of the counter as a 14-base counter.

The timing charts shown in the first and second embodiments are merely examples. Any thinning-out method may be used as long as the thinning-out of the video signal results in 3/8 (first embodiment) and 5/14 (second embodiment). For example, in the first embodiment, when a wide mode video signal of the PAL system is displayed, the video signals of the first 3 lines of each 8 horizontal scanning periods are thinned out and the video signals of the last 5 horizontal scanning periods are displayed. Good. Similarly, in the second embodiment, when displaying a PAL wide mode video signal, the video signals of the first 5 lines of each 14 horizontal scanning periods are thinned out and the video signals of the last 9 horizontal scanning periods are displayed. Good. The timing of these decimation can be arbitrarily adjusted by setting the decimation decoder 61 of the controller 21.

For example, in the first embodiment, repetition of 1/4 thinning and 2/4 thinning results in 3/8.
You may implement thinning. In addition, in the second embodiment,
Repeating 5/7 thinning and 4/7 thinning may result in 5/14 thinning by repeating 3/5 thinning, 3/5 thinning, and 3/4 thinning.

In the first and second embodiments, the present invention has been described by taking as an example the case of displaying an NTSC system video signal and a PAL system video signal on the LCD 15 having a screen having a size ratio of 3: 4. The invention can be applied to the case of displaying a video signal of any mode of any other system, that is, the case of thinning and displaying an arbitrary video signal at a predetermined ratio.

In the first and second embodiments, the case where the broadcast wave is received and displayed has been described as an example. However, the present invention is not limited to the above embodiment, and can be similarly applied to the case where a PAL system video signal obtained by an image pickup device such as a CCD is displayed on a monitor or the like. Further, the LCD 15 has a TF structure.
The type is not limited to the T type, and may be an active matrix type using MIM or an arbitrary passive matrix type color panel. Further, the present invention is not limited to the LCD, and can be applied to other arbitrary matrix display type display panels. The display panel may be an active matrix type or a passive matrix type. Examples of this type of display element include a plasma display panel (PD
P), field emission display panel (FED),
LED display panel, electroluminescence (EL)
A display panel or the like can be used.

[0087]

As described above, according to the present invention, it is possible to display video signals of different systems and / or different modes with desired aspect ratios and to keep the effective display rate substantially constant. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a television device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the structure of a signal electrode drive circuit.

3A to 3E are timing charts for explaining the operation of the signal electrode drive circuit shown in FIG.

FIG. 4 is a block diagram showing a structure of a scan electrode driving circuit.

5A to 5C are timing charts for explaining the operation of the scan electrode driving circuit shown in FIG.

FIG. 6 is a block diagram showing a structure of a controller.

7A to 7F are timing charts for explaining an operation of receiving the video signal in the normal mode of the NTSC system of the television device shown in FIG.

8A to 8F are timing charts for explaining an operation of receiving the NTSC wide-mode video signal of the television device shown in FIG.

9A to 9F are timing charts for explaining an operation of receiving the video signal in the normal mode of the PAL system of the television device shown in FIG.

10A to 10F are timing charts for explaining an operation of receiving a PAL wide mode video signal of the television device shown in FIG. 1.

FIG. 11 is a diagram illustrating another configuration example of a vertical counter, a thinning counter, a vertical decoder, and a thinning decoder.

12 is a timing chart for explaining the operation of the second embodiment of the television apparatus shown in FIG.

FIG. 13 is a diagram showing another configuration example of a vertical counter, a thinning counter, a vertical decoder, and a thinning decoder.

FIG. 14 is a diagram for explaining the sizes of a liquid crystal display element and a display image.

[Fig. 15] Fig. 15 is a diagram for describing the flatness of a display image when a video signal is thinned out and displayed.

[Explanation of symbols]

11 ... Antenna, 12 ... Tuner, 13 ... RGB decoder, 14 ... Inversion amplifier, 15 ... Liquid crystal display panel (LCD), 16 ... Signal side driver, 17 ... Scan Side driver, 18 ... Amplifier, 19 ... Mode detection circuit, 20
... switch section, 21 ... controller, 31 ... timing generation circuit, 32 ... shift register, 33 ... level shifter, 34 ... sample hold circuit, 35 ... output buffer, 41 ... ..Timing generation circuit, 42 ... shift register, 43 ... gate circuit, 44 ... level shifter, 4
5 ... Output buffer

Claims (10)

[Claims] 1. A display panel, a signal supply unit for supplying a video signal, P connected to the display panel and the signal supply unit, and N (N is a multiple of P) out of N horizontal scanning periods of the video signal. A display device comprising: driving means for displaying the video signal on the display panel at a desired aspect ratio by thinning out the signals in the horizontal scanning period and displaying the thinned signals on the display panel. 2. A display panel and a signal supply for supplying a first mode video signal having a first aspect ratio and a second mode video signal having a second aspect ratio different from the first aspect ratio. Means for connecting to the display panel and the signal supply means, and thinning out the signal in the M horizontal scanning period of the L horizontal scanning periods of the video signal in the first mode supplied from the signal supplying means. In the first display ratio at the first aspect ratio, and thinning out the signal of P (N is a number other than a multiple of P) horizontal scanning period of N horizontal scanning periods of the video signal of the second mode. And a drive unit for displaying the display panel on the display panel at the second aspect ratio at a display rate substantially equal to the first display rate. 3. A display panel having a screen having a size ratio of 3: 4 in length and width, signal supply means for supplying a PAL wide mode video signal having an aspect ratio of a display image of 9:16, and the display panel. And 3 horizontal scanning periods of 8 horizontal scanning periods of the PAL wide mode video signal which is connected to the signal supplying means and is supplied from the signal supplying means. 5. A display device comprising: driving means for displaying signals for 5 horizontal scanning periods on the display panel. 4. A display panel having a screen having a size ratio of 3: 4 in height and width, and a PAL first video signal having a display image aspect ratio of 3: 4 and a display image aspect ratio of 9:16. PA
A signal supply means for supplying a second video signal of the L system, a first video signal connected to the display panel and the signal supply means, and supplied from the signal supply means for 6 horizontal scanning periods. One horizontal scanning period is thinned out to display a signal for five horizontal scanning periods of six horizontal scanning periods on the display panel, and a second video signal for one horizontal scanning period of eight horizontal scanning periods. A display device comprising: driving means for thinning out and displaying signals for 7 horizontal scanning periods out of 8 horizontal scanning periods on the display panel. 5. A display panel having a screen having a size ratio of 3: 4 in height and width, signal supply means for supplying a PAL wide mode video signal having a display image aspect ratio of 9:16, and the display panel. And 5 horizontal scanning periods of 14 horizontal scanning periods of the PAL wide mode video signal which is connected to the signal supplying means and is supplied from the signal supplying means. And a drive unit for displaying signals for 9 horizontal scanning periods on the display panel. 6. A display panel having a screen with a vertical and horizontal size ratio of 3: 4, and a display image having an aspect ratio of 3: 4 and a PAL first video signal having a aspect ratio of 3: 4. PA
A signal supplying means for supplying a second video signal of the L system, a first video signal connected to the display panel and the signal supplying means, and supplied from the signal supplying means for a period of 7 horizontal scanning. One horizontal scanning period is thinned out to display 6 horizontal scanning period signals of 7 horizontal scanning periods on the display panel, and the second video signal is output for 1 horizontal scanning period of 14 horizontal scanning periods. A display device comprising: driving means for thinning out and displaying signals for 9 horizontal scanning periods out of 14 horizontal scanning periods on the display panel. 7. The driving means displays the video signal on the display means at different thinning rates according to the timing of the video signal within the vertical scanning period. The display device according to any one of claims. 8. A display panel having a plurality of scanning lines and a plurality of signal lines intersecting with the scanning lines, a signal supply means for supplying a video signal, and the signal connected to the display panel and the signal supply means. The signal side driving means for supplying a signal corresponding to the video signal to the line, and the scanning line to the scanning line only during NP (N is a number other than a multiple of P) horizontal scanning period of N horizontal scanning periods of the video signal. A scanning side driving means for thinning out a signal of a P horizontal scanning period of the N horizontal scanning periods of the video signal to display it on the display panel by supplying a selection signal. apparatus. 9. A step of supplying a video signal, comprising P (N is a number other than a multiple of P) horizontal scanning period of N horizontal scanning periods of the video signal, which is connected to said display panel and said signal supplying means. And a step of displaying the video signal on the display panel in a desired aspect ratio by thinning out the signal and displaying the thinned signal on the display panel. 10. A signal supplying step of supplying a video signal, a step of supplying a signal corresponding to the video signal to a signal line of a display panel, and N-P (N) of N horizontal scanning periods of the video signal. Is a number other than a multiple of P) by supplying a selection signal to a scan line of the display panel during a horizontal scanning period, thereby thinning out the signal of the P horizontal scanning period of the N horizontal scanning periods of the video signal. And a step of displaying on the display, and a display method comprising: