JPH08321761A - Output buffer circuit - Google Patents

Abstract

PURPOSE: To provide an output buffer circuit in which a drive capability of the output buffer is adjusted without a control terminal and an exclusive program. CONSTITUTION: An exclusive OR circuit 6 compares the timing of rising of an input signal of a 1st output buffer 50 with the timing of rising of an output signal. If a load requiring excessive rating than a rated load of the 1st output buffer 50 is loaded to an output terminal 54, since a delay is caused at a rising of an output signal of the 1st output buffer 50, one of two inputs to the exclusive OR circuit 6 goes to a high level and the other goes to a low level, and then the output goes to a high level. Since the input signal is fed to 2nd output buffers 1a, 1b via gate circuits 2, 3, the 2nd output buffers 1a, 1b are also driven.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer, and more particularly to an output buffer of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Since an output buffer in a semiconductor integrated circuit has a fixed driving capability, it is not possible to adjust the rise, fall, ringing, etc. of the output waveform when the output load changes depending on the application.

Therefore, the following output buffer is known as a technique for performing this adjustment.

FIG. 2 is a circuit diagram of a conventional output buffer. The output buffer includes a first output buffer 50, a second output buffer 51 connected in parallel with the output buffer 50, and a pre-buffer 52 connected to the common input side.
, An input terminal 53, and an output terminal 54, and the second output buffer 51 has a control terminal 55 because it is a three-state buffer.

According to this configuration, when the output terminal 54 is connected to the rated load when the output buffer 50 is used alone, the output buffer 50 alone can drive the second output buffer 51 to the high level. A signal to be an impedance is input, while the output buffer 54 is connected to the output terminal 54.
0 When a load exceeding the rated load in the case of single use is connected, the output buffer 50 alone has insufficient driving capability, and therefore a signal for driving the second output buffer 51 is input to the control terminal to output the output buffer 50. , 51 were driven in parallel to increase the driving capability.

Further, as a conventional technique, there is (1) Japanese Patent Laid-Open No.
Japanese Patent Laid-Open No. 274257/1987 discloses a microcomputer in which a plurality of output buffers are turned on by a user program to increase a driving force, and
Japanese Patent No. 206809 discloses an output buffer circuit in which a plurality of output buffers are turned on by an external control signal to increase a driving force, and (3) Japanese Unexamined Patent Publication No. 2-82715 discloses a parallel connection circuit. An output buffer circuit is disclosed in which one of the transistors is selectively driven by a control signal from the outside via a P-type MOS transistor.

[0007]

However, the conventional output buffer has a drawback that the number of terminals of the package of the semiconductor device increases because it requires a control terminal for externally controlling the output buffer. Further, since an operation or a component for external control is required, there is a drawback that the number of work steps and the number of components are increased, which hinders cost reduction and downsizing.

Further, when the output buffer is controlled by a program, a dedicated program for control has to be prepared separately.

Therefore, an object of the present invention is to provide an output buffer capable of adjusting the drive capability of the output buffer without a control terminal or a dedicated program.

[0010]

In order to solve the above-mentioned problems, the present invention provides a first output buffer, a second output buffer connected in parallel with this output buffer, and an input to the first output buffer. The delay means for delaying and extracting the generated signal, the comparing means for comparing the rising timings of the signals output from the delay means and the signals output from the first and second output buffers, and the comparing means. If the rising timings coincide with each other, the input side of the second output buffer is shut off, and if they do not coincide with each other, the second side is shut off.
And a control means for electrically connecting the input side of the output buffer.

[0011]

The input / output timing of the first output buffer is matched in advance by the delay means with a load below the rating, and the input / output timing in the state where the load is actually connected is compared by the comparing means. When the load is overloaded, the output timing is delayed, so that the comparing unit detects the mismatch between the input level and the output level, and when the mismatch is detected, the control unit drives the second output buffer.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of an output buffer according to the present invention. The same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

The output buffer is the first output buffer 50.
And a second output buffer 1 formed by connecting a P-type MOS transistor 1a and an N-type MOS transistor 1b in series.
A NAND circuit 2 whose output side is connected to the gate of the P-type MOS transistor 1a, and an AND circuit 3 whose output side is connected to the gate of the N-type MOS transistor 1b.
And a prebuffer 52 connected between the input side of the first output buffer 50 and the input terminal 53, and an internal buffer 4 having its input side connected to the output side of the prebuffer 52 and the input side of the P-type MOS transistor 1a. And an output monitor buffer 5 for waveform shaping, the output side of which is connected to the output side of the first output buffer 50, the output side of the second output buffer 1 and the output terminal 54, and the output and output monitor of the internal buffer 4. The output of the buffer 5 and an exclusive OR (hereinafter, referred to as EXOR) circuit 6 are input, and the output of the EXOR circuit 6 is commonly input to one input side of the NAND circuit 2 and the AND circuit 3. A signal is input from the input terminal 53 to the other input side of the NAND circuit 2, and the pre-buffer 52 is input to the other input side of the AND circuit 3.
The output of is input.

The internal buffer 4 is a buffer for extracting the signal input to the first output buffer 50 after delaying it for a fixed time. Then, with a small load (a load equal to or less than the rating) being applied to the first output buffer 50, the input signal of the first output buffer 50 and the rising timing of the output signal are input at the input side of the EXOR circuit 6 so that they coincide with each other. The rising timing of the signal is delayed by the internal buffer 4. That is, the delay time of the internal buffer 4 is adjusted in advance so that the rising timings of the input / output signals coincide with each other. It is necessary to prevent a signal from being input to the input side of the second output buffer 2 during this adjustment. For example, the output side of the EXOR circuit 6 is forcibly grounded.

With this arrangement, when the first output buffer 50 is loaded with a large load (a load equal to or higher than the rated value), the rising timing of the output of the first output buffer 50 is delayed, and this delay is caused. By detecting whether or not the load occurs, it is possible to determine whether the load applied to the first output buffer 50 is appropriate or excessive.

Next, the operation of this output buffer will be described. First, a case where a small load (load below the rating) is applied to the output terminal 54 will be described.

When a high level signal is input to the input terminal 53, this signal is inverted by the pre-buffer 52 to a low level and after a certain delay is given by the delay circuit 4, E
It is input to the XOR circuit 6.

The signal input to the first output buffer 50 is further inverted and becomes high level, and the output terminal 54
At the same time, the output monitor buffer 5 inverts it to a low level and inputs it to the EXOR circuit 6.

In this case, since the output signal of the first output buffer 50 is not delayed, the two signals input to the EXOR circuit 6 are both low level and rise (fall in this case) timing. Therefore, a low level signal is output from the output side of the EXOR circuit 6.

Therefore, the output of the NAND circuit 2 is at a high level and the output of the AND circuit 3 is at a low level, so that the P-type MO
Neither the S transistor 1a nor the N-type MOS transistor 1b is driven, and only the first output buffer is driven.

On the other hand, when a low level signal is input to the input terminal 53, this signal is inverted by the pre-buffer 52 to become a high level signal, and after being given a certain delay by the delay circuit 4, it is input to the EXOR circuit 6. It

The signal input to the first output buffer 50 is further inverted and becomes low level, and the output terminal 54
At the same time, the output monitor buffer 5 inverts it to a high level and inputs it to the EXOR circuit 6.

In this case, since the output signal of the first output buffer 50 is not delayed, the two signals input to the EXOR circuit 6 are both at the high level and the rising timings are the same, and thus EXOR. A low level signal is output from the output side of the circuit 6.

Therefore, the output of the NAND circuit 2 is at a high level and the output of the AND circuit 3 is at a low level, so that the P-type MO
Neither the S transistor 1a nor the N-type MOS transistor 1b is driven, and only the first output buffer is driven.

Next, a case where a large load (load above the rating) is applied to the output terminal 54 will be described.

When a high level signal is input to the input terminal 53, the high level signal is output from the first output buffer 50. However, this high level signal is output after a certain time delay due to heavy load. To be done. Therefore, a low level signal is output during this delayed period. As a result, a high level signal is output from the output monitor buffer 5 during this period and input to one of the EXOR circuits 6. Therefore, since the low level signal from the internal buffer 4 and the high level signal from the output monitor buffer 5 are input to the EXOR circuit 6, the output of the EXOR circuit 6 becomes high level.

Therefore, the output of the NAND circuit 2 or the AND circuit 3 depends on the level of the input signal. That is,
Since the two signals input to the NAND circuit 2 are both at high level, the output becomes high level, while the two signals input to the AND circuit 3 become the high level signal and the low level signal, the output becomes low level. Becomes Therefore, P-type MO
Since the S transistor 1a is driven and the N-type MOS transistor 1b is not driven, the output of the second output buffer 1 becomes high level, and thus the first output buffer 50 and the second output buffer 1 are driven in parallel.

When a low-level signal is input to the input terminal 53, the low-level signal is output from the first output buffer 50, but this low-level signal is output after a certain time delay due to the heavy load. To be done. Therefore, a high level signal is output during this delayed period. As a result, a low level signal is output from the output monitor buffer 5 during this period and input to one of the EXOR circuits 6. Therefore, since the high level signal from the internal buffer 4 and the low level signal from the output monitor buffer 5 are input to the EXOR circuit 6, the output of the EXOR circuit 6 becomes high level.

Therefore, the output of the NAND circuit 2 or the AND circuit 3 depends on the level of the input signal. That is,
Since the two signals input to the NAND circuit 2 are a high level signal and a low level signal, the output becomes high level. on the other hand,
Since the two signals input to the AND circuit 3 are both at high level, the output is at high level.

Therefore, the P-type MOS transistor 1a
Is not driven and the N-type MOS transistor 1b is driven, so that the output of the second output buffer 1 becomes low level,
Therefore, the first output buffer 50 and the second output buffer 1
Are driven in parallel.

Note that the output buffers 1 and 50 can be configured by buffers that do not phase invert. In this case, the output monitor buffer 5 must also be configured by buffers that do not phase invert.

[0032]

According to the present invention, the rising timings of the input signal and the output signal of the first output buffer are compared, and if there is a difference in the rising timings, it is determined that the load is excessive. Since the second output buffer is driven, it is possible to adjust the driving capability of the output buffer without a control terminal or a dedicated program.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of an output buffer according to the present invention.

FIG. 2 is a circuit diagram of a conventional output buffer.

[Explanation of symbols]

 1a P-type MOS transistor 1b N-type MOS transistor 2 NAND circuit 3 AND circuit 4 Internal buffer 5 Output monitor buffer 6 Exclusive OR circuit 50 First output buffer

Claims (6)

[Claims] 1. A first output buffer, a second output buffer connected in parallel with this output buffer, delay means for delaying and extracting a signal input to the first output buffer, and this delay means. The signal output from the first
And the comparing means for comparing the rising timings of the signals output from the second output buffer and the comparing means, if the rising timings match, the input side of the second output buffer is shut off, and there is a mismatch. In some cases, the output buffer circuit comprises control means for electrically connecting the input side of the second output buffer. 2. The delay means delays such that when the first output buffer is driven at a rated load, the rising timings of the output signal of the delay means and the output signal of the first output buffer match. The output buffer circuit according to claim 1, wherein the output buffer circuit has time. 3. The comparison means is a circuit that logically operates the output level of the delay means and the output levels of the first and second output buffers.
Or the output buffer circuit according to 2. 4. The control means receives the output of the comparison means at one input side, and receives at the other input side the same signal as the signal input to the first output buffer, and the comparison means. 4. The output buffer circuit according to claim 1, wherein a signal input to the other input side is input to the second output buffer when a mismatch is detected in. 5. The control means is a circuit that logically operates the output level of the comparison means and the signal level input to the first output buffer.
4. The output buffer circuit according to any one of 4 to 4. 6. The output buffer circuit according to claim 1, wherein the second output buffer is composed of a MOS transistor.