JPH08321555A - Semiconductor device - Google Patents

Abstract

PURPOSE: To finish a transistor with minimum gate length on design rule regardless of the pattern by previously skewing a mask while taking account of dependency of the finish dimensions of gate electrode on the pattern due to proximity effect or the like. CONSTITUTION: While taking account of dependency of the finish dimensions of gate electrode on the pattern, exposure is effected using a mask being skewed previously on the layout. The gate length Li of an isolated gate electrode is set shorter than the gate length Lc of aggregated gate electrodes which is equal to the minimum gate length Lmin on design rule considering the process margin and the space Ls between the aggregated gate electrodes is set in the range of minimum gate length min and 2Lmin. Gate lengths Li, Lc of the isolated gate electrode and aggregated gate electrode are set substantially equal to the minimum gate length Lmin by controlling the exposure conditions for finishing the aggregated gate as designed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an insulated gate transistor represented by a MOS (Metal-Oxide-Semiconductor) transistor, or an integrated circuit constituted by the transistor.

[0002]

2. Description of the Related Art In recent years, the miniaturization of MOS transistors forming integrated circuits has progressed, and it is about to enter the so-called deep submicron generation.
A transistor having a thickness of 0.35 μm or less is about to be realized.

However, since the deep submicron generation and beyond, the conventional lithography technique using an i-line stepper is approaching its limit, and when a fine pattern is dense, a phenomenon that the resist becomes thin due to a proximity effect or the like occurs. . For example, when a gate electrode that exists in an isolated state in a chip and a gate electrode that exists in a dense state as in a multi-input circuit or a memory cell coexist, the dense gate electrode is better than the isolated gate electrode. I know that it will get thinner.

FIG. 6A shows a layout example of isolated gate electrodes and dense gate electrodes. In the figure, 21 is a gate electrode, 22 is an active region, the gate length Lmin is the minimum value in the chip design, for example, about 0.35 μm, and the inter-gate electrode space Ls is Lmin to 2Lmi.
It is about n. In this case, if the exposure condition is adjusted to the isolated pattern, the dense pattern is narrower than the target, and therefore FIG.
As shown in (b), the gate length is 0.03 to 0.05 μm.
Therefore, it is necessary to secure a large gate length margin for the short channel effect. Note that FIG.
In (b), 23 is a gate insulating film.

On the contrary, when the exposure condition is adjusted to the dense pattern, as shown in FIG. 6C, the isolated pattern is thicker than the target by about 0.03 to 0.05 μm, so that the gate length becomes longer, which results from the miniaturization. The merit of improving the transistor performance cannot be obtained. Note that such pattern dependence of the gate electrode cannot be completely removed by the current lithography technology.

Under such circumstances, for example, "Science Forum latest version VLSI process data handbook,
March 1994, p. 121 ”, various high-resolution lithography techniques have been proposed.

As an optical lithography technique, excimer laser lithography using a KrF laser or an ArF laser as a light source has been attracting attention in recent years, and EB (electron beam) is used.
Direct writing technology and X-ray lithography technology are also being studied. Although KrF excimer laser stepper and EB writing system have been commercialized, there are still many problems to be solved, and it is said that the sub-half micron second generation or quarter micron generation will replace the i-line stepper. It is being appreciated.

As a movement for surviving the sub-half micron generation with an i-line stepper, for example, as described in "Nikkei Microdevice April 1992, p.22", exposure illumination such as modified illumination method is used. Efforts to improve system technology, resist technology such as new material design of photosensitizer, or mask technology such as phase shift mask,
Some of them are considered to be promising, but they have some problems such as increase in cost, decrease in throughput, and pattern dependence of effect. For the above-mentioned problem of pattern dependence of gate electrode finish, However, there is no guarantee that it will be resolved reliably, and it is just a situation that depends on the efforts of manufacturers in various fields.

[0009]

In view of the above situation, the present invention can be easily performed by using the conventional technique by devising the layout without relying on the improvement of the lithography, the exposure illumination system, the resist, the mask technique or the like. The present invention is intended to provide an insulated gate transistor or an integrated circuit which effectively copes with the pattern dependence of the finish of the gate electrode and enables miniaturization, high performance and high reliability at the same time. .

[0010]

That is, according to the present invention, by applying a skew in consideration of the finish of a pattern on a mask, it is possible to easily and effectively reduce the size, improve the performance, and improve the performance without resorting to a new technique. It is intended to provide a MOS transistor or an integrated circuit which enables reliability.

According to another aspect of the semiconductor device of the present invention, one or more gate electrodes and one or more other gate electrodes different from the gate electrodes have different lengths in the channel direction in the layout (hereinafter referred to as gate lengths). And the finished dimensions of the gate lengths of the both gate electrodes manufactured by using the mask having the above-mentioned layout are set to the same extent.

According to another aspect of the semiconductor device of the present invention, the difference in layout of the gate lengths of the both gate electrodes is about 1/10 to 1/7 of the minimum gate length in the same chip. Of the gate electrodes, the gate length of the gate electrode having the shortest gate length is the minimum gate length, and the finished dimension difference between the gate lengths of the two gate electrodes is 1/10 to 7 minutes of the minimum gate length. It is characterized in that it is within the range of less than 1.

According to another aspect of the semiconductor device of the present invention, the layout difference in gate length between the gate electrodes is 0.05.
The gate length of the gate electrode having the shortest gate length among the gate electrodes is the minimum gate length in the same chip, and the finished dimension difference between the gate lengths of the both gate electrodes is less than 0.05 μm. It is characterized by being settled.

A semiconductor device according to a fourth aspect is characterized in that the minimum gate length is 0.5 μm or less.

According to another aspect of the semiconductor device of the present invention, in a multi-input circuit in which a plurality of transistors are connected in series, there is no contact hole between the gate electrodes and the plurality of gates are arranged on the active region. Is manufactured by using a mask laid out so that the gate length is longer than the minimum gate length in the same chip.

A semiconductor device according to a sixth aspect is a multi-input N
The AND circuit is characterized by being manufactured using a mask in which the gate length of the N-channel transistor is longer than that of the P-channel transistor.

A semiconductor device according to a seventh aspect is a multi-input N
The OR circuit is characterized by being manufactured using a mask in which the gate length of the P-channel transistor is longer than that of the N-channel transistor.

According to another aspect of the semiconductor device of the present invention, in a memory circuit configured by arranging a plurality of basic memory cells side by side, the gate length of the memory cell constituent transistors is longer than the minimum gate length in the same chip. It is characterized by being manufactured using a laid-out mask.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. Example 1 FIG. 1A is a layout view of polysilicon for a gate electrode, and FIG. 1B is a cross-sectional view showing a finished state of a gate electrode. In these figures, the layout of wells, metal wirings, etc., or the finished state is shown. Illustration is omitted. In these figures, 1 is polysilicon for a gate electrode, 2 is an active region, and 5 is a gate insulating film.

In FIG. 1A, Li is the gate length of the isolated gate electrode, Lc is the gate length of the dense gate electrode, and Ls.
Is a space between the dense gate electrodes, Li is shorter than Lc, and Lc is laid out with the same length as the minimum gate length Lmin in the design rule in consideration of the process margin.
Is about Lmin to 2Lmin. A finished sectional view of the gate electrode formed using the mask having the layout is as shown in FIG.

When the exposure conditions are set so that the dense gate electrodes are finished as designed, the gate length of the isolated gate electrode is longer than Li, and as a result, both gate electrodes are finished to about Lmin.

Here, the Li and Lc will be described. To be precise, the mask skew on the layout in the present invention refers to both the Li-Lmin skew with respect to the isolated gate electrode and the Lc-Lmin skew with respect to the dense gate electrode. In the above embodiment, Li <
Since the case of Lc (Lc = Lmin) is considered, only the isolated gate electrode is subjected to Li-Lc mask skew.

| Li-Lc |, that is, the magnitude of the mask skew on the layout is 1/10 to 7 of the gate length.
One-third is appropriate. The reason for this is that as a result of actual evaluation up to now, the difference in finished dimension between the gate lengths of the isolated gate electrode and the dense gate electrode caused by the proximity effect or the like is about 1/10 to 1/7 of the gate length. (For example, when the gate length is 0.35 μm, the difference in finished dimension is about 0.03 to 0.05 μm.) Further, when the mask skew is about 1/5 or more, the finished shape of the peripheral pattern is affected. And may impair miniaturization.

Further, the mask skew is 0.05.
If the exposure condition is set to about μm and the finished dimensions of both gate electrodes are about the same, there is also an advantage that it can be easily applied to a lithographic technique that has been often used conventionally. The reason will be described below.

A lithographic technique that has been widely used in the past is 5 times reticle (mask) reduction exposure by an i-line stepper, and patterning of the reticle is performed by direct writing with EB or laser. If the minimum grid on the layout is 0.05 μm, then the minimum grid on the reticle is 0.25 μm. The EB direct writing technology has a resolution of about 1/10, but if the minimum grid is smaller than 0.25 μm, not only the reticle manufacturing cost increases but also
There is a problem that the resolution of the i-line stepper cannot keep up, and it does not make much sense. Therefore, considering that the present invention is applied at the conventional mass production technology level and the skew is such that the finished shape of the peripheral pattern is not affected, the skew on the layout is the minimum grid on the layout. It is preferable that the thickness is about 0.05 μm.

Next, the Lmin will be described. The above-mentioned proximity effect is particularly remarkable when the minimum gate length is 0.
It is the deep submicron generation after 5 μm. This is because the lithography technique using the i-line stepper is approaching its limit. Before the submicron generation, the current lithography technology can sufficiently cope with the above problem. Even if the above-described pattern dependency of the gate electrode finish exists, the present invention has a minimum gate length of 0.5 μm, considering that the gate length itself is long. It is especially effective in the following generations.

Embodiment 2 FIG. 2A shows a multi-input circuit in which an isolated transistor and a plurality (three in the figure, but any number) of transistors are connected in series (three in the figure, but any number is possible). It is a layout diagram of (good). Li, Lc, and Ls are the same as in the first embodiment. FIG. 2B is a finished cross-sectional view of a portion corresponding to the XY portion in FIG. 2A in the gate electrode formed using the mask having the layout of FIG. 2A. In these figures, 3 is an element isolation region, and 4 is a contact hole. If the present invention is applied to the circuit configuration shown in FIG. 2A, the circuit configuration shown in FIG.
As shown in, all gate lengths can be finished to Lmin, and high performance and high reliability can be realized.

Embodiment 3 FIG. 3 shows a multi-input NAND circuit (two inputs in the figure,
An example layout is shown. Reference numeral 10 is a P-channel type transistor region, and 11 is an N-channel type transistor region. As can be easily understood from this figure, the gate electrode of the P-channel transistor (10) has a relatively large space between the gate electrodes, and the isolated gate electrode and the gate electrode of the N-channel transistor (11) have a space between the gate electrodes. Can be regarded as a densely packed gate electrode and the actual finished size of the gate electrode is narrower in the N-channel transistor. Therefore, if Li, Lc and Ls are set similarly to the first embodiment and the present invention is applied, the gate lengths of both the P-channel type and N-channel type transistors can be finished to Lmin even in such a circuit, and high performance is achieved. And high reliability can be realized.

Embodiment 4 FIG. 4 shows a layout example of a multi-input NOR circuit (two inputs are shown in the drawing, but any number may be used). As can be easily understood from this figure, the gate electrode of the N-channel transistor (11) has a relatively large space between the gate electrodes, and the isolated gate electrode and the P-channel transistor (1
The gate electrode of 0) has a narrow space between the gate electrodes and can be regarded as a dense gate electrode, and an actual finished size of the gate electrode is narrower in the P-channel transistor. Therefore, if Li, Lc, and Ls are set similarly to the first embodiment and the present invention is applied, the gate lengths of both P-channel type and N-channel type transistors are also set to Lmin in such a circuit.
It is possible to achieve high performance and high reliability.

Embodiment 5 FIG. 5 shows an isolated transistor and an SRAM (Static Ran).
dom access memory) basic memory cell layout is shown. It is assumed that a large number of basic memory cells are densely arranged in the entire SRAM memory cell section. Even in this case, although the form is different from that of the dense gate electrode in the above-mentioned embodiment, it has been confirmed that the gate electrode finish is smaller than that of a normal isolated gate electrode due to a kind of proximity effect. Therefore, if the present invention is applied to such a circuit configuration, the gate length in the memory cell can be reduced to the minimum gate length Lmin of the isolated gate electrode in the same chip.
It can be finished to the same extent as, and high performance and high reliability can be realized. SRAM is shown here, but DR
AM (Dynamic Random Access Memory) and various ROMs
Other memory circuits such as (Read Only Memory) are similar to the SRAM in that the basic cells are densely arranged, and the present invention can be applied.

In the above embodiment, the description was made mainly on the dimension on the layout, but in the case of the dimension on the mask, for example, on the 5 × reticle in the reduction exposure system,
It goes without saying that a size five times larger than the above size is used.
Further, in the above embodiments, the description has been made on the assumption that the resist is a positive type. However, when a negative type resist is used, the method of finishing the dense gate electrodes is the reverse of the above example. May be thicker than the isolated gate electrode. Alternatively, even when the positive type is used, in a place where a plurality of gate electrodes are arranged in fine lines / spaces close to the resolution limit, underexposure may occur depending on the exposure conditions, and the finish of the gate electrode may be thicker. There is also a possibility. Under these conditions, it is easily conceivable to apply a mask skew that makes the isolated gate electrode thicker, contrary to the above embodiment.

What is important in the present invention is that a skew is applied in advance on the layout in consideration of the pattern dependence of the finish of the gate electrode, and the layout dimensions of one gate electrode and another gate electrode are different. Also, it should be clearly stated that when the finished dimensions of both the gate electrodes are similar, it falls within the scope of the present invention.

Further, in the present invention, a method of applying a negative mask skew only to the isolated gate electrode [Li <Lc
(Lc = Lmin)], a method of applying a positive mask skew only to the dense gate electrodes [Lc> Li (Li = Lmin)
)], Or a method of applying a positive mask skew to the dense gate electrodes at the same time as applying a negative mask skew to the isolated gate electrode (Li <Lmin <Lc). In the above-described embodiment, the method of applying the negative mask skew only to the isolated gate electrode has been described, but it is clear that the same effect as in the above-described embodiment can be obtained by adopting any of the above methods. . However, in the case of applying a positive mask skew only to the dense gate electrodes, in a place where a plurality of gate electrodes are arranged with fine lines / spaces, underexposure may occur depending on the exposure conditions, and conversely the finish of the gate electrodes may be poor. Be careful because you may get fat.

Further, in the above-mentioned embodiment, the explanation has been made by using the multi-input circuit or the memory circuit, but the present invention is not limited to the above-mentioned circuit only, and its application range is not limited to the above.
It can be applied to any pattern in which there is a pattern dependency of the finish of the gate electrode.

For example, the pattern dependence of the finish of the gate electrode is not caused only by the proximity effect, but the step dependence of the underlying layer, or the standing wave effect, the lens aberration, etc. in the lithography process may also be the cause of the pattern dependence. For example, a gate array (SOG: Sea Of G
In the case of a pattern such as ates), the phenomenon that the finish is smaller than that of the isolated gate electrode and the arrangement of the P-channel type and N-channel type transistors are symmetrical, although the gap between the gate electrodes is relatively wide. Despite this, a phenomenon in which the finish of the gate electrode is different between both channel type transistors may be seen, and it is difficult to explain it only by the proximity effect. Even in such a case, the present invention of skewing the mask can be easily applied, and
It is effective.

Further, in the above-described embodiment, an example is described in which the finishes between the two types of gate electrodes, that is, the isolated gate electrode and the dense gate electrode, are made to be approximately the same, but a large number of skews of three or more types are varied. Even if the pattern is set according to the finish of the pattern, it does not exceed the scope of the present invention.

Further, the present invention is not limited to the MOS transistor which has been conventionally used, but is applicable to other MISs (Metal-Insulator-Semiconducers).
tor) transistor, SOS (Silicon on Sapphire)
Alternatively, it can be applied to all kinds of insulated gate type transistors having a gate electrode such as an SOI (Silicon on Insulator) type transistor and further a TFT (Thin Film Transistor) and patterning the gate electrode by a lithography process using a mask. In this case, the same effect as that of the above embodiment can be obtained.

[0038]

As is apparent from the above description, the present invention is
By skewing the pattern on the mask in consideration of the finish of the pattern, it is possible to easily and effectively achieve miniaturization, high performance, and high reliability without resorting to new technology. The effects of the present invention will be described below. (1) In the semiconductor device according to claim 1, the mask is preliminarily skewed in consideration of the pattern dependency of the gate length, which is the finished dimension of the gate electrode caused by the proximity effect, etc. The gate length of the internal transistor can be finished to the minimum gate length according to the design rule, and miniaturization, high performance, and high reliability can be realized easily and effectively. (2) In the semiconductor device according to claim 2, the mask skew applied to the gate electrode pattern is 10 which is the minimum gate electrode.
Since it is about one-seventh to one-seventh, it does not affect the finish of the peripheral pattern so much and does not impair the miniaturization. (3) In the semiconductor device according to claim 3, since the mask skew applied to the gate electrode pattern is about 0.05 μm, it does not affect the finish of the peripheral pattern so much, and the i-line which is often used conventionally. Even in the 5 × reticle reduction exposure technique using a stepper, it is possible to easily and effectively realize miniaturization, high performance, and high reliability. (4) In the semiconductor device according to the fourth aspect, it is possible to deal with the case where the gate length is 0.5 μm or less, in which the proximity effect becomes a problem because the pattern dependence of the finish of the gate electrode is the limit of the lithography technique. . (5) In the semiconductor device according to claim 5, the mask is preliminarily skewed by the difference in the finished dimension of the gate length between the isolated gate electrode and the dense gate electrode, which is likely to occur due to the proximity effect or the like. The gate length of the transistor in the chip can be finished to the minimum gate length according to the design rule regardless of the pattern, and miniaturization, high performance, and high reliability can be easily and effectively realized. (6) In the semiconductor device according to claim 6, even in a NAND circuit often used as a logic circuit, the finish of the gate lengths of the P-channel type and N-channel type transistors can be made to be the minimum gate length in design, and the high Performance and high reliability can be realized. (7) In the semiconductor device according to claim 7, even in a NOR circuit often used as a logic circuit, the finish of the gate length of the P-channel type and N-channel type transistors can be made to be the minimum gate length in design, and the high Performance and high reliability can be realized. (8) In the semiconductor device according to claim 8, the finished gate lengths of the transistors in the memory cell in which the fine patterns are densely packed and the isolated transistors in the same chip can be made equal to the designed minimum gate length. , High performance and high reliability can be realized. The present invention can be widely and effectively applied to the technical field of performing fine processing through a lithography process using a mask.

[Brief description of drawings]

1A and 1B relate to Example 1 of the present invention, in which FIG. 1A is a layout view of polysilicon for a gate electrode, and FIG. 1B is a sectional view showing a finished state of a gate electrode.

2A and 2B relate to Example 2 of the present invention, in which FIG. 2A is a layout diagram of a multi-input circuit, and FIG. 2B is a sectional view showing a finished state of a gate electrode.

FIG. 3 is a layout diagram of a multi-input NAND circuit according to a third embodiment of the present invention.

FIG. 4 is a layout diagram of a multi-input NOR circuit according to a fourth embodiment of the present invention.

FIG. 5 is a layout diagram according to a fifth embodiment of the present invention and showing a part of a basic memory cell of an isolated transistor and an SRAM.

6A and 6B are related to a conventional example, FIG. 6A is a layout diagram of a gate electrode, and FIGS. 6B and 6C are cross-sectional views illustrating problems of this layout.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Polysilicon for gate electrode 2 Active region 3 Element isolation region 4 Contact hole 5 Gate insulating film 10 P channel type transistor region 11 N channel type transistor region 21 Gate electrode 22 Active region 23 Gate insulating film Li Gate length of isolated gate electrode Lc Gate length of dense gate electrode Ls Space between dense gate electrodes Lmin Minimum gate length according to design rules

Claims (8)

[Claims] 1. A length in a channel direction in which one or more gate electrodes and one or more other gate electrodes different from the gate electrode are different in layout (hereinafter, referred to as a gate length).
And the finished dimensions of the gate lengths of the both gate electrodes manufactured using a mask having the above-mentioned layout are within the same range. 2. The dimensional difference in the layout of the gate lengths of the two gate electrodes is about 1/10 to 1/7 of the minimum gate length in the same chip, and the short gate length of the gate electrodes. The gate length of the gate electrode having the above is the minimum gate length, and the finished dimension difference between the gate lengths of the both gate electrodes is within a range of 1/10 or more to less than 1/7 of the minimum gate length. The semiconductor device according to claim 1, wherein: 3. The layout size difference of the gate lengths of the two gate electrodes is about 0.05 μm, and the gate length of the gate electrode having the shortest gate length is the minimum gate length in the same chip. 2. The semiconductor device according to claim 1, wherein the difference in finished dimension between the gate lengths of the two gate electrodes is less than 0.05 μm. 4. The semiconductor device according to claim 2, wherein the minimum gate length is 0.5 μm or less. 5. In a multi-input circuit in which a plurality of transistors are connected in series, there is no contact hole between the gate electrodes, and the gate length of the gate electrode in the structure in which a plurality of gates are arranged on the active region is within the same chip. The semiconductor device according to claim 1, wherein the semiconductor device is manufactured using a mask laid out longer than the minimum gate length. 6. The multi-input NAND circuit according to claim 5, wherein the mask is laid out so that the gate length of the N-channel transistor is longer than that of the P-channel transistor. Semiconductor device. 7. The multi-input NOR circuit according to claim 5, wherein the multi-input NOR circuit is manufactured using a mask laid out so that the gate length of the P-channel type transistor is longer than that of the N-channel type transistor. Semiconductor device. 8. A memory circuit configured by arranging a plurality of basic memory cells side by side, using a mask laid out such that the gate length of the memory cell constituent transistors is longer than the minimum gate length in the same chip. The semiconductor device according to claim 1, 2, 3, or 4, wherein