JPH08320676A - Dither image display device - Google Patents

Abstract

PURPOSE: To provide a dither image display device which gives high-quality images with a small amount of hardware and low cost. CONSTITUTION: An adder 11 adds and outputs input image data and fed-back image data. The added image data is halved to that of upper bits and lower bits. Selectors, A12 and B13, multiply the image data of lower bits by 1/1 and 1/2 and select and output either of these. The selected image data is held by buffers, A14 and B15, and further selected and outputted by a buffer C16 to be made the feedback image data for the adder. Selection of image data by the selectors, A12, B13 and C16, is determined by the coordinate values of the image data. Through this, a high-quality dither processing procedure is secured with a lesser amount of buffer capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dither image display device, for example, an image display device having a display quality improved by using a dither method.

[0002]

2. Description of the Related Art Conventionally, there is a dither method as a method of displaying an image of high quality with a frame buffer having a capacity smaller than the information amount of the image to be displayed. This dither method is roughly classified into two methods: an ordered dither method shown in FIG. 3 and an error diffusion method shown in FIG. In these dither methods, a method of processing an image and storing the image from which false contours are removed in a frame buffer is adopted.

In the ordered dither method, a value obtained by adding a predetermined value to the pixel value of the original image is used as the pixel value. The predetermined value added to this pixel value is a constant depending on the pixel coordinate value, and is usually obtained from a matrix having a size of M × N. For example, the value of the matrix (X mod M, Y mod N) is added to the pixel of the coordinate value (X, Y). The ordered dither method has a feature that the amount of hardware is small.

In the other error diffusion method, the lower bits of the pixel information of the original image that cannot be stored in the frame buffer are accumulated, and the lower bits are added before the adjacent pixels are processed. Is updated and then stored in the frame buffer. The direction of propagating the lower bits of the pixel information is usually two directions of up and down or up,
There are four directions: bottom, bottom right and bottom left. This error diffusion method
It has the feature of high image quality.

As a conventional example similar to the technical field of the present invention, Japanese Patent Laid-Open No. 1-267 discloses a technique for compressing input image data using multi-value dither processing and storing it in an image memory.
Japanese Patent Laid-Open No. 63-213084 discloses a technique for converting a digital image signal into a dithered image signal using a dither matrix.

[0006]

However, in the ordered dither method, the size of the matrix is very small compared to the size of the image, so that a specific pattern appears over the entire image and the image quality is low. With problems. On the other hand, the other error diffusion method requires a buffer for storing the lower bits for at least one line of the image, which causes a problem of increasing the amount of hardware.

Incidentally, the above-mentioned conventional example, Japanese Patent Laid-Open No. 1-26778.
No. 2 relates to the application of dither processing, and on the other hand, JP-A-63-213084 differs from the present invention in the constitution of the invention.

An object of the present invention is to provide a dither image display device which can obtain high image quality with a small amount of hardware and a low cost.

[0009]

In order to achieve the above object, the dither image display device of the present invention includes an adding means for adding and outputting input image data and fed-back image data, and an added image added. The data is divided into upper bit and lower bit image data, and the divided lower bit image data is set to 1/1 and 1/2,
1st and 2nd which selects and outputs any one of these
Selection means, first and second buffer means for respectively holding image data output from the two selection means, and 2
A third selecting means for selecting and outputting one of the two image data of one buffer means, and the image data output from the third selecting means is used as feedback image data to the adding means. The feature is that the image data is output image data.

Further, the first, second and third selecting means described above are 2 depending on the coordinate value of the image data input to each.
One of the two inputs may be selected and output.

[0011]

Therefore, according to the dither image display apparatus of the present invention, the input image data and the fed-back image data are added and output, and the added image data is converted into the image data of the upper bits and the lower bits. The image data of the lower bit divided into two is divided into 1/1 and 1
/ 2, and one of these is selected and output. There are two selection outputs, each output image data is held, and the held image data is selected and output. The output image data is fed back to be the above-mentioned added image data. The image data of the upper bits of the added image data is output image data. By this procedure, a processing procedure for high-quality dither processing can be secured with a smaller buffer capacity.

[0012]

Embodiments of the dither image display device according to the present invention will now be described in detail with reference to the accompanying drawings. 1 to 3, there is shown an embodiment of a dither image display device to which the dither image display device of the present invention is applied. FIG. 1 is a circuit configuration block diagram of the dither image processing unit of the present embodiment,
FIG. 2 is a circuit configuration block diagram of a dither image display device including a dither processing unit. Further, FIG. 3 is a time chart showing a data flow in the main part of FIG.

The dither image display device of this embodiment will be described below. The dither processing unit 1 includes an adder 11, buffers A14 and B15, selectors A12, B13, C1.
It is configured to have 6.

The adder 11 is a circuit unit for adding pixel data, and in the present embodiment, a 2-input / 1-output adder is used. Pixel data to this device is input to one of the two input terminals. The output data of the selector C16 is fed back and input to the other input terminal.

The buffers A14 and B15 are temporary storages for holding pixel data. Each buffer A14, B15
Then, the output data selected by the selectors A12 and B13 is held. Since this input hold is held at the falling edge of the sync signal (not shown), it is delayed by one clock as a result.

The selectors A12, B13 and C16 are 2-input / 1-output line selectors. Selector A12, B
Data of 1/2 and 1/1 of the lower bits of the data output from the adder are input to 13 and any one of the data is output. This selection is determined by the X coordinate value and the Y coordinate value of the input data. That is, the selector A1
2 and B13 select the value of 1/2 of the lower bit when the X coordinate of the pixel is 0, and the value of 1/1 of the lower bit in other cases according to the output signal from the X coordinate determiner (not shown). Select a value. The selector C16 selects the value of the buffer A14 when the Y coordinate of the pixel has an even value and the value of the buffer B15 when the Y coordinate of the pixel has an odd value.

FIG. 3 shows a data flow in the main part of the embodiment constituted by the above-mentioned respective parts. In FIG. 3, circled numbers in the uppermost column are timing orders, and vertical columns are identification names of data and the like. That is, a is the X coordinate value, b is the Y coordinate value, c is the input pixel, d is the adder input, and e is the buffer A1.
4 hold data, f holds buffer B15 hold data, g
Is output data of the selector C16, and h is output data of the dither image display device. In FIG. 3, H (X) represents the upper bits of the adder output data, and L (X) represents the lower bits of the adder output data.

The operation of the dither image display device of this embodiment will be described below with reference to FIG. Selectors A12 and B13
Is a half value of the lower bit of the adder output data when the X coordinate value of the pixel by the X coordinate determiner (not shown) is 0;
Select (Pn + An) / 2, L (Pn + An) / 2, and select X
When the coordinate value is other than 0, the lower bit value itself; L
Select (Pn + An).

The buffer A14 inputs the value of the output of the selector A12 when the X coordinate value of the pixel data by the X coordinate determiner and the Y coordinate determiner is 0 or when the Y coordinate value of the pixel data is even and inputs itself. Rewrite the contents of. Further, the buffer B15 inputs the value of the output of the selector B13 when the X coordinate value of the pixel data by the X coordinate determiner and the Y coordinate determiner is 0, or when the Y coordinate value of the pixel data is odd, the buffer B15 itself. Rewrite the contents of. The buffers A14 and B15
Keeps the currently held data if each does not satisfy the above condition.

There is a one-clock delay between the value selected by the selectors A12 and B13 and the data determined and held in the buffers A14 and B15. In these relations in FIG. 3, the respective data represented in the buffer A14 of e and the buffer B15 of f are finalized data in the buffers A14 and B15. Therefore, for example, the value of 1/2 of the lower bit selected by the selector A12 at the coordinate (0,0); L (P0 + A0) / 2 is determined and held in the buffer A14 at the coordinate (1,0). Similarly, at the coordinate (0, 0), the value of 1/2 of the lower bit selected by the selector B13; L (P0 + A0) / 2
Is determined and held in the buffer B15 at the coordinate (1,0).

When the X coordinate value is 0, the selector A12 selects 1/2 of the lower bit. Therefore, the data selected in the columns and in FIG. 3 are held in the buffer A14 in the columns and. When the X coordinate value is other than 0, the lower bit 1/1 is selected. Therefore, the data selected in the column of FIG. 3 is held in the buffer A14 in the column.

Further, the selector B13 selects the lower bit under the same X-coordinate value condition as the selector A, and continuously holds the present holding data when the Y-coordinate value is not an odd number. So, for example, the value selected in the column of FIG.
It is held in the buffer B15 in the column.
The value selected in the column is held in the column, and the value selected in the column is held in the buffer B15 in the column.

The selector C16 selects the output data of the buffer A when the Y coordinate value of the pixel is an even value, which is 0 at the timing and L (P0 + A0) / 2 at the timing.
At timing, L (P1 + A1) is output. Also,
When the Y coordinate value of the pixel is an odd value, the output data of the buffer B15 is selected, L (P2 + B2) is output at the timing, and L (P3 + B3) / 2 is output at the timing.

The output data of the selector C16 is the adder 11
Is input to the other input terminal of and is added to the input pixel data of c. The output data of the adder 11 is h in FIG.

According to the above configuration, high-quality dithering can be realized with a smaller amount of hardware, and a high-quality image can be displayed at low cost.

Although the above-described embodiment is a preferred example of the present invention, the present invention is not limited to this and various modifications can be made without departing from the gist of the present invention.

[0027]

As is apparent from the above description, the dither image display device of the present invention adds the input image data and the fed-back image data, and adds the added image data to the image data of the upper bits and the lower bits. 2 minutes. The image data of the lower bit divided into two is 1/1 and 1
/ 2, and one of these is selected and output. There are two selection outputs, and each output image data is held. One of the held image data is selected and output. The image data selected and output is fed back to be the above-mentioned added image data. The image data of the upper bits of the added image data is the output image data of the dither image display device. According to this procedure, a high-quality dither processing procedure can be secured with a smaller buffer capacity. Therefore, it is possible to display a high-quality image at low cost.

[Brief description of drawings]

FIG. 1 is a circuit configuration block diagram showing an embodiment of a dither processing unit of a dither image display device of the present invention.

FIG. 2 is a block diagram showing an example of the overall configuration of a dither image display device of the present invention.

FIG. 3 is a time chart showing the operation of the dither processing unit in FIG. 1 in tabular form.

FIG. 4 is a block diagram of a configuration example of an image display device according to a conventional ordered dither method.

FIG. 5 is a block diagram of a configuration example of an image display device according to a conventional error diffusion method.

[Explanation of symbols]

 1 Dither Processing Unit 2 Frame Buffer 11 Adder 12 Selector A 13 Selector B 14 Buffer A 15 Buffer B 16 Selector C

Claims (2)

[Claims] 1. Addition means for adding and outputting input image data and fed-back image data; said added image data is divided into upper-order bit image data and lower-order bit image data; The image data of the lower bits are set to 1/1 and 1/2, and the first and second selecting means for selecting and outputting one of them and the image data output from the two selecting means are output. It has first and second buffer means which respectively hold it, and third selecting means which selects and outputs one of the two image data of the two buffer means, and is output from the third selecting means. 2. The dither image display device, wherein the image data is used as feedback image data to the adding means, and the higher-order image data is output image data. 2. The first, second and third selecting means select either one of the two inputs according to the coordinate value of the image data input to each and output the selected one. 1. The dither image display device according to 1.