JPH11283024A - Compression display method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the omission of an image element, to unnecessitate in- data calculation and to simplify a circuit scale by displaying the numbers of the lines and the dots of n-1 in an input video signal as an input signal itself and displaying the numbers of the remaining lines and the dots by generating average value data. SOLUTION: The numbers of the lines and the dots of n-1 in the input video signal are displayed as the input signal itself and the numbers of the remaining lines and the dots are displayed by generating average value data. That is, concerning an inputted line signal, the line signal as the inputted one itself and the line signal generated in average value data are inputted to the selector 52 of a vertical processing part 15. The three lines are selected as they are from among these kinds of input data of the selector 52 by a control signal from a decoding circuit 53, line data generated in average value data are selected concerning the remaining lines and these kinds of line data are written in the memory 25 of a horizontal processing part 16. The same processing is executed concerning a dot signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device having a predetermined number of display pixels (for example, 640.times.480 dots). The present invention relates to a compressed display method for displaying (600 dots) by performing pixel number conversion processing using a digital signal processing technique and a device therefor.

[0002]

2. Description of the Related Art Generally, a plasma display panel (PDP) and a liquid crystal display (LCD) are display devices in which the number of display pixels is fixed, for example, 640 × 480 dots, 800 × 600 dots, or the like. For example, as shown in FIG. 3, the video display device 11 having a display pixel number of 640 × 480 dots and a low resolution is
800 × 60 with higher resolution than the number of displayable pixels of 1
When displaying the video 12 of the video display device 10 of 0 dots, a portion of the video 12 will be missing if left as it is. Such a lack of information is a fatal defect in monitors such as computer images.

Conventionally, when the number of display pixels and the number of pixels of a display video signal are different, the number of pixels of the input video signal in the horizontal and vertical directions is calculated by using digital signal processing, and the number of pixels of the display device is Several methods have been proposed to make the display the same.

An example of a conventional apparatus for compressing 800 × 600 dots to 640 × 480 dots, that is, 4/5 will be described with reference to FIGS. 4 and 5. FIG. This conventional device,
The vertical processing unit 15 includes a vertical processing unit 15, a horizontal processing unit 16, and a control unit 17. The vertical processing unit 15 includes a video input signal input from the video input terminal 13 and a line memory.
The video input signal delayed by 1H by the H delay circuit 18 is sent to the pixel conversion circuit 19, and the horizontal processing unit 16 outputs the video input signal input from the memory 20 and a 1D comprising a DFF (D type flip-flop) and the like. 1 in the delay circuit 23
The video input signal delayed by the clock is sent to the pixel conversion circuit 24.

The pixel conversion circuit 19 and the pixel conversion circuit 24
Are based on the count values of the line counter 21 and the dot counter 26, respectively,
Based on the selection table value (calculation coefficient table value) as shown in FIG. 4B of FIG. 27, a mixture ratio as shown in FIG.
, And the output is = × 1, '= × 3
/ 4 + × １ ／, '= × 1/2 + × 1/2,
An operation is performed on the data such that '= × 1/4 + × 3/4, and stored in the memories 20 and 25, respectively.

[0006] The memories 20 and 25 are stored in a first-out (First)
-In), a first look-out (First-Out) memory, and among the data calculated by the pixel conversion circuits 19 and 24,
The pixel data at the thinning target position is skipped by controlling with the WE signal as shown in FIG. 4 (b) from the conversion tables 22 and 27, and the RE signal as shown in FIG. 4 (c) from the output control circuit 28. , And ',', 'are read out continuously and repeatedly, thereby realizing a conversion process of the number of pixels.

FIG. 6 shows details of the pixel conversion circuit 19 in the conventional vertical processing unit 15 as described above, and FIG. 7 shows its operation. Although not shown, the same applies to the pixel conversion circuit 24 in the conventional horizontal processing unit 16. As shown in FIG. 6, the pixel conversion circuit 19 includes a first
Adder 57, second adder 58, first selector 59, second
It is composed of many circuits such as a selector 60, a first multiplier 61, a second multiplier 62, and a flip-flop circuit 63.

In the circuit described above, the line counter 21 outputs signals STATE0 to ST0 as shown in FIG.
Pulse signals VC2, VC1, and VC0 that determine combination data up to ATE4 are output. In addition, STATE
In the case of 0, the number of lines is reduced from 5 lines to 4 lines, so that interpolation calculation is performed, but writing to the field memory is not performed. The second selector 60 has b as shown in FIG.
A selection signal is input. As shown in FIG.
Each selection signal of (a + b) / 2, a / 2, and b / 2 as shown in (c) is input. The selection signal of (a + b) / 4 as shown in FIG. 7D is input to the flip-flop circuit 63.

The STA is selected by each of the above selection signals.
In TE 1, “′” in FIG. 4A is calculated and stored in the memory 20. Similarly, in STATE2,
4 (a) is calculated and stored in the memory 20, in STATE3, 'in FIG. 4 (a) is calculated and stored in the memory 20, and in STATE4, the value in FIG. 4 (a) is calculated. Stored in the memory 20. Note that, in STATE0, storage in the memory 20 is not performed. In this way, the vertical processing unit 15 thins the number of lines from five to four, and similarly, the horizontal processing unit 16 thins the number of dots from five to four.

[0010]

In the above-described image conversion processing by the conventional compression display method and the conventional apparatus, the number of pixels is reduced as compared with the case where one dot or one line is thinned to convert the number of pixels. It has the advantage of not missing,
Since the original input signal is subjected to arithmetic processing,
There is a problem that the resolution is reduced. In particular, the circuit configuration of the pixel conversion circuit in the vertical processing unit 15 and the horizontal processing unit 16 includes a first adder, a second adder, a first selector,
It is composed of a second selector, a first multiplier, a second multiplier, and a flip-flop circuit, and has a problem of being extremely complicated and expensive.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit which is as simple as possible and has a small circuit size without causing any missing pixels and without performing calculations between data.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a compression display device for displaying an image having a resolution higher than the number of displayable pixels by performing a pixel number conversion process using a digital signal processing technique. And a horizontal processing unit 16 for compressing dot signals.
And a control unit 1 for controlling writing and reading of digital pixel signals of the vertical processing unit 15 and the horizontal processing unit 16.
And the vertical processing unit 15 converts the video signal into 1H
1H delay circuit 18 that delays, adder 51 that generates average value data of the delayed signal and the signal that is not delayed, and selector 52 that selects an array of the signal that is not delayed and the average value data
And a memory 20 for storing the output of the selector 52. The horizontal processing unit 16 includes a 1D delay circuit 23 for delaying the video signal by 1D, and an addition for generating average value data of the delayed signal and the signal not delayed. And a selector 55 for selecting an array of a signal without delay and an average value data, and a memory 25 for storing the output of the selector 55.

As for the input line signal, a line signal as input and a line signal generated as average value data are input to the selector 52. From the input data of the selector 52, the three lines are selected as they are by the control signal from the decode circuit 53, and the rest is selected as the line data ′ generated as the average value data. Line data is written to the memory 25. The same applies to dot signals.

As described above, according to the present invention, the pixel can be controlled only by a very simple delay circuit, an adder, and a control of writing and reading data to and from a memory without having a complicated data operation unit as in the prior art. Conversion is realized.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. In FIG. 1, the video signal input terminal 13
Are connected to the video signal output terminal 14 via the vertical processing unit 15 and the horizontal processing unit 16. The vertical processing unit 15
Are the 1H delay circuit 18, the adder 51, the selector 52, and the advance (First-In), and the prefetch (First-O).
ut), and the horizontal processing unit 16 includes a 1D delay circuit 23, an adder 54, a selector 5
5, first-out (First-In), pre-reading (Firsts)
(T-Out).

A control unit 17 for controlling the vertical processing unit 15 and the horizontal processing unit 16 outputs a control signal for the line counter 21 for counting the number of horizontal lines and the selector 52, and writes and thins out data to the memory 20. , A dot counter 26 for counting the number of dots, a control signal for the selector 55, and a WE signal for controlling writing of data into the memory 25 and thinning out. It comprises a decode circuit 56 and an output control circuit 28 for generating a read enable (RE) signal for continuously reading data written in the memories 20 and 25. The output control circuit 28 converts an image of 800 × 600 dots into 6
When converted to an image of 40 × 480 dots,
When the data is compressed to 4/5 in the vertical and horizontal directions, the period (frequency) of the vertical and horizontal synchronization signals is set to 4/5.

The operation of the above-described configuration will be described with reference to FIG. First, processing of a line signal will be described.
The line signals shown in FIG. 2A input to the video signal input terminal 13 are sequentially sent to one input terminal of the selector 52 as they are. 1H delay circuit 1
8 and the adder 51, '= (+) × 1/2,'
= (+) × １ ／, '= (+) × １ ／,
'= (+) × 1/2,' = (+) × 1/2
An operation is performed on the data such that

The line output of the selector 52 is selected by the control signal from the decode circuit 53 from the data 'セ レ ク タ' of the other input terminal of the selector 52 with the signal shown in FIG. Low of the WE signal shown in d)
During the period, the line data is written into the memory 20 and FIG.
Data (,,, ') is output as in (e). The present invention is not limited to the case shown in FIG. 2 (e), but includes (,,, ') (,,',) (,
',,) (' ,,,)) ,,,,
') Can be selected and stored in the memory 20.

Next, the processing of the dot signal will be described. The data written to the memory 20 is output to the output control circuit 2
8 is continuously read out by the read enable (RE) signal from FIG. 8, and the dot signals shown in FIG.
, Are sequentially sent to one input terminal of the selector 55 as they are. In the 1D delay circuit 23 and the adder 54, '= (+) × 1/2,' = (+) × 1
/ 2, '= (+) × 1/2,' = (+) ×
An operation is performed on the data such that 、, '= (+) × １ ／, and the result is sequentially sent to the other input terminal of the selector 55.

In the selector 55, (,,, '), (,) are provided by a control signal from the decode circuit 56.
',) (,' ,,) (',,,)
One of (,,, ') is selected and stored in the memory 25.

As described above, according to the present invention, the pixel can be controlled only by a very simple delay circuit, an adder, and a control of writing and reading data to and from a memory without having a complicated data operation unit as in the prior art. Conversion is realized. Note that when compressing to 4/5, it is necessary to delay the reading by one line × １ ／ (120 dots) or more in the horizontal direction from the writing so that the reading does not overtake the writing.

[0022]

According to the first aspect of the present invention, the number of n-1 lines and the number of dots of the input video signal are displayed as the input signal, and the remaining number of lines and the number of dots generate average value data. Since the image is displayed by the display, a complicated arithmetic circuit such as a pixel conversion circuit is not required, and the circuit is simplified and can be provided at a low cost.

According to a third aspect of the present invention, there is provided a vertical processing unit 15, a horizontal processing unit 16, and a control unit 17 for controlling writing and reading of these digital pixel signals. The horizontal processing unit 16 includes a circuit 18, an adder 51 that generates average value data, a selector 52 for these signals, and a memory 20. The horizontal processing unit 16 includes a 1D delay circuit 23 and an adder that generates average value data. Since it is composed of the selector 54, the selector 55 for these signals, and the memory 25, it is only necessary to perform a simple arithmetic processing on the original input signal, and it is possible to prevent the resolution from deteriorating.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a compressed display method and apparatus according to the present invention.

FIG. 2 is an operation waveform diagram and an operation explanatory diagram in FIG. 1;

FIG. 3 is an explanatory diagram of a defect that occurs when displaying an image having a higher resolution than the number of displayable pixels.

FIG. 4 is an explanatory diagram for describing a conventional compressed display method and a conventional apparatus when the number of display pixels and the number of pixels of a display video signal are different.

FIG. 5 is a conventional compressed display device for realizing FIG.

6 is a detailed block diagram of a main part of the conventional device of FIG.

FIG. 7 is an operation waveform diagram and an operation explanatory diagram in FIG. 6;

[Explanation of symbols]

10: High-resolution image display device, 11: Low-resolution image display device, 12: Video, 13: Video input terminal, 14
... video output terminal, 15 ... vertical processing unit, 16 ... horizontal processing unit, 17 ... control unit, 18 ... 1H delay circuit, 19 ... pixel conversion circuit, 20 ... memory, 21 ... line counter, 22 ...
Conversion table, 23 1D delay circuit, 24 pixel conversion circuit, 25 memory, 26 dot counter, 27 conversion table, 28 output control circuit, 51 adder, 52
Selector 53 Decoding circuit 54 Adder 55
Selector 56 decoding circuit 57 first adder 5
8 Second adder, 59 First selector, 60 Second selector, 61 First multiplier, 62 Second multiplier, 63 Flip-flop circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/66 H04N 5/66 B

Claims (3)

[Claims] 1. The number of lines and the number of dots of an input video signal;
The number of lines and dots that can be displayed is n × m: (n +
1) A video signal having a relationship of xm (m is the greatest common divisor) is
In a compressed display method for performing display by performing pixel number conversion processing using digital signal processing technology, the number of n-1 lines and the number of dots of an input video signal are displayed as input signals, and the remaining number of lines and dots are displayed. A compression display method, wherein the number is displayed by generating average value data. 2. An input video signal of 600 lines.times.800 dots is compressed into 4 lines.times.4 dots every 5 lines.times.5 dots using a digital signal processing technique, and converted to 480 lines.times.640 dots by a display device. A compressed display method for displaying, wherein 3 lines × 3 dots are displayed as input video signals as they are, and the remaining data is generated and displayed as average value data. 3. A vertical processing unit for compressing a line signal in a compression display device for displaying an image having a resolution higher than the number of displayable pixels by performing a pixel number conversion process using a digital signal processing technique. 15; a horizontal processing unit 16 for compressing dot signals; and a vertical processing unit 15
And a control unit 17 for controlling writing and reading of the digital pixel signal of the horizontal processing unit 16. The vertical processing unit 15 includes a 1H delay circuit 18 for delaying the video signal by 1H.
And an adder 51 for generating average data of the delayed signal and the non-delayed signal, a selector 52 for selecting an array of the non-delayed signal and the averaged data, and a memory 20 for storing an output of the selector 52. The horizontal processing unit 1
6, a 1D delay circuit 23 that delays the video signal by 1D, an adder 54 that generates average value data of the delayed signal and the signal that is not delayed, and a selector 55 that selects an array of the signal that is not delayed and the average value data. And a memory 25 for storing the output of the selector 55.