JPH08316256A - Pressure contact-type semiconductor device - Google Patents
Pressure contact-type semiconductor deviceInfo
- Publication number
- JPH08316256A JPH08316256A JP12461295A JP12461295A JPH08316256A JP H08316256 A JPH08316256 A JP H08316256A JP 12461295 A JP12461295 A JP 12461295A JP 12461295 A JP12461295 A JP 12461295A JP H08316256 A JPH08316256 A JP H08316256A
- Authority
- JP
- Japan
- Prior art keywords
- pressure contact
- semiconductor device
- aluminum
- electrode
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Die Bonding (AREA)
- Thyristors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特に
大電力用半導体装置として有効な圧接半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a pressure contact semiconductor device effective as a high power semiconductor device.
【0002】[0002]
【従来の技術】図3は圧接型半導体装置の概略構成を示
す分解図であって、同図において10は半導体素子で一
例としてのゲートターンオフサイリスタ(以下GTOと
略記する)、21は銅製のアノードキャップ、22は銀
(Ag)箔、23は円板状のモリブデン板、24はクッ
ション部材としてのゴム、25はPPSリング、26は
モリブデン製のリング板、27はリング状の銀箔、27
はセラミックからなる円筒、28は銅カソードブロッ
ク、29はCu−Ni−Coからなるウェルドリング、
30は銅カソードブロック28内に配設されたゲートブ
ロックである。2. Description of the Related Art FIG. 3 is an exploded view showing a schematic structure of a pressure contact type semiconductor device. In FIG. 3, 10 is a semiconductor element, which is a gate turn-off thyristor (hereinafter abbreviated as GTO), and 21 is a copper anode. A cap, 22 is a silver (Ag) foil, 23 is a disc-shaped molybdenum plate, 24 is rubber as a cushion member, 25 is a PPS ring, 26 is a molybdenum ring plate, 27 is a ring-shaped silver foil, 27
Is a cylinder made of ceramic, 28 is a copper cathode block, 29 is a weld ring made of Cu-Ni-Co,
Reference numeral 30 is a gate block arranged in the copper cathode block 28.
【0003】ゲートブロック30は、図4に示すよう
に、PPSカップ31,銅ゲートブロック32,ゲート
リード線33,ステンレス銅板34およびステンレス板
バネ35によって構成されている。As shown in FIG. 4, the gate block 30 is composed of a PPS cup 31, a copper gate block 32, a gate lead wire 33, a stainless copper plate 34 and a stainless plate spring 35.
【0004】一般に、不純物拡散・電極パターン等の形
成を行ったSiウェハの両面に、外部引出電極、および
高熱伝導・応力緩和材としての役割を果すモリブデン板
ではさむ。さらに銅ブロックで両側からはさみ、圧力を
かけて密着させる。この時、銅ブロックとモリブデン板
との間には、銅材とモリブデン板との熱膨張差による悪
影響(応力の発生等)を緩和するために銀箔を介在させ
る。この銅箔は素材上非常にやわらかく、銅ブロックお
よびモリブデン板の初期歪み・表面粗さによって生じる
空間部を埋める効果が有る。また高熱伝導性で有るた
め、介在することにより生じる熱伝導性の劣化はない。Generally, a molybdenum plate that serves as an external extraction electrode and a high thermal conductivity / stress relaxation material is sandwiched between both surfaces of a Si wafer on which impurity diffusion and electrode patterns are formed. Furthermore, it is pinched from both sides with copper blocks and pressure is applied to adhere them. At this time, a silver foil is interposed between the copper block and the molybdenum plate in order to mitigate adverse effects (such as generation of stress) due to the difference in thermal expansion between the copper material and the molybdenum plate. This copper foil is very soft in terms of material and has an effect of filling a space portion caused by initial strain and surface roughness of the copper block and molybdenum plate. Further, since it has high thermal conductivity, there is no deterioration in thermal conductivity caused by the interposition.
【0005】図5はゲートターンオフサイリスタ10の
素子構造を示すもので、同図において11はNベース
層、12はPエミッタ層、13はN+層からなるアノー
ド・ショート層、14は金属層であって、Pエミッタ層
12,アノード・ショート層13および金属層14によ
ってアノード電極部Aが形成される。15はPベース
層、16はNエミッタ層、17a,17bはアルミニウ
ム層、18はSiO2からなる絶縁層、19は絶縁保護
膜としてのポリミド層である。FIG. 5 shows the element structure of the gate turn-off thyristor 10, in which 11 is an N base layer, 12 is a P emitter layer, 13 is an anode / short layer made of an N + layer, and 14 is a metal layer. Therefore, the P emitter layer 12, the anode / short layer 13, and the metal layer 14 form the anode electrode portion A. Reference numeral 15 is a P base layer, 16 is an N emitter layer, 17a and 17b are aluminum layers, 18 is an insulating layer made of SiO 2 , and 19 is a polyimide layer as an insulating protective film.
【0006】図5の半導体素子において、N型結晶Si
上にPベース領域を拡散その他で形成する。その後拡散
窓を設け、Nエミッタ層を形成し、ゲート部分とカソー
ド部分をそれぞれ短絡しないように酸化膜(SiO2)
を形成した後にアルミで外部へ引き出す電極を形成す
る。最後にカソード・ゲート微細パターン部分に、絶縁
保護膜(現在はポリイミド膜)を塗布し、G−K間の絶
縁耐圧の長期的劣化を防ぐ。In the semiconductor device of FIG. 5, N-type crystalline Si
A P base region is formed thereon by diffusion or the like. After that, a diffusion window is provided, an N emitter layer is formed, and an oxide film (SiO 2 ) is formed so that the gate part and the cathode part are not short-circuited.
After forming the electrode, an electrode is formed with aluminum to lead to the outside. Finally, an insulating protective film (currently a polyimide film) is applied to the cathode / gate fine pattern portion to prevent long-term deterioration of the withstand voltage between G and K.
【0007】[0007]
【発明が解決しようとする課題】図6と図7は実際に圧
接した時のウェハ上部の状態を示すもので、20a,2
0bは冷却フィンを示す。FIGS. 6 and 7 show the state of the upper part of the wafer when it is actually pressure-contacted.
0b shows a cooling fin.
【0008】アルミニウム電極部分をモリブデン板で圧
接すると、電極の角部において応力の集中部40が生じ
る。またSiウェハの発熱・冷却に伴い、この部分にか
かる応力は更に増加する。モリブデン板自身の降伏応力
(塑性変形を起こし元の形状に戻らなくなる応力)は非
常に高く、変形することはまずないが、カソードアルミ
ニウム電極の降伏応力は低く、加圧・発熱によって容易
に塑性変形を生じる。When the aluminum electrode portion is pressed against the molybdenum plate, stress concentration portions 40 are generated at the corner portions of the electrode. Further, as the Si wafer is heated and cooled, the stress applied to this portion further increases. The yield stress of the molybdenum plate itself (stress that causes plastic deformation and does not return to its original shape) is extremely low, but it is unlikely to deform, but the yield stress of the cathode aluminum electrode is low, and plastic deformation easily occurs due to pressure and heat generation. Cause
【0009】発熱により塑性変形を生じたアルミニウム
電極は結果的に角がとれた形状になり、冷却時にはこの
部分で隙間を生じる。この発熱・冷却を繰り返すとこの
隙間が徐々に拡大し、結局加圧された状態でもアルミニ
ウム電極パターンの一部が全く接触されなくなる。この
状態では初期状態に比べ、接触面積が小さくなり、電気
特性の劣化をもたらす、またSiウェハから発熱した熱
は、主にアルミニウム電極を通ってモリブデン板・Cu
ブロックに伝導するが、この接触面積の減少に伴い熱伝
導性が悪化し、Si温度が上昇して熱暴走(熱破壊)を
生じる。The aluminum electrode that has been plastically deformed by heat generation has an angular shape as a result, and a gap is formed at this portion during cooling. When this heat generation / cooling is repeated, this gap gradually expands, and eventually the aluminum electrode pattern is not contacted at all even under pressure. In this state, the contact area becomes smaller than that in the initial state, which causes deterioration of electrical characteristics, and the heat generated from the Si wafer mainly passes through the aluminum electrode and the molybdenum plate / Cu.
Although it conducts to the block, the thermal conductivity deteriorates as the contact area decreases, and the Si temperature rises, causing thermal runaway (thermal destruction).
【0010】さらにアルミニウム電極とモリブデン板間
に微小な隙間が生じることにより、この部分でスパーク
(火花)状の電気の流れが生じ易くなる。この現象が生
じると、この隙間部分で瞬間的に温度が上昇し、熱破壊
・アルミニウム電極の溶融が生じる原因となる。Further, since a minute gap is formed between the aluminum electrode and the molybdenum plate, a spark (spark) -like electric current is apt to occur at this portion. When this phenomenon occurs, the temperature instantaneously rises in this gap, which causes thermal destruction and melting of the aluminum electrode.
【0011】本発明は上述の問題点に鑑みてなされたも
ので、その目的は長寿命にして高信頼性の圧接型半導体
装置を提供することである。The present invention has been made in view of the above problems, and an object thereof is to provide a pressure contact type semiconductor device having a long life and high reliability.
【0012】[0012]
【課題を解決するための手段】上記目的を達成するため
に、本発明の圧接型半導体装置は、半導体ウェハの一方
の面に第1の主電極部を有し、他方の面に第2の主電極
部と制御電極部を有する半導体素子の両面にそれぞれ金
属性の第1の圧接板を配設し、これらの第1の圧接板に
それぞれ箔部材を介して金属性の圧接ブロックを配設し
て前記半導体素子をその両面から加圧してなる半導体装
置において、前記第2の主電極部を、絶縁層を介して前
記制御電極部と電気的に絶縁された状態を保ちながらそ
の絶縁層の上部に設けた金属層に結合して構成したこと
を特徴とする。In order to achieve the above object, a pressure contact type semiconductor device of the present invention has a first main electrode portion on one surface of a semiconductor wafer and a second main electrode portion on the other surface. First metal pressure contact plates are arranged on both sides of a semiconductor element having a main electrode part and a control electrode part, and metal pressure contact blocks are arranged on these first pressure contact plates via foil members. In the semiconductor device in which the semiconductor element is pressed from both sides thereof, the second main electrode portion of the insulating layer is maintained while being electrically insulated from the control electrode portion through the insulating layer. It is characterized in that it is configured by being combined with a metal layer provided on the upper part.
【0013】[0013]
【作用】パターンを形成したSiウェハの両面に例えば
モリブデン板(タングステン板でも可)で挟み、さらに
その両側から例えば銀箔(アルミニウムでも可)を介し
Cuブロックで圧接した構造であって、分割されていた
カソード電極を、ゲート電極と電気的に絶縁された状態
を保ちながらその絶縁層の上部で結合し、電極が圧接し
てないことに起因する不均一な電流分布を防ぐ。一層に
まとめたカソード電極を平坦化することで、モリブデン
板との密着性を良くし、かつカソード電極の角部にかか
っていた応力集中部をなくすことができる。The structure has a structure in which molybdenum plates (tungsten plates are also acceptable) are sandwiched between both sides of a patterned Si wafer, and both sides are pressed with Cu blocks via silver foil (aluminum is acceptable). The cathode electrode is bonded to the gate electrode while being electrically insulated from the gate electrode to prevent uneven current distribution due to the electrode not being pressed. By flattening the cathode electrode in a single layer, it is possible to improve the adhesion to the molybdenum plate and to eliminate the stress concentration portion that is applied to the corner portion of the cathode electrode.
【0014】[0014]
【実施例】以下に本発明の実施例を図1〜図5を参照し
ながら説明する。Embodiments of the present invention will be described below with reference to FIGS.
【0015】図1〜図2はそれぞれ本発明の実施例によ
る圧接型半導体装置の主要部を示すもので、これらの図
において図3〜図7の同一又は相当部分には同一符号が
付されている。1 and 2 each show a main part of a pressure contact type semiconductor device according to an embodiment of the present invention. In these figures, the same or corresponding parts in FIGS. 3 to 7 are designated by the same reference numerals. There is.
【0016】同一において、アノード電極部は第1の主
電極部を形成し、アルミニウム電極17aは制御電極部
であるゲート電極部を形成し、アルミニウム電極17b
は第2の主電極部であるカソード電極部を形成する。本
実施例においては、図1に示すように、ポリイミド又は
Si窒化膜からなる絶縁膜19上にアルミニウム膜41
を形成して、各アルミニウム電極17bをアルミニウム
膜41に電気的に接合する。その後、このアルミニウム
膜41の表面の平坦化を行い、モリブデン板22と圧接
する。In the same manner, the anode electrode portion forms the first main electrode portion, the aluminum electrode 17a forms the gate electrode portion which is the control electrode portion, and the aluminum electrode 17b.
Forms a cathode electrode portion which is a second main electrode portion. In this embodiment, as shown in FIG. 1, an aluminum film 41 is formed on the insulating film 19 made of polyimide or Si nitride film.
And each aluminum electrode 17b is electrically joined to the aluminum film 41. After that, the surface of the aluminum film 41 is flattened and pressed against the molybdenum plate 22.
【0017】絶縁層を形成した時に、絶縁膜表面の高さ
とカソード電極の高さがそろわないのが普通で、このま
まスパッタ装置、蒸着装置などでアルミニウム膜を積層
すると図2のようにアルミニウム膜表面に段差部42が
生じる。そこで化学的、機械的研磨・エッチングによ
り、このアルミニウム膜表面またはアルミニウム成膜前
のアルミニウム電極・絶縁膜を平坦化する。When the insulating layer is formed, the height of the surface of the insulating film and the height of the cathode electrode are usually not aligned. If the aluminum film is laminated as it is by a sputtering apparatus, a vapor deposition apparatus or the like, the surface of the aluminum film is as shown in FIG. A step portion 42 is generated at the position. Therefore, the surface of the aluminum film or the aluminum electrode / insulating film before aluminum film formation is planarized by chemical / mechanical polishing / etching.
【0018】絶縁層の上部にアルミニウム電極を全体に
作ることで応力部が広範囲にわたって均一化し、その応
力値も減少する。しかし逆に絶縁膜上に力が加わるた
め、使用する絶縁膜は硬いものでなくてはならない。柔
らかい膜であると圧接時にこの絶縁部が凹み、アルミニ
ウム膜に亀裂が生じる。By forming an aluminum electrode entirely on the insulating layer, the stressed portion is made uniform over a wide range, and the stress value is also reduced. On the contrary, since a force is applied on the insulating film, the insulating film to be used must be hard. If it is a soft film, this insulating portion will be recessed during pressure contact, and a crack will occur in the aluminum film.
【0019】しかし現状で使用しているポリイミド樹脂
は材質的に柔らかく、高圧力の印加に対する耐性をもた
ない可能性が有る。従ってこの絶縁層の材質を例えばS
iN窒化膜、酸化膜、他の絶縁膜との複合層など変える
必要が有る。However, the polyimide resin currently used is soft in material and may not have resistance to application of high pressure. Therefore, the material of this insulating layer is, for example, S
It is necessary to change the iN nitride film, the oxide film, the composite layer with another insulating film, and the like.
【0020】[0020]
【発明の効果】本発明は、上述の如くであって、例え
ば、Siウェハ上のカソード電極パターンを1つにまと
め、平坦化することで、モリブデン板とアルミニウム電
極を圧接した時に接触面積が大幅に増加する。また圧接
時に発生する接触の不均一による電流密度の不均衡を改
善することができる。また、平坦化することによりアル
ミニウム電極部の角に発生する局部的な応力の集中を防
ぐことができ、アルミニウム電極のつぶれを防ぐことが
できる。従って長期動作による素子の劣化が改善され
る。The present invention is as described above. For example, by combining the cathode electrode patterns on the Si wafer into one and flattening it, the contact area when the molybdenum plate and the aluminum electrode are pressure-welded is significantly increased. Increase to. Further, it is possible to improve the imbalance of the current density due to the non-uniformity of the contact that occurs during the pressure welding. Further, by flattening, it is possible to prevent local concentration of stress generated at the corners of the aluminum electrode portion and prevent crushing of the aluminum electrode. Therefore, deterioration of the element due to long-term operation is improved.
【図1】本発明の実施例による圧接型半導体装置の要部
のパターン図。FIG. 1 is a pattern diagram of a main part of a pressure contact type semiconductor device according to an embodiment of the present invention.
【図2】本発明の実施例による圧接型半導体装置の要部
のパターン図。FIG. 2 is a pattern diagram of a main part of a pressure contact type semiconductor device according to an embodiment of the present invention.
【図3】平型圧接構造の半導体装置の分解図。FIG. 3 is an exploded view of a semiconductor device having a flat pressure contact structure.
【図4】図3の半導体装置の一部を拡大した断面図。4 is an enlarged cross-sectional view of a part of the semiconductor device of FIG.
【図5】素子構造の一例を示すゲートターンオフサイリ
スタのパターン図。FIG. 5 is a pattern diagram of a gate turn-off thyristor showing an example of a device structure.
【図6】従来の圧接型半導体装置のパターン図。FIG. 6 is a pattern diagram of a conventional pressure contact type semiconductor device.
【図7】図6の圧接型半導体装置の部分拡大図。7 is a partially enlarged view of the pressure contact type semiconductor device of FIG.
10…ゲートターンオフサイリスタ 15…Pベース層 16…Nエミッタ層 17a,17b…アルミニウム層 18…絶縁層(SiO2) 19…絶縁板(ポリアミド) 23…圧接板(モリブデン板) 41…アルミニウム膜10 ... gate turn-off thyristors 15 ... P base layer 16 ... N emitter layer 17a, 17b ... aluminum layer 18: insulating layer (SiO 2) 19 ... insulating plate (polyamide) 23 ... press-in plate (molybdenum plate) 41 ... aluminum film
Claims (1)
部を有し、他方の面に第2の主電極部と制御電極部を有
する半導体素子の両面にそれぞれ金属性の第1の圧接板
を配設し、これらの第1の圧接板にそれぞれ箔部材を介
して金属性の圧接ブロックを配設して前記半導体素子を
その両面から加圧してなる半導体装置において、前記第
2の主電極部を、絶縁層を介して前記制御電極部と電気
的に絶縁された状態を保ちながらその絶縁層の上部に設
けた金属層に結合して構成したことを特徴とする圧接型
半導体装置。1. A semiconductor element having a first main electrode section on one surface of a semiconductor wafer and a second main electrode section and a control electrode section on the other surface of the semiconductor wafer. In the semiconductor device in which the pressure contact plates are disposed, the metal pressure contact blocks are disposed on the first pressure contact plates via the foil members, and the semiconductor element is pressed from both sides thereof, A pressure contact type semiconductor device, characterized in that the main electrode portion is connected to a metal layer provided on the insulating layer while maintaining a state of being electrically insulated from the control electrode portion via an insulating layer. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12461295A JPH08316256A (en) | 1995-05-24 | 1995-05-24 | Pressure contact-type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12461295A JPH08316256A (en) | 1995-05-24 | 1995-05-24 | Pressure contact-type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08316256A true JPH08316256A (en) | 1996-11-29 |
Family
ID=14889740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12461295A Pending JPH08316256A (en) | 1995-05-24 | 1995-05-24 | Pressure contact-type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08316256A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007288100A (en) * | 2006-04-20 | 2007-11-01 | Mitsubishi Electric Corp | Pressure contact semiconductor device, and its manufacturing method |
JP2012234962A (en) * | 2011-04-28 | 2012-11-29 | Honda Motor Co Ltd | Pressure-welded semiconductor device and manufacturing method therefor |
-
1995
- 1995-05-24 JP JP12461295A patent/JPH08316256A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007288100A (en) * | 2006-04-20 | 2007-11-01 | Mitsubishi Electric Corp | Pressure contact semiconductor device, and its manufacturing method |
JP2012234962A (en) * | 2011-04-28 | 2012-11-29 | Honda Motor Co Ltd | Pressure-welded semiconductor device and manufacturing method therefor |
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